1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) ST-Ericsson SA 2007-2010
4  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
9 #include <linux/platform_data/dma-ste-dma40.h>
30 	u32 l1 = 0; /* src */  in d40_log_cfg()
32 	/* src is mem? -> increase address pos */  in d40_log_cfg()
33 	if (cfg->dir ==  DMA_MEM_TO_DEV ||  in d40_log_cfg()
34 	    cfg->dir ==  DMA_MEM_TO_MEM)  in d40_log_cfg()
37 	/* dst is mem? -> increase address pos */  in d40_log_cfg()
38 	if (cfg->dir ==  DMA_DEV_TO_MEM ||  in d40_log_cfg()
39 	    cfg->dir ==  DMA_MEM_TO_MEM)  in d40_log_cfg()
42 	/* src is hw? -> master port 1 */  in d40_log_cfg()
43 	if (cfg->dir ==  DMA_DEV_TO_MEM ||  in d40_log_cfg()
44 	    cfg->dir ==  DMA_DEV_TO_DEV)  in d40_log_cfg()
47 	/* dst is hw? -> master port 1 */  in d40_log_cfg()
48 	if (cfg->dir ==  DMA_MEM_TO_DEV ||  in d40_log_cfg()
49 	    cfg->dir ==  DMA_DEV_TO_DEV)  in d40_log_cfg()
53 	l3 |= cfg->dst_info.psize << D40_MEM_LCSP3_DCFG_PSIZE_POS;  in d40_log_cfg()
54 	l3 |= d40_width_to_bits(cfg->dst_info.data_width)  in d40_log_cfg()
58 	l1 |= cfg->src_info.psize << D40_MEM_LCSP1_SCFG_PSIZE_POS;  in d40_log_cfg()
59 	l1 |= d40_width_to_bits(cfg->src_info.data_width)  in d40_log_cfg()
69 	u32 src = 0;  in d40_phy_cfg()  local
72 	if ((cfg->dir == DMA_DEV_TO_MEM) ||  in d40_phy_cfg()
73 	    (cfg->dir == DMA_DEV_TO_DEV)) {  in d40_phy_cfg()
75 		src |= BIT(D40_SREG_CFG_MST_POS);  in d40_phy_cfg()
76 		src |= D40_TYPE_TO_EVENT(cfg->dev_type);  in d40_phy_cfg()
78 		if (cfg->src_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)  in d40_phy_cfg()
79 			src |= BIT(D40_SREG_CFG_PHY_TM_POS);  in d40_phy_cfg()
81 			src |= 3 << D40_SREG_CFG_PHY_TM_POS;  in d40_phy_cfg()
83 	if ((cfg->dir == DMA_MEM_TO_DEV) ||  in d40_phy_cfg()
84 	    (cfg->dir == DMA_DEV_TO_DEV)) {  in d40_phy_cfg()
87 		dst |= D40_TYPE_TO_EVENT(cfg->dev_type);  in d40_phy_cfg()
89 		if (cfg->dst_info.flow_ctrl == STEDMA40_NO_FLOW_CTRL)  in d40_phy_cfg()
94 	/* Interrupt on end of transfer for destination */  in d40_phy_cfg()
97 	/* Generate interrupt on error */  in d40_phy_cfg()
98 	src |= BIT(D40_SREG_CFG_EIM_POS);  in d40_phy_cfg()
102 	if (cfg->src_info.psize != STEDMA40_PSIZE_PHY_1) {  in d40_phy_cfg()
103 		src |= BIT(D40_SREG_CFG_PHY_PEN_POS);  in d40_phy_cfg()
104 		src |= cfg->src_info.psize << D40_SREG_CFG_PSIZE_POS;  in d40_phy_cfg()
106 	if (cfg->dst_info.psize != STEDMA40_PSIZE_PHY_1) {  in d40_phy_cfg()
108 		dst |= cfg->dst_info.psize << D40_SREG_CFG_PSIZE_POS;  in d40_phy_cfg()
112 	src |= d40_width_to_bits(cfg->src_info.data_width)  in d40_phy_cfg()
114 	dst |= d40_width_to_bits(cfg->dst_info.data_width)  in d40_phy_cfg()
118 	if (cfg->high_priority) {  in d40_phy_cfg()
119 		src |= BIT(D40_SREG_CFG_PRI_POS);  in d40_phy_cfg()
123 	if (cfg->src_info.big_endian)  in d40_phy_cfg()
124 		src |= BIT(D40_SREG_CFG_LBE_POS);  in d40_phy_cfg()
125 	if (cfg->dst_info.big_endian)  in d40_phy_cfg()
128 	*src_cfg = src;  in d40_phy_cfg()
142 	unsigned int data_width = info->data_width;  in d40_phy_fill_lli()
143 	int psize = info->psize;  in d40_phy_fill_lli()
153 		return -EINVAL;  in d40_phy_fill_lli()
157 		return -EINVAL;  in d40_phy_fill_lli()
160 	lli->reg_elt = (data_size / data_width) << D40_SREG_ELEM_PHY_ECNT_POS;  in d40_phy_fill_lli()
167 		lli->reg_elt |= data_width << D40_SREG_ELEM_PHY_EIDX_POS;  in d40_phy_fill_lli()
170 	lli->reg_ptr = data;  in d40_phy_fill_lli()
171 	lli->reg_cfg = reg_cfg;  in d40_phy_fill_lli()
175 		lli->reg_lnk = BIT(D40_SREG_LNK_PHY_TCP_POS);  in d40_phy_fill_lli()
177 		lli->reg_lnk = next_lli;  in d40_phy_fill_lli()
179 	/* Set/clear interrupt generation on this link item.*/  in d40_phy_fill_lli()
181 		lli->reg_cfg |= BIT(D40_SREG_CFG_TIM_POS);  in d40_phy_fill_lli()
183 		lli->reg_cfg &= ~BIT(D40_SREG_CFG_TIM_POS);  in d40_phy_fill_lli()
186 	 * Post link - D40_SREG_LNK_PHY_PRE_POS = 0  in d40_phy_fill_lli()
200 		seg_max -= max_w;  in d40_seg_size()
235 		size_seg = d40_seg_size(size_rest, info->data_width,  in d40_phy_buf_to_lli()
236 					otherinfo->data_width);  in d40_phy_buf_to_lli()
237 		size_rest -= size_seg;  in d40_phy_buf_to_lli()
291 		if (i == sg_len - 1)  in d40_phy_sg_to_lli()
294 		l_phys = ALIGN(lli_phys + (lli - lli_sg) *  in d40_phy_sg_to_lli()
301 			return -EINVAL;  in d40_phy_sg_to_lli()
314 	bool interrupt = flags & LLI_TERM_INT;  in d40_log_lli_link()  local
318 	if (next != -EINVAL) {  in d40_log_lli_link()
323 	if (interrupt) {  in d40_log_lli_link()
324 		lli_dst->lcsp13 |= D40_MEM_LCSP1_SCFG_TIM_MASK;  in d40_log_lli_link()
325 		lli_dst->lcsp13 |= D40_MEM_LCSP3_DTCP_MASK;  in d40_log_lli_link()
328 	lli_src->lcsp13 = (lli_src->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |  in d40_log_lli_link()
331 	lli_dst->lcsp13 = (lli_dst->lcsp13 & ~D40_MEM_LCSP1_SLOS_MASK) |  in d40_log_lli_link()
342 	writel_relaxed(lli_src->lcsp02, &lcpa[0].lcsp0);  in d40_log_lli_lcpa_write()
343 	writel_relaxed(lli_src->lcsp13, &lcpa[0].lcsp1);  in d40_log_lli_lcpa_write()
344 	writel_relaxed(lli_dst->lcsp02, &lcpa[0].lcsp2);  in d40_log_lli_lcpa_write()
345 	writel_relaxed(lli_dst->lcsp13, &lcpa[0].lcsp3);  in d40_log_lli_lcpa_write()
355 	writel_relaxed(lli_src->lcsp02, &lcla[0].lcsp02);  in d40_log_lli_lcla_write()
356 	writel_relaxed(lli_src->lcsp13, &lcla[0].lcsp13);  in d40_log_lli_lcla_write()
357 	writel_relaxed(lli_dst->lcsp02, &lcla[1].lcsp02);  in d40_log_lli_lcla_write()
358 	writel_relaxed(lli_dst->lcsp13, &lcla[1].lcsp13);  in d40_log_lli_lcla_write()
369 	lli->lcsp13 = reg_cfg;  in d40_log_fill_lli()
372 	lli->lcsp02 = ((data_size / data_width) <<  in d40_log_fill_lli()
378 	lli->lcsp02 |= data & D40_MEM_LCSP0_SPTR_MASK;  in d40_log_fill_lli()
380 	lli->lcsp13 |= data & D40_MEM_LCSP1_SPTR_MASK;  in d40_log_fill_lli()
383 		lli->lcsp13 |= D40_MEM_LCSP1_SCFG_INCR_MASK;  in d40_log_fill_lli()
390 				       u32 lcsp13, /* src or dst*/  in d40_log_buf_to_lli()
402 		size_rest -= size_seg;  in d40_log_buf_to_lli()
421 		      u32 lcsp13, /* src or dst*/  in d40_log_sg_to_lli()