Lines Matching +full:0 +full:x00000bff
26 #define VNMC_REG 0x00 /* Video n Main Control Register */
27 #define VNMS_REG 0x04 /* Video n Module Status Register */
28 #define VNFC_REG 0x08 /* Video n Frame Capture Register */
29 #define VNSLPRC_REG 0x0C /* Video n Start Line Pre-Clip Register */
30 #define VNELPRC_REG 0x10 /* Video n End Line Pre-Clip Register */
31 #define VNSPPRC_REG 0x14 /* Video n Start Pixel Pre-Clip Register */
32 #define VNEPPRC_REG 0x18 /* Video n End Pixel Pre-Clip Register */
33 #define VNIS_REG 0x2C /* Video n Image Stride Register */
34 #define VNMB_REG(m) (0x30 + ((m) << 2)) /* Video n Memory Base m Register */
35 #define VNIE_REG 0x40 /* Video n Interrupt Enable Register */
36 #define VNINTS_REG 0x44 /* Video n Interrupt Status Register */
37 #define VNSI_REG 0x48 /* Video n Scanline Interrupt Register */
38 #define VNMTC_REG 0x4C /* Video n Memory Transfer Control Register */
39 #define VNDMR_REG 0x58 /* Video n Data Mode Register */
40 #define VNDMR2_REG 0x5C /* Video n Data Mode Register 2 */
41 #define VNUVAOF_REG 0x60 /* Video n UV Address Offset Register */
44 #define VNSLPOC_REG 0x1C /* Video n Start Line Post-Clip Register */
45 #define VNELPOC_REG 0x20 /* Video n End Line Post-Clip Register */
46 #define VNSPPOC_REG 0x24 /* Video n Start Pixel Post-Clip Register */
47 #define VNEPPOC_REG 0x28 /* Video n End Pixel Post-Clip Register */
48 #define VNYS_REG 0x50 /* Video n Y Scale Register */
49 #define VNXS_REG 0x54 /* Video n X Scale Register */
50 #define VNC1A_REG 0x80 /* Video n Coefficient Set C1A Register */
51 #define VNC1B_REG 0x84 /* Video n Coefficient Set C1B Register */
52 #define VNC1C_REG 0x88 /* Video n Coefficient Set C1C Register */
53 #define VNC2A_REG 0x90 /* Video n Coefficient Set C2A Register */
54 #define VNC2B_REG 0x94 /* Video n Coefficient Set C2B Register */
55 #define VNC2C_REG 0x98 /* Video n Coefficient Set C2C Register */
56 #define VNC3A_REG 0xA0 /* Video n Coefficient Set C3A Register */
57 #define VNC3B_REG 0xA4 /* Video n Coefficient Set C3B Register */
58 #define VNC3C_REG 0xA8 /* Video n Coefficient Set C3C Register */
59 #define VNC4A_REG 0xB0 /* Video n Coefficient Set C4A Register */
60 #define VNC4B_REG 0xB4 /* Video n Coefficient Set C4B Register */
61 #define VNC4C_REG 0xB8 /* Video n Coefficient Set C4C Register */
62 #define VNC5A_REG 0xC0 /* Video n Coefficient Set C5A Register */
63 #define VNC5B_REG 0xC4 /* Video n Coefficient Set C5B Register */
64 #define VNC5C_REG 0xC8 /* Video n Coefficient Set C5C Register */
65 #define VNC6A_REG 0xD0 /* Video n Coefficient Set C6A Register */
66 #define VNC6B_REG 0xD4 /* Video n Coefficient Set C6B Register */
67 #define VNC6C_REG 0xD8 /* Video n Coefficient Set C6C Register */
68 #define VNC7A_REG 0xE0 /* Video n Coefficient Set C7A Register */
69 #define VNC7B_REG 0xE4 /* Video n Coefficient Set C7B Register */
70 #define VNC7C_REG 0xE8 /* Video n Coefficient Set C7C Register */
71 #define VNC8A_REG 0xF0 /* Video n Coefficient Set C8A Register */
72 #define VNC8B_REG 0xF4 /* Video n Coefficient Set C8B Register */
73 #define VNC8C_REG 0xF8 /* Video n Coefficient Set C8C Register */
76 #define VNCSI_IFMD_REG 0x20 /* Video n CSI2 Interface Mode Register */
84 #define VNMC_INF_YUV8_BT656 (0 << 16)
92 #define VNMC_IM_ODD (0 << 3)
97 #define VNMC_ME (1 << 0)
104 #define VNMS_CA (1 << 0)
108 #define VNFC_S_FRAME (1 << 0)
115 #define VNDMR_A8BIT(n) (((n) & 0xff) << 24)
116 #define VNDMR_A8BIT_MASK (0xff << 24)
121 #define VNDMR_DTMD_ARGB (1 << 0)
122 #define VNDMR_DTMD_YCSEP_420 (3 << 0)
130 #define VNDMR2_VLV(n) ((n & 0xf) << 12)
135 #define VNCSI_IFMD_CSI_CHSEL(n) (((n) & 0xf) << 0)
136 #define VNCSI_IFMD_CSI_CHSEL_MASK 0xf
167 { 0x0000, {
168 0x00000000, 0x00000000, 0x00000000,
169 0x00000000, 0x00000000, 0x00000000,
170 0x00000000, 0x00000000, 0x00000000,
171 0x00000000, 0x00000000, 0x00000000,
172 0x00000000, 0x00000000, 0x00000000,
173 0x00000000, 0x00000000, 0x00000000,
174 0x00000000, 0x00000000, 0x00000000,
175 0x00000000, 0x00000000, 0x00000000 },
177 { 0x1000, {
178 0x000fa400, 0x000fa400, 0x09625902,
179 0x000003f8, 0x00000403, 0x3de0d9f0,
180 0x001fffed, 0x00000804, 0x3cc1f9c3,
181 0x001003de, 0x00000c01, 0x3cb34d7f,
182 0x002003d2, 0x00000c00, 0x3d24a92d,
183 0x00200bca, 0x00000bff, 0x3df600d2,
184 0x002013cc, 0x000007ff, 0x3ed70c7e,
185 0x00100fde, 0x00000000, 0x3f87c036 },
187 { 0x1200, {
188 0x002ffff1, 0x002ffff1, 0x02a0a9c8,
189 0x002003e7, 0x001ffffa, 0x000185bc,
190 0x002007dc, 0x000003ff, 0x3e52859c,
191 0x00200bd4, 0x00000002, 0x3d53996b,
192 0x00100fd0, 0x00000403, 0x3d04ad2d,
193 0x00000bd5, 0x00000403, 0x3d35ace7,
194 0x3ff003e4, 0x00000801, 0x3dc674a1,
195 0x3fffe800, 0x00000800, 0x3e76f461 },
197 { 0x1400, {
198 0x00100be3, 0x00100be3, 0x04d1359a,
199 0x00000fdb, 0x002003ed, 0x0211fd93,
200 0x00000fd6, 0x002003f4, 0x0002d97b,
201 0x000007d6, 0x002ffffb, 0x3e93b956,
202 0x3ff003da, 0x001003ff, 0x3db49926,
203 0x3fffefe9, 0x00100001, 0x3d655cee,
204 0x3fffd400, 0x00000003, 0x3d65f4b6,
205 0x000fb421, 0x00000402, 0x3dc6547e },
207 { 0x1600, {
208 0x00000bdd, 0x00000bdd, 0x06519578,
209 0x3ff007da, 0x00000be3, 0x03c24973,
210 0x3ff003d9, 0x00000be9, 0x01b30d5f,
211 0x3ffff7df, 0x001003f1, 0x0003c542,
212 0x000fdfec, 0x001003f7, 0x3ec4711d,
213 0x000fc400, 0x002ffffd, 0x3df504f1,
214 0x001fa81a, 0x002ffc00, 0x3d957cc2,
215 0x002f8c3c, 0x00100000, 0x3db5c891 },
217 { 0x1800, {
218 0x3ff003dc, 0x3ff003dc, 0x0791e558,
219 0x000ff7dd, 0x3ff007de, 0x05328554,
220 0x000fe7e3, 0x3ff00be2, 0x03232546,
221 0x000fd7ee, 0x000007e9, 0x0143bd30,
222 0x001fb800, 0x000007ee, 0x00044511,
223 0x002fa015, 0x000007f4, 0x3ef4bcee,
224 0x002f8832, 0x001003f9, 0x3e4514c7,
225 0x001f7853, 0x001003fd, 0x3de54c9f },
227 { 0x1a00, {
228 0x000fefe0, 0x000fefe0, 0x08721d3c,
229 0x001fdbe7, 0x000ffbde, 0x0652a139,
230 0x001fcbf0, 0x000003df, 0x0463292e,
231 0x002fb3ff, 0x3ff007e3, 0x0293a91d,
232 0x002f9c12, 0x3ff00be7, 0x01241905,
233 0x001f8c29, 0x000007ed, 0x3fe470eb,
234 0x000f7c46, 0x000007f2, 0x3f04b8ca,
235 0x3fef7865, 0x000007f6, 0x3e74e4a8 },
237 { 0x1c00, {
238 0x001fd3e9, 0x001fd3e9, 0x08f23d26,
239 0x002fbff3, 0x001fe3e4, 0x0712ad23,
240 0x002fa800, 0x000ff3e0, 0x05631d1b,
241 0x001f9810, 0x000ffbe1, 0x03b3890d,
242 0x000f8c23, 0x000003e3, 0x0233e8fa,
243 0x3fef843b, 0x000003e7, 0x00f430e4,
244 0x3fbf8456, 0x3ff00bea, 0x00046cc8,
245 0x3f8f8c72, 0x3ff00bef, 0x3f3490ac },
247 { 0x1e00, {
248 0x001fbbf4, 0x001fbbf4, 0x09425112,
249 0x001fa800, 0x002fc7ed, 0x0792b110,
250 0x000f980e, 0x001fdbe6, 0x0613110a,
251 0x3fff8c20, 0x001fe7e3, 0x04a368fd,
252 0x3fcf8c33, 0x000ff7e2, 0x0343b8ed,
253 0x3f9f8c4a, 0x000fffe3, 0x0203f8da,
254 0x3f5f9c61, 0x000003e6, 0x00e428c5,
255 0x3f1fb07b, 0x000003eb, 0x3fe440af },
257 { 0x2000, {
258 0x000fa400, 0x000fa400, 0x09625902,
259 0x3fff980c, 0x001fb7f5, 0x0812b0ff,
260 0x3fdf901c, 0x001fc7ed, 0x06b2fcfa,
261 0x3faf902d, 0x001fd3e8, 0x055348f1,
262 0x3f7f983f, 0x001fe3e5, 0x04038ce3,
263 0x3f3fa454, 0x001fefe3, 0x02e3c8d1,
264 0x3f0fb86a, 0x001ff7e4, 0x01c3e8c0,
265 0x3ecfd880, 0x000fffe6, 0x00c404ac },
267 { 0x2200, {
268 0x3fdf9c0b, 0x3fdf9c0b, 0x09725cf4,
269 0x3fbf9818, 0x3fffa400, 0x0842a8f1,
270 0x3f8f9827, 0x000fb3f7, 0x0702f0ec,
271 0x3f5fa037, 0x000fc3ef, 0x05d330e4,
272 0x3f2fac49, 0x001fcfea, 0x04a364d9,
273 0x3effc05c, 0x001fdbe7, 0x038394ca,
274 0x3ecfdc6f, 0x001fe7e6, 0x0273b0bb,
275 0x3ea00083, 0x001fefe6, 0x0183c0a9 },
277 { 0x2400, {
278 0x3f9fa014, 0x3f9fa014, 0x098260e6,
279 0x3f7f9c23, 0x3fcf9c0a, 0x08629ce5,
280 0x3f4fa431, 0x3fefa400, 0x0742d8e1,
281 0x3f1fb440, 0x3fffb3f8, 0x062310d9,
282 0x3eefc850, 0x000fbbf2, 0x050340d0,
283 0x3ecfe062, 0x000fcbec, 0x041364c2,
284 0x3ea00073, 0x001fd3ea, 0x03037cb5,
285 0x3e902086, 0x001fdfe8, 0x022388a5 },
287 { 0x2600, {
288 0x3f5fa81e, 0x3f5fa81e, 0x096258da,
289 0x3f3fac2b, 0x3f8fa412, 0x088290d8,
290 0x3f0fbc38, 0x3fafa408, 0x0772c8d5,
291 0x3eefcc47, 0x3fcfa800, 0x0672f4ce,
292 0x3ecfe456, 0x3fefaffa, 0x05531cc6,
293 0x3eb00066, 0x3fffbbf3, 0x047334bb,
294 0x3ea01c77, 0x000fc7ee, 0x039348ae,
295 0x3ea04486, 0x000fd3eb, 0x02b350a1 },
297 { 0x2800, {
298 0x3f2fb426, 0x3f2fb426, 0x094250ce,
299 0x3f0fc032, 0x3f4fac1b, 0x086284cd,
300 0x3eefd040, 0x3f7fa811, 0x0782acc9,
301 0x3ecfe84c, 0x3f9fa807, 0x06a2d8c4,
302 0x3eb0005b, 0x3fbfac00, 0x05b2f4bc,
303 0x3eb0186a, 0x3fdfb3fa, 0x04c308b4,
304 0x3eb04077, 0x3fefbbf4, 0x03f31ca8,
305 0x3ec06884, 0x000fbff2, 0x03031c9e },
307 { 0x2a00, {
308 0x3f0fc42d, 0x3f0fc42d, 0x090240c4,
309 0x3eefd439, 0x3f2fb822, 0x08526cc2,
310 0x3edfe845, 0x3f4fb018, 0x078294bf,
311 0x3ec00051, 0x3f6fac0f, 0x06b2b4bb,
312 0x3ec0185f, 0x3f8fac07, 0x05e2ccb4,
313 0x3ec0386b, 0x3fafac00, 0x0502e8ac,
314 0x3ed05c77, 0x3fcfb3fb, 0x0432f0a3,
315 0x3ef08482, 0x3fdfbbf6, 0x0372f898 },
317 { 0x2c00, {
318 0x3eefdc31, 0x3eefdc31, 0x08e238b8,
319 0x3edfec3d, 0x3f0fc828, 0x082258b9,
320 0x3ed00049, 0x3f1fc01e, 0x077278b6,
321 0x3ed01455, 0x3f3fb815, 0x06c294b2,
322 0x3ed03460, 0x3f5fb40d, 0x0602acac,
323 0x3ef0506c, 0x3f7fb006, 0x0542c0a4,
324 0x3f107476, 0x3f9fb400, 0x0472c89d,
325 0x3f309c80, 0x3fbfb7fc, 0x03b2cc94 },
327 { 0x2e00, {
328 0x3eefec37, 0x3eefec37, 0x088220b0,
329 0x3ee00041, 0x3effdc2d, 0x07f244ae,
330 0x3ee0144c, 0x3f0fd023, 0x07625cad,
331 0x3ef02c57, 0x3f1fc81a, 0x06c274a9,
332 0x3f004861, 0x3f3fbc13, 0x060288a6,
333 0x3f20686b, 0x3f5fb80c, 0x05529c9e,
334 0x3f408c74, 0x3f6fb805, 0x04b2ac96,
335 0x3f80ac7e, 0x3f8fb800, 0x0402ac8e },
337 { 0x3000, {
338 0x3ef0003a, 0x3ef0003a, 0x084210a6,
339 0x3ef01045, 0x3effec32, 0x07b228a7,
340 0x3f00284e, 0x3f0fdc29, 0x073244a4,
341 0x3f104058, 0x3f0fd420, 0x06a258a2,
342 0x3f305c62, 0x3f2fc818, 0x0612689d,
343 0x3f508069, 0x3f3fc011, 0x05728496,
344 0x3f80a072, 0x3f4fc00a, 0x04d28c90,
345 0x3fc0c07b, 0x3f6fbc04, 0x04429088 },
347 { 0x3200, {
348 0x3f00103e, 0x3f00103e, 0x07f1fc9e,
349 0x3f102447, 0x3f000035, 0x0782149d,
350 0x3f203c4f, 0x3f0ff02c, 0x07122c9c,
351 0x3f405458, 0x3f0fe424, 0x06924099,
352 0x3f607061, 0x3f1fd41d, 0x06024c97,
353 0x3f909068, 0x3f2fcc16, 0x05726490,
354 0x3fc0b070, 0x3f3fc80f, 0x04f26c8a,
355 0x0000d077, 0x3f4fc409, 0x04627484 },
357 { 0x3400, {
358 0x3f202040, 0x3f202040, 0x07a1e898,
359 0x3f303449, 0x3f100c38, 0x0741fc98,
360 0x3f504c50, 0x3f10002f, 0x06e21495,
361 0x3f706459, 0x3f1ff028, 0x06722492,
362 0x3fa08060, 0x3f1fe421, 0x05f2348f,
363 0x3fd09c67, 0x3f1fdc19, 0x05824c89,
364 0x0000bc6e, 0x3f2fd014, 0x04f25086,
365 0x0040dc74, 0x3f3fcc0d, 0x04825c7f },
367 { 0x3600, {
368 0x3f403042, 0x3f403042, 0x0761d890,
369 0x3f504848, 0x3f301c3b, 0x0701f090,
370 0x3f805c50, 0x3f200c33, 0x06a2008f,
371 0x3fa07458, 0x3f10002b, 0x06520c8d,
372 0x3fd0905e, 0x3f1ff424, 0x05e22089,
373 0x0000ac65, 0x3f1fe81d, 0x05823483,
374 0x0030cc6a, 0x3f2fdc18, 0x04f23c81,
375 0x0080e871, 0x3f2fd412, 0x0482407c },
377 { 0x3800, {
378 0x3f604043, 0x3f604043, 0x0721c88a,
379 0x3f80544a, 0x3f502c3c, 0x06d1d88a,
380 0x3fb06851, 0x3f301c35, 0x0681e889,
381 0x3fd08456, 0x3f30082f, 0x0611fc88,
382 0x00009c5d, 0x3f200027, 0x05d20884,
383 0x0030b863, 0x3f2ff421, 0x05621880,
384 0x0070d468, 0x3f2fe81b, 0x0502247c,
385 0x00c0ec6f, 0x3f2fe015, 0x04a22877 },
387 { 0x3a00, {
388 0x3f904c44, 0x3f904c44, 0x06e1b884,
389 0x3fb0604a, 0x3f70383e, 0x0691c885,
390 0x3fe07451, 0x3f502c36, 0x0661d483,
391 0x00009055, 0x3f401831, 0x0601ec81,
392 0x0030a85b, 0x3f300c2a, 0x05b1f480,
393 0x0070c061, 0x3f300024, 0x0562047a,
394 0x00b0d867, 0x3f3ff41e, 0x05020c77,
395 0x00f0f46b, 0x3f2fec19, 0x04a21474 },
397 { 0x3c00, {
398 0x3fb05c43, 0x3fb05c43, 0x06c1b07e,
399 0x3fe06c4b, 0x3f902c3f, 0x0681c081,
400 0x0000844f, 0x3f703838, 0x0631cc7d,
401 0x00309855, 0x3f602433, 0x05d1d47e,
402 0x0060b459, 0x3f50142e, 0x0581e47b,
403 0x00a0c85f, 0x3f400828, 0x0531f078,
404 0x00e0e064, 0x3f300021, 0x0501fc73,
405 0x00b0fc6a, 0x3f3ff41d, 0x04a20873 },
407 { 0x3e00, {
408 0x3fe06444, 0x3fe06444, 0x0681a07a,
409 0x00007849, 0x3fc0503f, 0x0641b07a,
410 0x0020904d, 0x3fa0403a, 0x05f1c07a,
411 0x0060a453, 0x3f803034, 0x05c1c878,
412 0x0090b858, 0x3f70202f, 0x0571d477,
413 0x00d0d05d, 0x3f501829, 0x0531e073,
414 0x0110e462, 0x3f500825, 0x04e1e471,
415 0x01510065, 0x3f40001f, 0x04a1f06d },
417 { 0x4000, {
418 0x00007044, 0x00007044, 0x06519476,
419 0x00208448, 0x3fe05c3f, 0x0621a476,
420 0x0050984d, 0x3fc04c3a, 0x05e1b075,
421 0x0080ac52, 0x3fa03c35, 0x05a1b875,
422 0x00c0c056, 0x3f803030, 0x0561c473,
423 0x0100d45b, 0x3f70202b, 0x0521d46f,
424 0x0140e860, 0x3f601427, 0x04d1d46e,
425 0x01810064, 0x3f500822, 0x0491dc6b },
427 { 0x5000, {
428 0x0110a442, 0x0110a442, 0x0551545e,
429 0x0140b045, 0x00e0983f, 0x0531585f,
430 0x0160c047, 0x00c08c3c, 0x0511645e,
431 0x0190cc4a, 0x00908039, 0x04f1685f,
432 0x01c0dc4c, 0x00707436, 0x04d1705e,
433 0x0200e850, 0x00506833, 0x04b1785b,
434 0x0230f453, 0x00305c30, 0x0491805a,
435 0x02710056, 0x0010542d, 0x04718059 },
437 { 0x6000, {
438 0x01c0bc40, 0x01c0bc40, 0x04c13052,
439 0x01e0c841, 0x01a0b43d, 0x04c13851,
440 0x0210cc44, 0x0180a83c, 0x04a13453,
441 0x0230d845, 0x0160a03a, 0x04913c52,
442 0x0260e047, 0x01409838, 0x04714052,
443 0x0280ec49, 0x01208c37, 0x04514c50,
444 0x02b0f44b, 0x01008435, 0x04414c50,
445 0x02d1004c, 0x00e07c33, 0x0431544f },
447 { 0x7000, {
448 0x0230c83e, 0x0230c83e, 0x04711c4c,
449 0x0250d03f, 0x0210c43c, 0x0471204b,
450 0x0270d840, 0x0200b83c, 0x0451244b,
451 0x0290dc42, 0x01e0b43a, 0x0441244c,
452 0x02b0e443, 0x01c0b038, 0x0441284b,
453 0x02d0ec44, 0x01b0a438, 0x0421304a,
454 0x02f0f445, 0x0190a036, 0x04213449,
455 0x0310f847, 0x01709c34, 0x04213848 },
457 { 0x8000, {
458 0x0280d03d, 0x0280d03d, 0x04310c48,
459 0x02a0d43e, 0x0270c83c, 0x04311047,
460 0x02b0dc3e, 0x0250c83a, 0x04311447,
461 0x02d0e040, 0x0240c03a, 0x04211446,
462 0x02e0e840, 0x0220bc39, 0x04111847,
463 0x0300e842, 0x0210b438, 0x04012445,
464 0x0310f043, 0x0200b037, 0x04012045,
465 0x0330f444, 0x01e0ac36, 0x03f12445 },
467 { 0xefff, {
468 0x0340dc3a, 0x0340dc3a, 0x03b0ec40,
469 0x0340e03a, 0x0330e039, 0x03c0f03e,
470 0x0350e03b, 0x0330dc39, 0x03c0ec3e,
471 0x0350e43a, 0x0320dc38, 0x03c0f43e,
472 0x0360e43b, 0x0320d839, 0x03b0f03e,
473 0x0360e83b, 0x0310d838, 0x03c0fc3b,
474 0x0370e83b, 0x0310d439, 0x03a0f83d,
475 0x0370e83c, 0x0300d438, 0x03b0fc3c },
486 for (i = 0; i < ARRAY_SIZE(vin_coeff_set); i++) { in rvin_set_coeff()
500 rvin_write(vin, p_set->coeff_set[0], VNC1A_REG); in rvin_set_coeff()
543 ys = 0; in rvin_crop_scale_comp_gen2()
548 xs = 0; in rvin_crop_scale_comp_gen2()
553 if (xs > 0 && xs < 2048) in rvin_crop_scale_comp_gen2()
565 rvin_write(vin, 0, VNSPPOC_REG); in rvin_crop_scale_comp_gen2()
566 rvin_write(vin, 0, VNSLPOC_REG); in rvin_crop_scale_comp_gen2()
578 0, 0); in rvin_crop_scale_comp_gen2()
741 0x80), VNUVAOF_REG); in rvin_setup()
751 dmr = 0; in rvin_setup()
758 dmr = 0; in rvin_setup()
765 dmr = (vin->alpha ? VNDMR_ABIT : 0) | VNDMR_DTMD_ARGB; in rvin_setup()
774 dmr = 0; in rvin_setup()
777 vin_err(vin, "Invalid pixelformat (0x%x)\n", in rvin_setup()
811 return 0; in rvin_setup()
816 rvin_write(vin, 0, VNIE_REG); in rvin_disable_interrupts()
889 prev = (slot == 0 ? HW_BUFFER_NUM : slot) - 1; in rvin_fill_hw_slot()
922 phys_addr = vb2_dma_contig_plane_dma_addr(&vbuf->vb2_buf, 0); in rvin_fill_hw_slot()
936 for (slot = 0; slot < HW_BUFFER_NUM; slot++) { in rvin_capture_start()
941 for (slot = 0; slot < HW_BUFFER_NUM; slot++) in rvin_capture_start()
957 return 0; in rvin_capture_start()
963 rvin_write(vin, 0, VNFC_REG); in rvin_capture_stop()
981 unsigned int handled = 0; in rvin_irq()
1011 * to capture first from slot 0. in rvin_irq()
1014 if (slot != 0) { in rvin_irq()
1065 for (i = 0; i < HW_BUFFER_NUM; i++) { in return_all_buffers()
1069 for (n = 0; n < i; n++) { in return_all_buffers()
1095 return sizes[0] < vin->format.sizeimage ? -EINVAL : 0; in rvin_queue_setup()
1098 sizes[0] = vin->format.sizeimage; in rvin_queue_setup()
1100 return 0; in rvin_queue_setup()
1108 if (vb2_plane_size(vb, 0) < size) { in rvin_buffer_prepare()
1110 vb2_plane_size(vb, 0), size); in rvin_buffer_prepare()
1114 vb2_set_plane_payload(vb, 0, size); in rvin_buffer_prepare()
1116 return 0; in rvin_buffer_prepare()
1210 return 0; in rvin_mc_validate_format()
1226 return ret == -ENOIOCTLCMD ? 0 : ret; in rvin_set_stream()
1237 return v4l2_subdev_call(sd, video, s_stream, 0); in rvin_set_stream()
1260 ret = 0; in rvin_set_stream()
1294 vin->sequence = 0; in rvin_start_streaming()
1299 rvin_set_stream(vin, 0); in rvin_start_streaming()
1315 int retries = 0; in rvin_stop_streaming()
1352 rvin_set_stream(vin, 0); in rvin_stop_streaming()
1396 for (i = 0; i < HW_BUFFER_NUM; i++) in rvin_dma_register()
1412 if (ret < 0) { in rvin_dma_register()
1425 return 0; in rvin_dma_register()
1447 if (ret < 0) { in rvin_set_channel_routing()
1460 vin_dbg(vin, "Set IFMD 0x%x\n", ifmd); in rvin_set_channel_routing()
1467 return 0; in rvin_set_channel_routing()