Lines Matching full:ppv2
3 * Definitions for Marvell PPv2 network controller for Armada 375 SoC.
472 /* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
509 /* SMI registers. PPv2.2 only, relative to priv->iface_base. */
513 /* TAI registers, PPv2.2 only, relative to priv->iface_base */
585 /* XPCS registers. PPv2.2 only */
596 /* XPCS registers. PPv2.2 only */
603 /* PTP registers. PPv2.2 only */
949 /* On PPv2.2, each "software thread" can access the base
956 /* On PPv2.2, some port control registers are located into the system
1094 * of view. This is specific to PPv2.2.
1212 /* HW TX descriptor for PPv2.1 */
1224 /* HW RX descriptor for PPv2.1 */
1240 /* HW TX descriptor for PPv2.2 */
1252 /* HW RX descriptor for PPv2.2 */