Lines Matching +full:0 +full:x07ffffff
43 static int gvp11_xfer_mask = 0;
59 static int scsi_alloc_out_of_range = 0; in dma_setup()
63 wh->dma_bounce_len = (cmd->SCp.this_residual + 511) & ~0x1ff; in dma_setup()
78 wh->dma_bounce_len = 0; in dma_setup()
102 wh->dma_bounce_len = 0; in dma_setup()
135 bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; in dma_setup()
143 return 0; in dma_setup()
170 wh->dma_bounce_len = 0; in dma_stop()
215 if (q & 0x08) /* bit 3 should always be clear */ in check_wd33c93()
226 if (*scmd_3393 != q) /* and so should the image at 0x1f */ in check_wd33c93()
245 *sasr_3393 = 0x1e; /* this register is unimplemented */ in check_wd33c93()
247 *sasr_3393 = 0x1e; in check_wd33c93()
249 *sasr_3393 = 0x1e; in check_wd33c93()
251 *sasr_3393 = 0x1e; in check_wd33c93()
253 if (qq != q || qq != 0xff) /* should be read only, all 1's */ in check_wd33c93()
263 if (qq != (~q & 0xff)) /* should be read/write */ in check_wd33c93()
267 return 0; in check_wd33c93()
288 if (zorro_resource_len(z) != 0x10000) in gvp11_probe()
312 regs->secret1 = 0; in gvp11_probe()
316 regs->CNTR = 0; in gvp11_probe()
317 regs->BANK = 0; in gvp11_probe()
328 hdata->wh.no_sync = 0xff; in gvp11_probe()
329 hdata->wh.fast = 0; in gvp11_probe()
336 epc = *(unsigned short *)(ZTWO_VADDR(address) + 0x8000); in gvp11_probe()
354 return 0; in gvp11_probe()
370 hdata->regs->CNTR = 0; in gvp11_remove()
384 { ZORRO_PROD_GVP_COMBO_030_R3_SCSI, ~0x00ffffff },
385 { ZORRO_PROD_GVP_SERIES_II, ~0x00ffffff },
386 { ZORRO_PROD_GVP_GFORCE_030_SCSI, ~0x01ffffff },
387 { ZORRO_PROD_GVP_A530_SCSI, ~0x01ffffff },
388 { ZORRO_PROD_GVP_COMBO_030_R4_SCSI, ~0x01ffffff },
389 { ZORRO_PROD_GVP_A1291, ~0x07ffffff },
390 { ZORRO_PROD_GVP_GFORCE_040_SCSI_1, ~0x07ffffff },
391 { 0 }