Lines Matching +full:0 +full:x7000e400
57 #define PMC_CNTRL 0x0
68 #define PMC_WAKE_MASK 0x0c
69 #define PMC_WAKE_LEVEL 0x10
70 #define PMC_WAKE_STATUS 0x14
71 #define PMC_SW_WAKE_STATUS 0x18
72 #define PMC_DPD_PADS_ORIDE 0x1c
75 #define DPD_SAMPLE 0x020
76 #define DPD_SAMPLE_ENABLE BIT(0)
77 #define DPD_SAMPLE_DISABLE (0 << 0)
79 #define PWRGATE_TOGGLE 0x30
82 #define REMOVE_CLAMPING 0x34
84 #define PWRGATE_STATUS 0x38
86 #define PMC_BLINK_TIMER 0x40
87 #define PMC_IMPL_E_33V_PWR 0x40
89 #define PMC_PWR_DET 0x48
98 #define PMC_CPUPWRGOOD_TIMER 0xc8
99 #define PMC_CPUPWROFF_TIMER 0xcc
100 #define PMC_COREPWRGOOD_TIMER 0x3c
101 #define PMC_COREPWROFF_TIMER 0xe0
103 #define PMC_PWR_DET_VALUE 0xe4
105 #define PMC_SCRATCH41 0x140
107 #define PMC_WAKE2_MASK 0x160
108 #define PMC_WAKE2_LEVEL 0x164
109 #define PMC_WAKE2_STATUS 0x168
110 #define PMC_SW_WAKE2_STATUS 0x16c
112 #define PMC_CLK_OUT_CNTRL 0x1a8
113 #define PMC_CLK_OUT_MUX_MASK GENMASK(1, 0)
114 #define PMC_SENSOR_CTRL 0x1b0
118 #define PMC_RST_STATUS_POR 0
125 #define IO_DPD_REQ 0x1b8
126 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
131 #define IO_DPD_STATUS 0x1bc
132 #define IO_DPD2_REQ 0x1c0
133 #define IO_DPD2_STATUS 0x1c4
134 #define SEL_DPD_TIM 0x1c8
136 #define PMC_SCRATCH54 0x258
138 #define PMC_SCRATCH54_ADDR_SHIFT 0
140 #define PMC_SCRATCH55 0x25c
146 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
148 #define GPU_RG_CNTRL 0x2d4
151 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
153 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
154 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
155 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
156 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
157 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
158 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
159 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
161 #define WAKE_AOWAKE_CTRL 0x4f4
162 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
165 #define TEGRA_SMC_PMC 0xc2fffe00
166 #define TEGRA_SMC_PMC_READ 0xaa
167 #define TEGRA_SMC_PMC_WRITE 0xbb
288 .irq = 0, \
426 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0, in tegra_pmc_readl()
427 0, 0, 0, &res); in tegra_pmc_readl()
450 value, 0, 0, 0, 0, &res); in tegra_pmc_writel()
489 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0; in tegra_powergate_state()
491 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0; in tegra_powergate_state()
511 for (i = 0; i < pmc->soc->num_powergates; i++) { in tegra_powergate_lookup()
576 return 0; in tegra114_powergate_set()
597 return 0; in tegra_powergate_set()
620 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL); in __tegra_powergate_remove_clamping()
641 return 0; in __tegra_powergate_remove_clamping()
648 for (i = 0; i < pg->num_clks; i++) in tegra_powergate_disable_clocks()
657 for (i = 0; i < pg->num_clks; i++) { in tegra_powergate_enable_clocks()
663 return 0; in tegra_powergate_enable_clocks()
674 return 0; in tegra210_clk_handle_mbist_war()
689 if (err < 0) in tegra_powergate_power_up()
720 return 0; in tegra_powergate_power_up()
756 return 0; in tegra_powergate_power_down()
796 if (err < 0) { in tegra_genpd_power_off()
927 if (id < 0) in tegra_pmc_cpu_is_powered()
942 if (id < 0) in tegra_pmc_cpu_power_on()
957 if (id < 0) in tegra_pmc_cpu_remove_clamping()
973 if (strcmp(cmd, "recovery") == 0) in tegra_pmc_restart_notify()
976 if (strcmp(cmd, "bootloader") == 0) in tegra_pmc_restart_notify()
979 if (strcmp(cmd, "forced-recovery") == 0) in tegra_pmc_restart_notify()
1006 for (i = 0; i < pmc->soc->num_powergates; i++) { in powergate_show()
1008 if (status < 0) in powergate_show()
1015 return 0; in powergate_show()
1027 return 0; in tegra_powergate_debugfs_init()
1038 if (count == 0) in tegra_powergate_of_get_clks()
1045 for (i = 0; i < count; i++) { in tegra_powergate_of_get_clks()
1055 return 0; in tegra_powergate_of_get_clks()
1080 if (err < 0) { in tegra_powergate_of_get_resets()
1089 if (err < 0) in tegra_powergate_of_get_resets()
1108 int id, err = 0; in tegra_powergate_add()
1116 if (id < 0) { in tegra_powergate_add()
1137 if (err < 0) { in tegra_powergate_add()
1143 if (err < 0) { in tegra_powergate_add()
1156 if (err < 0) { in tegra_powergate_add()
1163 if (err < 0) { in tegra_powergate_add()
1171 return 0; in tegra_powergate_add()
1198 int err = 0; in tegra_powergate_init()
1202 return 0; in tegra_powergate_init()
1206 if (err < 0) { in tegra_powergate_init()
1260 for (i = 0; i < pmc->soc->num_io_pads; i++) in tegra_io_pad_find()
1294 return 0; in tegra_io_pad_get_dpd_register_bit()
1323 return 0; in tegra_io_pad_prepare()
1336 return 0; in tegra_io_pad_poll()
1354 * Returns: 0 on success or a negative error code on failure.
1365 if (err < 0) { in tegra_io_pad_power_enable()
1372 err = tegra_io_pad_poll(pmc, status, mask, 0, 250); in tegra_io_pad_power_enable()
1373 if (err < 0) { in tegra_io_pad_power_enable()
1390 * Returns: 0 on success or a negative error code on failure.
1401 if (err < 0) { in tegra_io_pad_power_disable()
1409 if (err < 0) { in tegra_io_pad_power_disable()
1483 return 0; in tegra_io_pad_set_voltage()
1503 if ((value & BIT(pad->voltage)) == 0) in tegra_io_pad_get_voltage()
1549 unsigned long long rate = 0; in tegra_pmc_enter_suspend_mode()
1566 if (WARN_ON_ONCE(rate == 0)) in tegra_pmc_enter_suspend_mode()
1591 case 0: in tegra_pmc_parse_dt()
1625 pmc->core_osc_time = values[0]; in tegra_pmc_parse_dt()
1650 pmc->lp0_vec_phys = values[0]; in tegra_pmc_parse_dt()
1653 return 0; in tegra_pmc_parse_dt()
1700 pinmux = 0; in tegra_pmc_init_tsense_reset()
1719 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff) in tegra_pmc_init_tsense_reset()
1720 + ((value >> 24) & 0xff); in tegra_pmc_init_tsense_reset()
1721 checksum &= 0xff; in tegra_pmc_init_tsense_reset()
1722 checksum = 0x100 - checksum; in tegra_pmc_init_tsense_reset()
1763 return 0; in tegra_io_pad_pinctrl_get_group_pins()
1790 if (ret < 0) in tegra_io_pad_pinconf_get()
1798 if (ret < 0) in tegra_io_pad_pinconf_get()
1810 return 0; in tegra_io_pad_pinconf_get()
1828 for (i = 0; i < num_configs; ++i) { in tegra_io_pad_pinconf_set()
1854 return 0; in tegra_io_pad_pinconf_set()
1873 return 0; in tegra_pmc_pinctrl_init()
1888 return 0; in tegra_pmc_pinctrl_init()
1928 int err = 0; in tegra_pmc_reset_sysfs_init()
1932 if (err < 0) in tegra_pmc_reset_sysfs_init()
1940 if (err < 0) in tegra_pmc_reset_sysfs_init()
1955 *hwirq = fwspec->param[0]; in tegra_pmc_irq_translate()
1958 return 0; in tegra_pmc_irq_translate()
1968 int err = 0; in tegra_pmc_irq_alloc()
1973 for (i = 0; i < soc->num_wake_events; i++) { in tegra_pmc_irq_alloc()
1979 if (event->id != fwspec->param[0]) in tegra_pmc_irq_alloc()
1985 if (err < 0) in tegra_pmc_irq_alloc()
1990 spec.param[0] = GIC_SPI; in tegra_pmc_irq_alloc()
2001 if (event->gpio.instance != fwspec->param[0] || in tegra_pmc_irq_alloc()
2039 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2040 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2042 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS); in tegra210_pmc_irq_set_wake()
2043 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS); in tegra210_pmc_irq_set_wake()
2060 return 0; in tegra210_pmc_irq_set_wake()
2100 return 0; in tegra210_pmc_irq_set_type()
2113 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq)); in tegra186_pmc_irq_set_wake()
2128 return 0; in tegra186_pmc_irq_set_wake()
2159 return 0; in tegra186_pmc_irq_set_type()
2202 return 0; in tegra_pmc_irq_init()
2212 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node, in tegra_pmc_irq_init()
2219 return 0; in tegra_pmc_irq_init()
2278 return 0; in pmc_clk_mux_set_parent()
2288 return val ? 1 : 0; in pmc_clk_is_enabled()
2307 return 0; in pmc_clk_enable()
2314 pmc_clk_set_state(clk->offs, clk->force_en_shift, 0); in pmc_clk_disable()
2357 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0; in pmc_clk_gate_is_enabled()
2366 return 0; in pmc_clk_gate_enable()
2373 pmc_clk_set_state(gate->offs, gate->shift, 0); in pmc_clk_gate_disable()
2398 init.flags = 0; in tegra_pmc_clk_gate_register()
2433 for (i = 0; i < TEGRA_PMC_CLK_MAX; i++) in tegra_pmc_clock_register()
2436 for (i = 0; i < pmc->soc->num_pmc_clks; i++) { in tegra_pmc_clock_register()
2460 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER); in tegra_pmc_clock_register()
2516 if (err < 0) in tegra_pmc_probe()
2520 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in tegra_pmc_probe()
2591 if (err < 0) in tegra_pmc_probe()
2607 if (err < 0) in tegra_pmc_probe()
2611 if (err < 0) in tegra_pmc_probe()
2622 return 0; in tegra_pmc_probe()
2645 return 0; in tegra_pmc_suspend()
2652 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41); in tegra_pmc_resume()
2654 return 0; in tegra_pmc_resume()
2672 .scratch0 = 0x50,
2673 .dpd_req = 0x1b8,
2674 .dpd_status = 0x1bc,
2675 .dpd2_req = 0x1c0,
2676 .dpd2_status = 0x1c4,
2677 .rst_status = 0x1b4,
2678 .rst_source_shift = 0x0,
2679 .rst_source_mask = 0x7,
2680 .rst_level_shift = 0x0,
2681 .rst_level_mask = 0x0,
2718 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff), in tegra20_pmc_init()
2743 .num_cpu_powergates = 0,
2750 .num_io_pads = 0,
2752 .num_pin_descs = 0,
2759 .num_reset_sources = 0,
2761 .num_reset_levels = 0,
2763 .num_pmc_clks = 0,
2809 .num_io_pads = 0,
2811 .num_pin_descs = 0,
2820 .num_reset_levels = 0,
2864 .num_io_pads = 0,
2866 .num_pin_descs = 0,
2875 .num_reset_levels = 0,
2934 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2990 .num_reset_levels = 0,
3035 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3116 .num_reset_levels = 0,
3126 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3163 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3174 .scratch0 = 0x2000,
3175 .dpd_req = 0x74,
3176 .dpd_status = 0x78,
3177 .dpd2_req = 0x7c,
3178 .dpd2_status = 0x80,
3179 .rst_status = 0x70,
3180 .rst_source_shift = 0x2,
3181 .rst_source_mask = 0x3c,
3182 .rst_level_shift = 0x0,
3183 .rst_level_mask = 0x3,
3196 if (index < 0) { in tegra186_pmc_setup_irq_polarity()
3245 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
3250 .num_powergates = 0,
3252 .num_cpu_powergates = 0,
3275 .num_pmc_clks = 0,
3281 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
3329 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
3340 .scratch0 = 0x2000,
3341 .dpd_req = 0x74,
3342 .dpd_status = 0x78,
3343 .dpd2_req = 0x7c,
3344 .dpd2_status = 0x80,
3345 .rst_status = 0x70,
3346 .rst_source_shift = 0x2,
3347 .rst_source_mask = 0x7c,
3348 .rst_level_shift = 0x0,
3349 .rst_level_mask = 0x3,
3383 .num_powergates = 0,
3385 .num_cpu_powergates = 0,
3408 .num_pmc_clks = 0,
3413 .scratch0 = 0x2000,
3414 .dpd_req = 0,
3415 .dpd_status = 0,
3416 .dpd2_req = 0,
3417 .dpd2_status = 0,
3418 .rst_status = 0x70,
3419 .rst_source_shift = 0x2,
3420 .rst_source_mask = 0xfc,
3421 .rst_level_shift = 0x0,
3422 .rst_level_mask = 0x3,
3450 .num_powergates = 0,
3452 .num_cpu_powergates = 0,
3459 .num_io_pads = 0,
3461 .num_pin_descs = 0,
3472 .num_wake_events = 0,
3475 .num_pmc_clks = 0,
3510 value = saved ^ 0xffffffff; in tegra_pmc_detect_tz_only()
3512 if (value == 0xffffffff) in tegra_pmc_detect_tz_only()
3513 value = 0xdeadbeef; in tegra_pmc_detect_tz_only()
3520 if (value == 0) { in tegra_pmc_detect_tz_only()
3560 regs.start = 0x7000e400; in tegra_pmc_early_init()
3561 regs.end = 0x7000e7ff; in tegra_pmc_early_init()
3570 return 0; in tegra_pmc_early_init()
3577 if (of_address_to_resource(np, 0, ®s) < 0) { in tegra_pmc_early_init()
3598 for (i = 0; i < pmc->soc->num_powergates; i++) in tegra_pmc_early_init()
3613 return 0; in tegra_pmc_early_init()