Lines Matching +full:3 +full:x3
13 #define PMIC_ACCDET_EINT1_IRQ_SHIFT 3
72 #define PMIC_ACCDET_EINT0_MEM_IN_MASK 0x3
78 #define PMIC_ACCDET_EINT1_IRQ_SHIFT 3
183 #define RG_AUDIF_CK_CKSEL_SFT 3
185 #define RG_AUDIF_CK_CKSEL_MASK_SFT (0x1 << 3)
210 #define RG_AUDIF_CK_TSTSEL_SFT 3
212 #define RG_AUDIF_CK_TSTSEL_MASK_SFT (0x1 << 3)
236 #define RG_AUDNCP_RST_SFT 3
238 #define RG_AUDNCP_RST_MASK_SFT (0x1 << 3)
299 #define DMIC_LOW_POWER_MODE_CTL_MASK 0x3
300 #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
330 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK 0x3
331 #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT (0x3 << 14)
352 #define ADDA6_UL_SINE_ON_SFT 3
354 #define ADDA6_UL_SINE_ON_MASK_SFT (0x1 << 3)
378 #define PDN_I2S_DL_CTL_SFT 3
380 #define PDN_I2S_DL_CTL_MASK_SFT (0x1 << 3)
393 #define AUDIO_SYS_TOP_MON_SWAP_MASK 0x3
394 #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT (0x3 << 14)
433 #define CCI_AUD_SDM_MUTEL_SFT 3
435 #define CCI_AUD_SDM_MUTEL_MASK_SFT (0x1 << 3)
464 #define CCI_AUDIO_FIFO_ENABLE_SFT 3
466 #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT (0x1 << 3)
507 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
509 #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
530 #define R_AUD_DAC_POS_TINY_MONO_MASK 0x3
531 #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT (0x3 << 6)
533 #define R_AUD_DAC_NEG_TINY_MONO_MASK 0x3
534 #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT (0x3 << 4)
535 #define R_AUD_DAC_MONO_SEL_SFT 3
537 #define R_AUD_DAC_MONO_SEL_MASK_SFT (0x1 << 3)
564 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_SFT 3
566 #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT (0x1 << 3)
616 #define CCI_AUD_SDM_MUTEL_2ND_SFT 3
618 #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT (0x1 << 3)
647 #define CCI_AUDIO_FIFO_ENABLE_2ND_SFT 3
649 #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT (0x1 << 3)
797 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK 0x3
798 #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT (0x3 << 6)
805 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_SFT 3
807 #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT (0x1 << 3)
828 #define RG_MTKAIF_RXIF_DETECT_ON_SFT 3
830 #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT (0x1 << 3)
873 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT 3
875 #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT (0x1 << 3)
915 #define R_AUD_SDM_MUTE_L_2ND_SFT 3
917 #define R_AUD_SDM_MUTE_L_2ND_MASK_SFT (0x1 << 3)
960 #define DCCLK_REF_CK_SEL_MASK 0x3
961 #define DCCLK_REF_CK_SEL_MASK_SFT (0x3 << 2)
971 #define RESYNC_SRC_SEL_MASK 0x3
972 #define RESYNC_SRC_SEL_MASK_SFT (0x3 << 10)
1063 #define RG_AMIC_ADC1_SOURCE_SEL_MASK 0x3
1064 #define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 10)
1066 #define RG_AMIC_ADC2_SOURCE_SEL_MASK 0x3
1067 #define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 8)
1069 #define RG_AMIC_ADC3_SOURCE_SEL_MASK 0x3
1070 #define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 6)
1072 #define RG_DMIC_ADC1_SOURCE_SEL_MASK 0x3
1073 #define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT (0x3 << 4)
1075 #define RG_DMIC_ADC2_SOURCE_SEL_MASK 0x3
1076 #define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT (0x3 << 2)
1078 #define RG_DMIC_ADC3_SOURCE_SEL_MASK 0x3
1079 #define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT (0x3 << 0)
1094 #define RG_ADDA6_CH2_SEL_MASK 0x3
1095 #define RG_ADDA6_CH2_SEL_MASK_SFT (0x3 << 10)
1097 #define RG_ADDA6_CH1_SEL_MASK 0x3
1098 #define RG_ADDA6_CH1_SEL_MASK_SFT (0x3 << 8)
1103 #define RG_ADDA_CH2_SEL_MASK 0x3
1104 #define RG_ADDA_CH2_SEL_MASK_SFT (0x3 << 2)
1106 #define RG_ADDA_CH1_SEL_MASK 0x3
1107 #define RG_ADDA_CH1_SEL_MASK_SFT (0x3 << 0)
1163 #define RG_AUDPREAMPLPGATEST_SFT 3
1165 #define RG_AUDPREAMPLPGATEST_MASK_SFT (0x1 << 3)
1167 #define RG_AUDPREAMPLVSCALE_MASK 0x3
1168 #define RG_AUDPREAMPLVSCALE_MASK_SFT (0x3 << 4)
1170 #define RG_AUDPREAMPLINPUTSEL_MASK 0x3
1171 #define RG_AUDPREAMPLINPUTSEL_MASK_SFT (0x3 << 6)
1182 #define RG_AUDADCLINPUTSEL_MASK 0x3
1183 #define RG_AUDADCLINPUTSEL_MASK_SFT (0x3 << 13)
1195 #define RG_AUDPREAMPRPGATEST_SFT 3
1197 #define RG_AUDPREAMPRPGATEST_MASK_SFT (0x1 << 3)
1199 #define RG_AUDPREAMPRVSCALE_MASK 0x3
1200 #define RG_AUDPREAMPRVSCALE_MASK_SFT (0x3 << 4)
1202 #define RG_AUDPREAMPRINPUTSEL_MASK 0x3
1203 #define RG_AUDPREAMPRINPUTSEL_MASK_SFT (0x3 << 6)
1214 #define RG_AUDADCRINPUTSEL_MASK 0x3
1215 #define RG_AUDADCRINPUTSEL_MASK_SFT (0x3 << 13)
1227 #define RG_AUDPREAMP3PGATEST_SFT 3
1229 #define RG_AUDPREAMP3PGATEST_MASK_SFT (0x1 << 3)
1231 #define RG_AUDPREAMP3VSCALE_MASK 0x3
1232 #define RG_AUDPREAMP3VSCALE_MASK_SFT (0x3 << 4)
1234 #define RG_AUDPREAMP3INPUTSEL_MASK 0x3
1235 #define RG_AUDPREAMP3INPUTSEL_MASK_SFT (0x3 << 6)
1246 #define RG_AUDADC3INPUTSEL_MASK 0x3
1247 #define RG_AUDADC3INPUTSEL_MASK_SFT (0x3 << 13)
1259 #define RG_AUDADC1STSTAGELPEN_SFT 3
1261 #define RG_AUDADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
1269 #define RG_AUDPREAMPIDDTEST_MASK 0x3
1270 #define RG_AUDPREAMPIDDTEST_MASK_SFT (0x3 << 6)
1272 #define RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
1273 #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
1275 #define RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
1276 #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
1278 #define RG_AUDADCREFBUFIDDTEST_MASK 0x3
1279 #define RG_AUDADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
1281 #define RG_AUDADCFLASHIDDTEST_MASK 0x3
1282 #define RG_AUDADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
1294 #define RG_AUDRADC1STSTAGELPEN_SFT 3
1296 #define RG_AUDRADC1STSTAGELPEN_MASK_SFT (0x1 << 3)
1304 #define RG_AUDRPREAMPIDDTEST_MASK 0x3
1305 #define RG_AUDRPREAMPIDDTEST_MASK_SFT (0x3 << 6)
1307 #define RG_AUDRADC1STSTAGEIDDTEST_MASK 0x3
1308 #define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT (0x3 << 8)
1310 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK 0x3
1311 #define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT (0x3 << 10)
1313 #define RG_AUDRADCREFBUFIDDTEST_MASK 0x3
1314 #define RG_AUDRADCREFBUFIDDTEST_MASK_SFT (0x3 << 12)
1316 #define RG_AUDRADCFLASHIDDTEST_MASK 0x3
1317 #define RG_AUDRADCFLASHIDDTEST_MASK_SFT (0x3 << 14)
1324 #define RG_AUDADCCLKSEL_MASK 0x3
1325 #define RG_AUDADCCLKSEL_MASK_SFT (0x3 << 1)
1326 #define RG_AUDADCCLKSOURCE_SFT 3
1327 #define RG_AUDADCCLKSOURCE_MASK 0x3
1328 #define RG_AUDADCCLKSOURCE_MASK_SFT (0x3 << 3)
1330 #define RG_AUDADCCLKGENMODE_MASK 0x3
1331 #define RG_AUDADCCLKGENMODE_MASK_SFT (0x3 << 5)
1358 #define RG_AUDADCFSRESET_SFT 3
1360 #define RG_AUDADCFSRESET_MASK_SFT (0x1 << 3)
1377 #define RG_AUDADCDACIDDTEST_MASK 0x3
1378 #define RG_AUDADCDACIDDTEST_MASK_SFT (0x3 << 9)
1454 #define RG_AUDENC_SPARE2_SFT 3
1456 #define RG_AUDENC_SPARE2_MASK_SFT (0x1fff << 3)
1463 #define RG_AUDDIGMICBIAS_MASK 0x3
1464 #define RG_AUDDIGMICBIAS_MASK_SFT (0x3 << 1)
1465 #define RG_DMICHPCLKEN_SFT 3
1467 #define RG_DMICHPCLKEN_MASK_SFT (0x1 << 3)
1469 #define RG_AUDDIGMICPDUTY_MASK 0x3
1470 #define RG_AUDDIGMICPDUTY_MASK_SFT (0x3 << 4)
1472 #define RG_AUDDIGMICNDUTY_MASK 0x3
1473 #define RG_AUDDIGMICNDUTY_MASK_SFT (0x3 << 6)
1486 #define RG_AUDDIGMICBIAS1_MASK 0x3
1487 #define RG_AUDDIGMICBIAS1_MASK_SFT (0x3 << 1)
1488 #define RG_DMIC1HPCLKEN_SFT 3
1490 #define RG_DMIC1HPCLKEN_MASK_SFT (0x1 << 3)
1492 #define RG_AUDDIGMIC1PDUTY_MASK 0x3
1493 #define RG_AUDDIGMIC1PDUTY_MASK_SFT (0x3 << 4)
1495 #define RG_AUDDIGMIC1NDUTY_MASK 0x3
1496 #define RG_AUDDIGMIC1NDUTY_MASK_SFT (0x3 << 6)
1517 #define RG_AUDPWDBMICBIAS3_SFT 3
1519 #define RG_AUDPWDBMICBIAS3_MASK_SFT (0x1 << 3)
1607 #define RG_AUDACCDETVIN1PULLLOW_SFT 3
1609 #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT (0x1 << 3)
1692 #define RG_EINT0CEN_SFT 3
1694 #define RG_EINT0CEN_MASK_SFT (0x1 << 3)
1743 #define RG_AUDIO_VOW_EN_SFT 3
1745 #define RG_AUDIO_VOW_EN_MASK_SFT (0x1 << 3)
1769 #define RG_AUD_DAC_PWL_UP_VA32_SFT 3
1771 #define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT (0x1 << 3)
1785 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK 0x3
1786 #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 8)
1788 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK 0x3
1789 #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 10)
1813 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_SFT 3
1815 #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT (0x1 << 3)
1889 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK 0x3
1890 #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT (0x3 << 12)
1911 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK 0x3
1912 #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
1946 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK 0x3
1947 #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT (0x3 << 2)
1984 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK 0x3
1985 #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK_SFT (0x3 << 4)
1990 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK 0x3
1991 #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 8)
1993 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK 0x3
1994 #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK_SFT (0x3 << 10)
2019 #define RG_AUDZCDCLKSEL_VAUDP32_SFT 3
2021 #define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT (0x1 << 3)
2082 #define RG_AUDZCDGAINSTEPSIZE_MASK 0x3
2083 #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT (0x3 << 4)
2365 #define DRBIAS_HS_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 3)
2369 #define IBIAS_MASK 0x3
2420 MUX_MIC_TYPE_2, /* ain2/3, micbias 2 */
2457 RCV_MUX_MASK = 0x3,
2465 LO_MUX_MASK = 0x3,
2613 /* PGA 3 MUX */