Lines Matching full:cpu4
182 Note that cpu4 in this example is 99.99% busy, while the other CPUs are all under 1% busy.
183 Notice that cpu4's HT sibling is cpu0, which is under 1% busy, but can get into CPU%c1 only,
184 because its cpu4's activity on shared hardware keeps it from entering a deeper C-state.
196 cpu4: MSR_IA32_MISC_ENABLE: 0x00850089 (TCC EIST No-MWAIT PREFETCH TURBO)
198 cpu4: MSR_MISC_PWR_MGMT: 0x00400000 (ENable-EIST_Coordination DISable-EPB DISable-OOB)
200 cpu4: MSR_PLATFORM_INFO: 0x80838f3012300
203 cpu4: MSR_IA32_POWER_CTL: 0x0004005d (C1E auto-promotion: DISabled)
204 cpu4: MSR_TURBO_RATIO_LIMIT: 0x25262727
209 cpu4: MSR_CONFIG_TDP_NOMINAL: 0x00000023 (base_ratio=35)
210 cpu4: MSR_CONFIG_TDP_LEVEL_1: 0x00000000 ()
211 cpu4: MSR_CONFIG_TDP_LEVEL_2: 0x00000000 ()
212 cpu4: MSR_CONFIG_TDP_CONTROL: 0x80000000 ( lock=1)
213 cpu4: MSR_TURBO_ACTIVATION_RATIO: 0x00000000 (MAX_NON_TURBO_RATIO=0 lock=0)
214 cpu4: MSR_PKG_CST_CONFIG_CONTROL: 0x1e000400 (UNdemote-C3, UNdemote-C1, demote-C3, demote-C1, UNloc…
215 cpu4: POLL: CPUIDLE CORE POLL IDLE
216 cpu4: C1: MWAIT 0x00
217 cpu4: C1E: MWAIT 0x01
218 cpu4: C3: MWAIT 0x10
219 cpu4: C6: MWAIT 0x20
220 cpu4: C7s: MWAIT 0x32
221 cpu4: MSR_MISC_FEATURE_CONTROL: 0x00000000 (L2-Prefetch L2-Prefetch-pair L1-Prefetch L1-IP-Prefetch)
243 cpu4: MSR_PKGC3_IRTL: 0x00008842 (valid, 67584 ns)
244 cpu4: MSR_PKGC6_IRTL: 0x00008873 (valid, 117760 ns)
245 cpu4: MSR_PKGC7_IRTL: 0x00008891 (valid, 148480 ns)