Lines Matching full:bandwidth
25 MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local"
26 MBA (Memory Bandwidth Allocation) "mba"
27 SMBA (Slow Memory Bandwidth Allocation) ""
28 BMEC (Bandwidth Monitoring Event Configuration) ""
48 bandwidth in MBps
128 Memory bandwidth(MB) subdirectory contains the following files
132 The minimum memory bandwidth percentage which
136 The granularity in which the memory bandwidth
140 available bandwidth control steps are:
151 request different memory bandwidth percentages:
157 bandwidth percentages are directly applied to
178 If the system supports Bandwidth Monitoring Event
179 Configuration (BMEC), then the bandwidth events will
191 and mbm_local_bytes events, respectively, when the Bandwidth
195 changed, the bandwidth counters for all RMIDs of both events
455 Memory bandwidth Allocation and monitoring
458 For Memory bandwidth resource, by default the user controls the resource
459 by indicating the percentage of total memory bandwidth.
461 The minimum bandwidth percentage value for each cpu model is predefined
462 and can be looked up through "info/MB/min_bandwidth". The bandwidth
464 be looked up at "info/MB/bandwidth_gran". The available bandwidth
468 The bandwidth throttling is a core specific mechanism on some of Intel
469 SKUs. Using a high bandwidth and a low bandwidth setting on two threads
471 low bandwidth (see "thread_throttle_mode").
473 The fact that Memory bandwidth allocation(MBA) may be a core
474 specific mechanism where as memory bandwidth monitoring(MBM) is done at
476 via the MBA and then monitor the bandwidth to see if the controls are
479 1. User may *not* see increase in actual bandwidth when percentage
482 This can occur when aggregate L2 external bandwidth is more than L3
483 external bandwidth. Consider an SKL SKU with 24 cores on a package and
484 where L2 external is 10GBps (hence aggregate L2 external bandwidth is
485 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
486 threads, having 50% bandwidth, each consuming 5GBps' consumes the max L3
487 bandwidth of 100GBps although the percentage value specified is only 50%
488 << 100%. Hence increasing the bandwidth percentage will not yield any
489 more bandwidth. This is because although the L2 external bandwidth still
490 has capacity, the L3 external bandwidth is fully used. Also note that
493 2. Same bandwidth percentage may mean different actual bandwidth
496 For the same SKU in #1, a 'single thread, with 10% bandwidth' and '4
497 thread, with 10% bandwidth' can consume upto 10GBps and 40GBps although
498 they have same percentage bandwidth of 10%. This is simply because as
499 threads start using more cores in an rdtgroup, the actual bandwidth may
500 increase or vary although user specified bandwidth percentage is same.
503 resctrl added support for specifying the bandwidth in MBps as well. The
505 Controller(mba_sc)" which reads the actual bandwidth using MBM counters
506 and adjust the memory bandwidth percentages to ensure::
508 "actual bandwidth < user specified bandwidth".
510 By default, the schemata would take the bandwidth percentage values
542 Memory bandwidth Allocation (default mode)
550 Memory bandwidth Allocation specified in MBps
553 Memory bandwidth domain is L3 cache.
558 Slow Memory Bandwidth Allocation (SMBA)
560 AMD hardware supports Slow Memory Bandwidth Allocation (SMBA).
562 support of SMBA, the hardware enables bandwidth allocation on
571 The bandwidth domain for slow memory is L3 cache. Its schemata file
594 Reading the schemata file will show the current bandwidth limit on all
597 configure the bandwidth limit.
819 for cache bit masks, minimum b/w of 10% with a memory bandwidth
924 50% of the L3 cache on socket 0, and 50% of memory bandwidth on socket 0
930 to the "top" 50% of the cache on socket 0 and 50% of memory bandwidth on
939 also get 50% of memory bandwidth assuming that the cores 4-7 are SMT
1366 Intel MBM Counters May Report System Memory Bandwidth Incorrectly
1371 Problem: Intel Memory Bandwidth Monitoring (MBM) counters track metrics
1374 metrics, may report incorrect system bandwidth for certain RMID values.
1376 Implication: Due to the errata, system memory bandwidth may not match