1 // SPDX-License-Identifier: GPL-2.0-only
3  * arch/arm/mm/cache-tauros2.c - Tauros2 L2 cache controller support
8  * - PJ1 CPU Core Datasheet,
9  *   Document ID MV-S104837-01, Rev 0.7, January 24 2008.
10  * - PJ4 CPU Core Datasheet,
11  *   Document ID MV-S105190-00, Rev 0.7, March 14 2008.
20 #include <asm/hardware/cache-tauros2.h>
29  * When Tauros2 is used on a CPU that supports the v7 hierarchical
30  * cache operations, the cache handling code in proc-v7.S takes care
34  * being used on a pre-v7 CPU, and we only need to build support for
36  * configured to support a pre-v7 CPU.
40  * Low-level cache maintenance operations.
44 	__asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr));  in tauros2_clean_pa()
49 	__asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr));  in tauros2_clean_inv_pa()
54 	__asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr));  in tauros2_inv_pa()
71 	if (start & (CACHE_LINE_SIZE - 1)) {  in tauros2_inv_range()
72 		tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));  in tauros2_inv_range()
73 		start = (start | (CACHE_LINE_SIZE - 1)) + 1;  in tauros2_inv_range()
79 	if (end & (CACHE_LINE_SIZE - 1)) {  in tauros2_inv_range()
80 		tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));  in tauros2_inv_range()
81 		end &= ~(CACHE_LINE_SIZE - 1);  in tauros2_inv_range()
97 	start &= ~(CACHE_LINE_SIZE - 1);  in tauros2_clean_range()
108 	start &= ~(CACHE_LINE_SIZE - 1);  in tauros2_flush_range()
124 	: : "r" (0x0));  in tauros2_disable()
134 	: : "r" (0x0));  in tauros2_resume()
142 	__asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));  in read_extra_features()
149 	__asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));  in write_extra_features()
161 	__asm__("mrc p15, 0, %0, c0, c1, 7\n" : "=r" (mmfr3));  in read_mmfr3()
170 	__asm__("mrc p15, 0, %0, c1, c0, 1\n" : "=r" (actlr));  in read_actlr()
177 	__asm__("mcr p15, 0, %0, c1, c0, 1\n" : : "r" (actlr));  in write_actlr()
236 	 * Check whether this CPU has support for the v7 hierarchical  in tauros2_internal_init()
237 	 * cache ops.  (PJ4 is in its v7 personality mode if the MMFR3  in tauros2_internal_init()
238 	 * register indicates support for the v7 hierarchical cache  in tauros2_internal_init()
242 	 * implement the v7 cache ops but are only ARMv6 CPUs (due to  in tauros2_internal_init()
244 	 * there are no real-life examples of Tauros2 being used on  in tauros2_internal_init()
254 		 * ARMv7 spec to contain fine-grained cache control bits).  in tauros2_internal_init()
277 	{ .compatible = "marvell,tauros2-cache"},
291 		pr_info("Not found marvell,tauros2-cache, disable it\n");  in tauros2_init()
293 		ret = of_property_read_u32(node, "marvell,tauros2-cache-features", &f);  in tauros2_init()
295 			pr_info("Not found marvell,tauros-cache-features property, "  in tauros2_init()