Lines Matching full:apic
4 * Local APIC virtualization
68 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
69 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);
76 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument
78 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
87 static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg) in kvm_lapic_get_reg64() argument
89 return __kvm_lapic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
98 static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic, in kvm_lapic_set_reg64() argument
101 __kvm_lapic_set_reg64(apic->regs, reg, val); in kvm_lapic_set_reg64()
111 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_pending_eoi() local
113 return apic_test_vector(vector, apic->regs + APIC_ISR) || in kvm_apic_pending_eoi()
114 apic_test_vector(vector, apic->regs + APIC_IRR); in kvm_apic_pending_eoi()
130 static inline int apic_enabled(struct kvm_lapic *apic) in apic_enabled() argument
132 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); in apic_enabled()
142 static inline u32 kvm_x2apic_id(struct kvm_lapic *apic) in kvm_x2apic_id() argument
144 return apic->vcpu->vcpu_id; in kvm_x2apic_id()
221 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_phys_map() local
222 u32 x2apic_id = kvm_x2apic_id(apic); in kvm_recalculate_phys_map()
223 u32 xapic_id = kvm_xapic_id(apic); in kvm_recalculate_phys_map()
235 * Bail if a vCPU was added and/or enabled its APIC between allocating in kvm_recalculate_phys_map()
244 * Deliberately truncate the vCPU ID when detecting a mismatched APIC in kvm_recalculate_phys_map()
249 if (!apic_x2apic_mode(apic) && xapic_id != (u8)vcpu->vcpu_id) in kvm_recalculate_phys_map()
253 * Apply KVM's hotplug hack if userspace has enable 32-bit APIC IDs. in kvm_recalculate_phys_map()
260 * userspace has not enabled 32-bit x2APIC IDs. Each APIC is supposed in kvm_recalculate_phys_map()
262 * effective APIC ID, e.g. due to the x2APIC wrap or because the guest in kvm_recalculate_phys_map()
268 if (apic_x2apic_mode(apic) || x2apic_id > 0xff) in kvm_recalculate_phys_map()
269 new->phys_map[x2apic_id] = apic; in kvm_recalculate_phys_map()
271 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id]) in kvm_recalculate_phys_map()
272 new->phys_map[xapic_id] = apic; in kvm_recalculate_phys_map()
275 * Disable the optimized map if the physical APIC ID is already in kvm_recalculate_phys_map()
279 if (apic_x2apic_mode(apic)) in kvm_recalculate_phys_map()
287 new->phys_map[physical_id] = apic; in kvm_recalculate_phys_map()
296 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_recalculate_logical_map() local
305 if (!kvm_apic_sw_enabled(apic)) in kvm_recalculate_logical_map()
308 ldr = kvm_lapic_get_reg(apic, APIC_LDR); in kvm_recalculate_logical_map()
312 if (apic_x2apic_mode(apic)) { in kvm_recalculate_logical_map()
316 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) in kvm_recalculate_logical_map()
340 if (apic_x2apic_mode(apic)) { in kvm_recalculate_logical_map()
341 WARN_ON_ONCE(ldr != kvm_apic_calc_x2apic_ldr(kvm_x2apic_id(apic))); in kvm_recalculate_logical_map()
358 cluster[ldr] = apic; in kvm_recalculate_logical_map()
387 "Dirty APIC map without an in-kernel local APIC"); in kvm_recalculate_apic_map()
394 * or the APIC registers (if dirty). Note, on retry the map may have in kvm_recalculate_apic_map()
411 * with the highest x2APIC ID is toggling its APIC on and off. in kvm_recalculate_apic_map()
417 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic)); in kvm_recalculate_apic_map()
472 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty. in kvm_recalculate_apic_map()
485 static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) in apic_set_spiv() argument
489 kvm_lapic_set_reg(apic, APIC_SPIV, val); in apic_set_spiv()
491 if (enabled != apic->sw_enabled) { in apic_set_spiv()
492 apic->sw_enabled = enabled; in apic_set_spiv()
498 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in apic_set_spiv()
503 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu); in apic_set_spiv()
506 static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id) in kvm_apic_set_xapic_id() argument
508 kvm_lapic_set_reg(apic, APIC_ID, id << 24); in kvm_apic_set_xapic_id()
509 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_xapic_id()
512 static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) in kvm_apic_set_ldr() argument
514 kvm_lapic_set_reg(apic, APIC_LDR, id); in kvm_apic_set_ldr()
515 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_ldr()
518 static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val) in kvm_apic_set_dfr() argument
520 kvm_lapic_set_reg(apic, APIC_DFR, val); in kvm_apic_set_dfr()
521 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_dfr()
524 static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id) in kvm_apic_set_x2apic_id() argument
528 WARN_ON_ONCE(id != apic->vcpu->vcpu_id); in kvm_apic_set_x2apic_id()
530 kvm_lapic_set_reg(apic, APIC_ID, id); in kvm_apic_set_x2apic_id()
531 kvm_lapic_set_reg(apic, APIC_LDR, ldr); in kvm_apic_set_x2apic_id()
532 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_x2apic_id()
535 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) in apic_lvt_enabled() argument
537 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); in apic_lvt_enabled()
540 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) in apic_lvtt_oneshot() argument
542 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; in apic_lvtt_oneshot()
545 static inline int apic_lvtt_period(struct kvm_lapic *apic) in apic_lvtt_period() argument
547 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; in apic_lvtt_period()
550 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) in apic_lvtt_tscdeadline() argument
552 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; in apic_lvtt_tscdeadline()
560 static inline bool kvm_lapic_lvt_supported(struct kvm_lapic *apic, int lvt_index) in kvm_lapic_lvt_supported() argument
562 return apic->nr_lvt_entries > lvt_index; in kvm_lapic_lvt_supported()
572 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_version() local
578 v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16); in kvm_apic_set_version()
590 kvm_lapic_set_reg(apic, APIC_LVR, v); in kvm_apic_set_version()
596 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_after_set_mcg_cap() local
599 if (!lapic_in_kernel(vcpu) || nr_lvt_entries == apic->nr_lvt_entries) in kvm_apic_after_set_mcg_cap()
603 for (i = apic->nr_lvt_entries; i < nr_lvt_entries; i++) in kvm_apic_after_set_mcg_cap()
604 kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED); in kvm_apic_after_set_mcg_cap()
606 apic->nr_lvt_entries = nr_lvt_entries; in kvm_apic_after_set_mcg_cap()
689 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_irr() local
690 bool irr_updated = __kvm_apic_update_irr(pir, apic->regs, max_irr); in kvm_apic_update_irr()
692 if (unlikely(!apic->apicv_active && irr_updated)) in kvm_apic_update_irr()
693 apic->irr_pending = true; in kvm_apic_update_irr()
698 static inline int apic_search_irr(struct kvm_lapic *apic) in apic_search_irr() argument
700 return find_highest_vector(apic->regs + APIC_IRR); in apic_search_irr()
703 static inline int apic_find_highest_irr(struct kvm_lapic *apic) in apic_find_highest_irr() argument
711 if (!apic->irr_pending) in apic_find_highest_irr()
714 result = apic_search_irr(apic); in apic_find_highest_irr()
720 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) in apic_clear_irr() argument
722 if (unlikely(apic->apicv_active)) { in apic_clear_irr()
724 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
725 static_call_cond(kvm_x86_hwapic_irr_update)(apic->vcpu, in apic_clear_irr()
726 apic_find_highest_irr(apic)); in apic_clear_irr()
728 apic->irr_pending = false; in apic_clear_irr()
729 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR); in apic_clear_irr()
730 if (apic_search_irr(apic) != -1) in apic_clear_irr()
731 apic->irr_pending = true; in apic_clear_irr()
737 apic_clear_irr(vec, vcpu->arch.apic); in kvm_apic_clear_irr()
741 static inline void apic_set_isr(int vec, struct kvm_lapic *apic) in apic_set_isr() argument
743 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) in apic_set_isr()
747 * With APIC virtualization enabled, all caching is disabled in apic_set_isr()
751 if (unlikely(apic->apicv_active)) in apic_set_isr()
754 ++apic->isr_count; in apic_set_isr()
755 BUG_ON(apic->isr_count > MAX_APIC_VECTOR); in apic_set_isr()
761 apic->highest_isr_cache = vec; in apic_set_isr()
765 static inline int apic_find_highest_isr(struct kvm_lapic *apic) in apic_find_highest_isr() argument
771 * is always -1, with APIC virtualization enabled. in apic_find_highest_isr()
773 if (!apic->isr_count) in apic_find_highest_isr()
775 if (likely(apic->highest_isr_cache != -1)) in apic_find_highest_isr()
776 return apic->highest_isr_cache; in apic_find_highest_isr()
778 result = find_highest_vector(apic->regs + APIC_ISR); in apic_find_highest_isr()
784 static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) in apic_clear_isr() argument
786 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) in apic_clear_isr()
790 * We do get here for APIC virtualization enabled if the guest in apic_clear_isr()
791 * uses the Hyper-V APIC enlightenment. In this case we may need in apic_clear_isr()
796 if (unlikely(apic->apicv_active)) in apic_clear_isr()
797 static_call_cond(kvm_x86_hwapic_isr_update)(apic_find_highest_isr(apic)); in apic_clear_isr()
799 --apic->isr_count; in apic_clear_isr()
800 BUG_ON(apic->isr_count < 0); in apic_clear_isr()
801 apic->highest_isr_cache = -1; in apic_clear_isr()
812 return apic_find_highest_irr(vcpu->arch.apic); in kvm_lapic_find_highest_irr()
816 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
823 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_irq() local
825 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, in kvm_apic_set_irq()
929 static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr) in apic_has_interrupt_for_ppr() argument
933 highest_irr = static_call(kvm_x86_sync_pir_to_irr)(apic->vcpu); in apic_has_interrupt_for_ppr()
935 highest_irr = apic_find_highest_irr(apic); in apic_has_interrupt_for_ppr()
941 static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr) in __apic_update_ppr() argument
946 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); in __apic_update_ppr()
947 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); in __apic_update_ppr()
948 isr = apic_find_highest_isr(apic); in __apic_update_ppr()
958 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); in __apic_update_ppr()
963 static void apic_update_ppr(struct kvm_lapic *apic) in apic_update_ppr() argument
967 if (__apic_update_ppr(apic, &ppr) && in apic_update_ppr()
968 apic_has_interrupt_for_ppr(apic, ppr) != -1) in apic_update_ppr()
969 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_update_ppr()
974 apic_update_ppr(vcpu->arch.apic); in kvm_apic_update_ppr()
978 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) in apic_set_tpr() argument
980 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); in apic_set_tpr()
981 apic_update_ppr(apic); in apic_set_tpr()
984 static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) in kvm_apic_broadcast() argument
986 return mda == (apic_x2apic_mode(apic) ? in kvm_apic_broadcast()
990 static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) in kvm_apic_match_physical_addr() argument
992 if (kvm_apic_broadcast(apic, mda)) in kvm_apic_match_physical_addr()
997 * were in x2APIC mode if the target APIC ID can't be encoded as an in kvm_apic_match_physical_addr()
999 * start in xAPIC mode) with an APIC ID that is unaddressable in xAPIC in kvm_apic_match_physical_addr()
1000 * mode. Match the x2APIC ID if and only if the target APIC ID can't in kvm_apic_match_physical_addr()
1004 if (apic_x2apic_mode(apic) || mda > 0xff) in kvm_apic_match_physical_addr()
1005 return mda == kvm_x2apic_id(apic); in kvm_apic_match_physical_addr()
1007 return mda == kvm_xapic_id(apic); in kvm_apic_match_physical_addr()
1010 static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) in kvm_apic_match_logical_addr() argument
1014 if (kvm_apic_broadcast(apic, mda)) in kvm_apic_match_logical_addr()
1017 logical_id = kvm_lapic_get_reg(apic, APIC_LDR); in kvm_apic_match_logical_addr()
1019 if (apic_x2apic_mode(apic)) in kvm_apic_match_logical_addr()
1025 switch (kvm_lapic_get_reg(apic, APIC_DFR)) { in kvm_apic_match_logical_addr()
1036 /* The KVM local APIC implementation has two quirks:
1067 struct kvm_lapic *target = vcpu->arch.apic; in kvm_apic_match_dest()
1288 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, in __apic_accept_irq() argument
1293 struct kvm_vcpu *vcpu = apic->vcpu; in __apic_accept_irq()
1306 if (unlikely(!apic_enabled(apic))) in __apic_accept_irq()
1316 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { in __apic_accept_irq()
1319 apic->regs + APIC_TMR); in __apic_accept_irq()
1322 apic->regs + APIC_TMR); in __apic_accept_irq()
1325 static_call(kvm_x86_deliver_interrupt)(apic, delivery_mode, in __apic_accept_irq()
1353 apic->pending_events = (1UL << KVM_APIC_INIT); in __apic_accept_irq()
1361 apic->sipi_vector = vector; in __apic_accept_irq()
1364 set_bit(KVM_APIC_SIPI, &apic->pending_events); in __apic_accept_irq()
1434 static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) in kvm_ioapic_handles_vector() argument
1436 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); in kvm_ioapic_handles_vector()
1439 static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) in kvm_ioapic_send_eoi() argument
1444 if (!kvm_ioapic_handles_vector(apic, vector)) in kvm_ioapic_send_eoi()
1448 if (irqchip_split(apic->vcpu->kvm)) { in kvm_ioapic_send_eoi()
1449 apic->vcpu->arch.pending_ioapic_eoi = vector; in kvm_ioapic_send_eoi()
1450 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); in kvm_ioapic_send_eoi()
1454 if (apic_test_vector(vector, apic->regs + APIC_TMR)) in kvm_ioapic_send_eoi()
1459 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); in kvm_ioapic_send_eoi()
1462 static int apic_set_eoi(struct kvm_lapic *apic) in apic_set_eoi() argument
1464 int vector = apic_find_highest_isr(apic); in apic_set_eoi()
1466 trace_kvm_eoi(apic, vector); in apic_set_eoi()
1475 apic_clear_isr(vector, apic); in apic_set_eoi()
1476 apic_update_ppr(apic); in apic_set_eoi()
1478 if (to_hv_vcpu(apic->vcpu) && in apic_set_eoi()
1479 test_bit(vector, to_hv_synic(apic->vcpu)->vec_bitmap)) in apic_set_eoi()
1480 kvm_hv_synic_send_eoi(apic->vcpu, vector); in apic_set_eoi()
1482 kvm_ioapic_send_eoi(apic, vector); in apic_set_eoi()
1483 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in apic_set_eoi()
1493 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_eoi_accelerated() local
1495 trace_kvm_eoi(apic, vector); in kvm_apic_set_eoi_accelerated()
1497 kvm_ioapic_send_eoi(apic, vector); in kvm_apic_set_eoi_accelerated()
1498 kvm_make_request(KVM_REQ_EVENT, apic->vcpu); in kvm_apic_set_eoi_accelerated()
1502 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high) in kvm_apic_send_ipi() argument
1516 if (apic_x2apic_mode(apic)) in kvm_apic_send_ipi()
1523 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); in kvm_apic_send_ipi()
1527 static u32 apic_get_tmcct(struct kvm_lapic *apic) in apic_get_tmcct() argument
1532 ASSERT(apic != NULL); in apic_get_tmcct()
1535 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || in apic_get_tmcct()
1536 apic->lapic_timer.period == 0) in apic_get_tmcct()
1540 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in apic_get_tmcct()
1544 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); in apic_get_tmcct()
1545 return div64_u64(ns, (APIC_BUS_CYCLE_NS * apic->divide_count)); in apic_get_tmcct()
1548 static void __report_tpr_access(struct kvm_lapic *apic, bool write) in __report_tpr_access() argument
1550 struct kvm_vcpu *vcpu = apic->vcpu; in __report_tpr_access()
1558 static inline void report_tpr_access(struct kvm_lapic *apic, bool write) in report_tpr_access() argument
1560 if (apic->vcpu->arch.tpr_access_reporting) in report_tpr_access()
1561 __report_tpr_access(apic, write); in report_tpr_access()
1564 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) in __apic_read() argument
1576 if (apic_lvtt_tscdeadline(apic)) in __apic_read()
1579 val = apic_get_tmcct(apic); in __apic_read()
1582 apic_update_ppr(apic); in __apic_read()
1583 val = kvm_lapic_get_reg(apic, offset); in __apic_read()
1586 report_tpr_access(apic, false); in __apic_read()
1589 val = kvm_lapic_get_reg(apic, offset); in __apic_read()
1605 u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic) in kvm_lapic_readable_reg_mask() argument
1630 if (kvm_lapic_lvt_supported(apic, LVT_CMCI)) in kvm_lapic_readable_reg_mask()
1634 if (!apic_x2apic_mode(apic)) in kvm_lapic_readable_reg_mask()
1643 static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, in kvm_lapic_reg_read() argument
1653 WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR); in kvm_lapic_reg_read()
1659 !(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset))) in kvm_lapic_reg_read()
1662 result = __apic_read(apic, offset & ~0xf); in kvm_lapic_reg_read()
1673 printk(KERN_ERR "Local APIC read with len = %x, " in kvm_lapic_reg_read()
1680 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) in apic_mmio_in_range() argument
1682 return addr >= apic->base_address && in apic_mmio_in_range()
1683 addr < apic->base_address + LAPIC_MMIO_LENGTH; in apic_mmio_in_range()
1689 struct kvm_lapic *apic = to_lapic(this); in apic_mmio_read() local
1690 u32 offset = address - apic->base_address; in apic_mmio_read()
1692 if (!apic_mmio_in_range(apic, address)) in apic_mmio_read()
1695 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { in apic_mmio_read()
1704 kvm_lapic_reg_read(apic, offset, len, data); in apic_mmio_read()
1709 static void update_divide_count(struct kvm_lapic *apic) in update_divide_count() argument
1713 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); in update_divide_count()
1716 apic->divide_count = 0x1 << (tmp2 & 0x7); in update_divide_count()
1719 static void limit_periodic_timer_frequency(struct kvm_lapic *apic) in limit_periodic_timer_frequency() argument
1726 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in limit_periodic_timer_frequency()
1729 if (apic->lapic_timer.period < min_period) { in limit_periodic_timer_frequency()
1733 apic->vcpu->vcpu_id, in limit_periodic_timer_frequency()
1734 apic->lapic_timer.period, min_period); in limit_periodic_timer_frequency()
1735 apic->lapic_timer.period = min_period; in limit_periodic_timer_frequency()
1740 static void cancel_hv_timer(struct kvm_lapic *apic);
1742 static void cancel_apic_timer(struct kvm_lapic *apic) in cancel_apic_timer() argument
1744 hrtimer_cancel(&apic->lapic_timer.timer); in cancel_apic_timer()
1746 if (apic->lapic_timer.hv_timer_in_use) in cancel_apic_timer()
1747 cancel_hv_timer(apic); in cancel_apic_timer()
1749 atomic_set(&apic->lapic_timer.pending, 0); in cancel_apic_timer()
1752 static void apic_update_lvtt(struct kvm_lapic *apic) in apic_update_lvtt() argument
1754 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & in apic_update_lvtt()
1755 apic->lapic_timer.timer_mode_mask; in apic_update_lvtt()
1757 if (apic->lapic_timer.timer_mode != timer_mode) { in apic_update_lvtt()
1758 if (apic_lvtt_tscdeadline(apic) != (timer_mode == in apic_update_lvtt()
1760 cancel_apic_timer(apic); in apic_update_lvtt()
1761 kvm_lapic_set_reg(apic, APIC_TMICT, 0); in apic_update_lvtt()
1762 apic->lapic_timer.period = 0; in apic_update_lvtt()
1763 apic->lapic_timer.tscdeadline = 0; in apic_update_lvtt()
1765 apic->lapic_timer.timer_mode = timer_mode; in apic_update_lvtt()
1766 limit_periodic_timer_frequency(apic); in apic_update_lvtt()
1777 struct kvm_lapic *apic = vcpu->arch.apic; in lapic_timer_int_injected() local
1778 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); in lapic_timer_int_injected()
1780 if (kvm_apic_hw_enabled(apic)) { in lapic_timer_int_injected()
1782 void *bitmap = apic->regs + APIC_ISR; in lapic_timer_int_injected()
1784 if (apic->apicv_active) in lapic_timer_int_injected()
1785 bitmap = apic->regs + APIC_IRR; in lapic_timer_int_injected()
1795 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns; in __wait_lapic_expire()
1816 struct kvm_lapic *apic = vcpu->arch.apic; in adjust_lapic_timer_advance() local
1817 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns; in adjust_lapic_timer_advance()
1839 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in adjust_lapic_timer_advance()
1844 struct kvm_lapic *apic = vcpu->arch.apic; in __kvm_wait_lapic_expire() local
1847 tsc_deadline = apic->lapic_timer.expired_tscdeadline; in __kvm_wait_lapic_expire()
1848 apic->lapic_timer.expired_tscdeadline = 0; in __kvm_wait_lapic_expire()
1870 vcpu->arch.apic->lapic_timer.expired_tscdeadline && in kvm_wait_lapic_expire()
1871 vcpu->arch.apic->lapic_timer.timer_advance_ns && in kvm_wait_lapic_expire()
1877 static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic) in kvm_apic_inject_pending_timer_irqs() argument
1879 struct kvm_timer *ktimer = &apic->lapic_timer; in kvm_apic_inject_pending_timer_irqs()
1881 kvm_apic_local_deliver(apic, APIC_LVTT); in kvm_apic_inject_pending_timer_irqs()
1882 if (apic_lvtt_tscdeadline(apic)) { in kvm_apic_inject_pending_timer_irqs()
1884 } else if (apic_lvtt_oneshot(apic)) { in kvm_apic_inject_pending_timer_irqs()
1890 static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn) in apic_timer_expired() argument
1892 struct kvm_vcpu *vcpu = apic->vcpu; in apic_timer_expired()
1893 struct kvm_timer *ktimer = &apic->lapic_timer; in apic_timer_expired()
1895 if (atomic_read(&apic->lapic_timer.pending)) in apic_timer_expired()
1898 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use) in apic_timer_expired()
1901 if (!from_timer_fn && apic->apicv_active) { in apic_timer_expired()
1903 kvm_apic_inject_pending_timer_irqs(apic); in apic_timer_expired()
1907 if (kvm_use_posted_timer_interrupt(apic->vcpu)) { in apic_timer_expired()
1915 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline && in apic_timer_expired()
1916 vcpu->arch.apic->lapic_timer.timer_advance_ns) in apic_timer_expired()
1918 kvm_apic_inject_pending_timer_irqs(apic); in apic_timer_expired()
1922 atomic_inc(&apic->lapic_timer.pending); in apic_timer_expired()
1928 static void start_sw_tscdeadline(struct kvm_lapic *apic) in start_sw_tscdeadline() argument
1930 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_tscdeadline()
1934 struct kvm_vcpu *vcpu = apic->vcpu; in start_sw_tscdeadline()
1951 likely(ns > apic->lapic_timer.timer_advance_ns)) { in start_sw_tscdeadline()
1956 apic_timer_expired(apic, false); in start_sw_tscdeadline()
1961 static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict) in tmict_to_ns() argument
1963 return (u64)tmict * APIC_BUS_CYCLE_NS * (u64)apic->divide_count; in tmict_to_ns()
1966 static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor) in update_target_expiration() argument
1971 apic->lapic_timer.period = in update_target_expiration()
1972 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT)); in update_target_expiration()
1973 limit_periodic_timer_frequency(apic); in update_target_expiration()
1976 remaining = ktime_sub(apic->lapic_timer.target_expiration, now); in update_target_expiration()
1982 apic->divide_count, old_divisor); in update_target_expiration()
1984 apic->lapic_timer.tscdeadline += in update_target_expiration()
1985 nsec_to_cycles(apic->vcpu, ns_remaining_new) - in update_target_expiration()
1986 nsec_to_cycles(apic->vcpu, ns_remaining_old); in update_target_expiration()
1987 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new); in update_target_expiration()
1990 static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg) in set_target_expiration() argument
1997 apic->lapic_timer.period = in set_target_expiration()
1998 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT)); in set_target_expiration()
2000 if (!apic->lapic_timer.period) { in set_target_expiration()
2001 apic->lapic_timer.tscdeadline = 0; in set_target_expiration()
2005 limit_periodic_timer_frequency(apic); in set_target_expiration()
2006 deadline = apic->lapic_timer.period; in set_target_expiration()
2008 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { in set_target_expiration()
2010 deadline = tmict_to_ns(apic, in set_target_expiration()
2011 kvm_lapic_get_reg(apic, count_reg)); in set_target_expiration()
2013 if (apic_lvtt_period(apic)) in set_target_expiration()
2014 deadline = apic->lapic_timer.period; in set_target_expiration()
2018 else if (unlikely(deadline > apic->lapic_timer.period)) { in set_target_expiration()
2023 apic->vcpu->vcpu_id, in set_target_expiration()
2025 kvm_lapic_get_reg(apic, count_reg), in set_target_expiration()
2026 deadline, apic->lapic_timer.period); in set_target_expiration()
2027 kvm_lapic_set_reg(apic, count_reg, 0); in set_target_expiration()
2028 deadline = apic->lapic_timer.period; in set_target_expiration()
2033 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in set_target_expiration()
2034 nsec_to_cycles(apic->vcpu, deadline); in set_target_expiration()
2035 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline); in set_target_expiration()
2040 static void advance_periodic_target_expiration(struct kvm_lapic *apic) in advance_periodic_target_expiration() argument
2053 apic->lapic_timer.target_expiration = in advance_periodic_target_expiration()
2054 ktime_add_ns(apic->lapic_timer.target_expiration, in advance_periodic_target_expiration()
2055 apic->lapic_timer.period); in advance_periodic_target_expiration()
2056 delta = ktime_sub(apic->lapic_timer.target_expiration, now); in advance_periodic_target_expiration()
2057 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) + in advance_periodic_target_expiration()
2058 nsec_to_cycles(apic->vcpu, delta); in advance_periodic_target_expiration()
2061 static void start_sw_period(struct kvm_lapic *apic) in start_sw_period() argument
2063 if (!apic->lapic_timer.period) in start_sw_period()
2067 apic->lapic_timer.target_expiration)) { in start_sw_period()
2068 apic_timer_expired(apic, false); in start_sw_period()
2070 if (apic_lvtt_oneshot(apic)) in start_sw_period()
2073 advance_periodic_target_expiration(apic); in start_sw_period()
2076 hrtimer_start(&apic->lapic_timer.timer, in start_sw_period()
2077 apic->lapic_timer.target_expiration, in start_sw_period()
2086 return vcpu->arch.apic->lapic_timer.hv_timer_in_use; in kvm_lapic_hv_timer_in_use()
2089 static void cancel_hv_timer(struct kvm_lapic *apic) in cancel_hv_timer() argument
2092 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in cancel_hv_timer()
2093 static_call(kvm_x86_cancel_hv_timer)(apic->vcpu); in cancel_hv_timer()
2094 apic->lapic_timer.hv_timer_in_use = false; in cancel_hv_timer()
2097 static bool start_hv_timer(struct kvm_lapic *apic) in start_hv_timer() argument
2099 struct kvm_timer *ktimer = &apic->lapic_timer; in start_hv_timer()
2100 struct kvm_vcpu *vcpu = apic->vcpu; in start_hv_timer()
2121 if (!apic_lvtt_period(apic)) { in start_hv_timer()
2127 cancel_hv_timer(apic); in start_hv_timer()
2129 apic_timer_expired(apic, false); in start_hv_timer()
2130 cancel_hv_timer(apic); in start_hv_timer()
2139 static void start_sw_timer(struct kvm_lapic *apic) in start_sw_timer() argument
2141 struct kvm_timer *ktimer = &apic->lapic_timer; in start_sw_timer()
2144 if (apic->lapic_timer.hv_timer_in_use) in start_sw_timer()
2145 cancel_hv_timer(apic); in start_sw_timer()
2146 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending)) in start_sw_timer()
2149 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) in start_sw_timer()
2150 start_sw_period(apic); in start_sw_timer()
2151 else if (apic_lvtt_tscdeadline(apic)) in start_sw_timer()
2152 start_sw_tscdeadline(apic); in start_sw_timer()
2153 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false); in start_sw_timer()
2156 static void restart_apic_timer(struct kvm_lapic *apic) in restart_apic_timer() argument
2160 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending)) in restart_apic_timer()
2163 if (!start_hv_timer(apic)) in restart_apic_timer()
2164 start_sw_timer(apic); in restart_apic_timer()
2171 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_expired_hv_timer() local
2175 if (!apic->lapic_timer.hv_timer_in_use) in kvm_lapic_expired_hv_timer()
2178 apic_timer_expired(apic, false); in kvm_lapic_expired_hv_timer()
2179 cancel_hv_timer(apic); in kvm_lapic_expired_hv_timer()
2181 if (apic_lvtt_period(apic) && apic->lapic_timer.period) { in kvm_lapic_expired_hv_timer()
2182 advance_periodic_target_expiration(apic); in kvm_lapic_expired_hv_timer()
2183 restart_apic_timer(apic); in kvm_lapic_expired_hv_timer()
2192 restart_apic_timer(vcpu->arch.apic); in kvm_lapic_switch_to_hv_timer()
2197 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_switch_to_sw_timer() local
2201 if (apic->lapic_timer.hv_timer_in_use) in kvm_lapic_switch_to_sw_timer()
2202 start_sw_timer(apic); in kvm_lapic_switch_to_sw_timer()
2208 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_restart_hv_timer() local
2210 WARN_ON(!apic->lapic_timer.hv_timer_in_use); in kvm_lapic_restart_hv_timer()
2211 restart_apic_timer(apic); in kvm_lapic_restart_hv_timer()
2214 static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg) in __start_apic_timer() argument
2216 atomic_set(&apic->lapic_timer.pending, 0); in __start_apic_timer()
2218 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) in __start_apic_timer()
2219 && !set_target_expiration(apic, count_reg)) in __start_apic_timer()
2222 restart_apic_timer(apic); in __start_apic_timer()
2225 static void start_apic_timer(struct kvm_lapic *apic) in start_apic_timer() argument
2227 __start_apic_timer(apic, APIC_TMICT); in start_apic_timer()
2230 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) in apic_manage_nmi_watchdog() argument
2234 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { in apic_manage_nmi_watchdog()
2235 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; in apic_manage_nmi_watchdog()
2237 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2239 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); in apic_manage_nmi_watchdog()
2253 static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) in kvm_lapic_reg_write() argument
2260 case APIC_ID: /* Local APIC ID */ in kvm_lapic_reg_write()
2261 if (!apic_x2apic_mode(apic)) { in kvm_lapic_reg_write()
2262 kvm_apic_set_xapic_id(apic, val >> 24); in kvm_lapic_reg_write()
2269 report_tpr_access(apic, true); in kvm_lapic_reg_write()
2270 apic_set_tpr(apic, val & 0xff); in kvm_lapic_reg_write()
2274 apic_set_eoi(apic); in kvm_lapic_reg_write()
2278 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2279 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); in kvm_lapic_reg_write()
2285 if (!apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2286 kvm_apic_set_dfr(apic, val | 0x0FFFFFFF); in kvm_lapic_reg_write()
2293 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) in kvm_lapic_reg_write()
2295 apic_set_spiv(apic, val & mask); in kvm_lapic_reg_write()
2299 for (i = 0; i < apic->nr_lvt_entries; i++) { in kvm_lapic_reg_write()
2300 kvm_lapic_set_reg(apic, APIC_LVTx(i), in kvm_lapic_reg_write()
2301 kvm_lapic_get_reg(apic, APIC_LVTx(i)) | APIC_LVT_MASKED); in kvm_lapic_reg_write()
2303 apic_update_lvtt(apic); in kvm_lapic_reg_write()
2304 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reg_write()
2310 WARN_ON_ONCE(apic_x2apic_mode(apic)); in kvm_lapic_reg_write()
2314 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2)); in kvm_lapic_reg_write()
2315 kvm_lapic_set_reg(apic, APIC_ICR, val); in kvm_lapic_reg_write()
2318 if (apic_x2apic_mode(apic)) in kvm_lapic_reg_write()
2321 kvm_lapic_set_reg(apic, APIC_ICR2, val & 0xff000000); in kvm_lapic_reg_write()
2325 apic_manage_nmi_watchdog(apic, val); in kvm_lapic_reg_write()
2333 if (!kvm_lapic_lvt_supported(apic, index)) { in kvm_lapic_reg_write()
2337 if (!kvm_apic_sw_enabled(apic)) in kvm_lapic_reg_write()
2340 kvm_lapic_set_reg(apic, reg, val); in kvm_lapic_reg_write()
2345 if (!kvm_apic_sw_enabled(apic)) in kvm_lapic_reg_write()
2347 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); in kvm_lapic_reg_write()
2348 kvm_lapic_set_reg(apic, APIC_LVTT, val); in kvm_lapic_reg_write()
2349 apic_update_lvtt(apic); in kvm_lapic_reg_write()
2353 if (apic_lvtt_tscdeadline(apic)) in kvm_lapic_reg_write()
2356 cancel_apic_timer(apic); in kvm_lapic_reg_write()
2357 kvm_lapic_set_reg(apic, APIC_TMICT, val); in kvm_lapic_reg_write()
2358 start_apic_timer(apic); in kvm_lapic_reg_write()
2362 uint32_t old_divisor = apic->divide_count; in kvm_lapic_reg_write()
2364 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb); in kvm_lapic_reg_write()
2365 update_divide_count(apic); in kvm_lapic_reg_write()
2366 if (apic->divide_count != old_divisor && in kvm_lapic_reg_write()
2367 apic->lapic_timer.period) { in kvm_lapic_reg_write()
2368 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reg_write()
2369 update_target_expiration(apic, old_divisor); in kvm_lapic_reg_write()
2370 restart_apic_timer(apic); in kvm_lapic_reg_write()
2375 if (apic_x2apic_mode(apic) && val != 0) in kvm_lapic_reg_write()
2384 if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK)) in kvm_lapic_reg_write()
2387 kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0); in kvm_lapic_reg_write()
2395 * Recalculate APIC maps if necessary, e.g. if the software enable bit in kvm_lapic_reg_write()
2396 * was toggled, the APIC ID changed, etc... The maps are marked dirty in kvm_lapic_reg_write()
2399 kvm_recalculate_apic_map(apic->vcpu->kvm); in kvm_lapic_reg_write()
2407 struct kvm_lapic *apic = to_lapic(this); in apic_mmio_write() local
2408 unsigned int offset = address - apic->base_address; in apic_mmio_write()
2411 if (!apic_mmio_in_range(apic, address)) in apic_mmio_write()
2414 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) { in apic_mmio_write()
2423 * APIC register must be aligned on 128-bits boundary. in apic_mmio_write()
2432 kvm_lapic_reg_write(apic, offset & 0xff0, val); in apic_mmio_write()
2439 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); in kvm_lapic_set_eoi()
2443 /* emulate APIC access in a trap manner */
2446 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_write_nodecode() local
2454 * virtual APIC state, but KVM needs to conditionally modify the value in kvm_apic_write_nodecode()
2459 if (apic_x2apic_mode(apic) && offset == APIC_ICR) in kvm_apic_write_nodecode()
2460 kvm_x2apic_icr_write(apic, kvm_lapic_get_reg64(apic, APIC_ICR)); in kvm_apic_write_nodecode()
2462 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset)); in kvm_apic_write_nodecode()
2468 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_free_lapic() local
2470 if (!vcpu->arch.apic) in kvm_free_lapic()
2473 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_free_lapic()
2478 if (!apic->sw_enabled) in kvm_free_lapic()
2481 if (apic->regs) in kvm_free_lapic()
2482 free_page((unsigned long)apic->regs); in kvm_free_lapic()
2484 kfree(apic); in kvm_free_lapic()
2494 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_lapic_tscdeadline_msr() local
2496 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) in kvm_get_lapic_tscdeadline_msr()
2499 return apic->lapic_timer.tscdeadline; in kvm_get_lapic_tscdeadline_msr()
2504 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_set_lapic_tscdeadline_msr() local
2506 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic)) in kvm_set_lapic_tscdeadline_msr()
2509 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_set_lapic_tscdeadline_msr()
2510 apic->lapic_timer.tscdeadline = data; in kvm_set_lapic_tscdeadline_msr()
2511 start_apic_timer(apic); in kvm_set_lapic_tscdeadline_msr()
2516 apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4); in kvm_lapic_set_tpr()
2523 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); in kvm_lapic_get_cr8()
2531 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_set_base() local
2538 if (!apic) in kvm_lapic_set_base()
2544 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2550 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_lapic_set_base()
2556 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2558 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_set_base()
2566 apic->base_address = apic->vcpu->arch.apic_base & in kvm_lapic_set_base()
2570 apic->base_address != APIC_DEFAULT_PHYS_BASE) { in kvm_lapic_set_base()
2571 kvm_set_apicv_inhibit(apic->vcpu->kvm, in kvm_lapic_set_base()
2578 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_update_apicv() local
2580 if (apic->apicv_active) { in kvm_apic_update_apicv()
2582 apic->irr_pending = true; in kvm_apic_update_apicv()
2583 apic->isr_count = 1; in kvm_apic_update_apicv()
2591 apic->isr_count = count_vectors(apic->regs + APIC_ISR); in kvm_apic_update_apicv()
2593 apic->highest_isr_cache = -1; in kvm_apic_update_apicv()
2669 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_reset() local
2682 if (!apic) in kvm_lapic_reset()
2685 /* Stop the timer in case it's a reset to an active apic */ in kvm_lapic_reset()
2686 hrtimer_cancel(&apic->lapic_timer.timer); in kvm_lapic_reset()
2688 /* The xAPIC ID is set at RESET even if the APIC was already enabled. */ in kvm_lapic_reset()
2690 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id); in kvm_lapic_reset()
2691 kvm_apic_set_version(apic->vcpu); in kvm_lapic_reset()
2693 for (i = 0; i < apic->nr_lvt_entries; i++) in kvm_lapic_reset()
2694 kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED); in kvm_lapic_reset()
2695 apic_update_lvtt(apic); in kvm_lapic_reset()
2698 kvm_lapic_set_reg(apic, APIC_LVT0, in kvm_lapic_reset()
2700 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); in kvm_lapic_reset()
2702 kvm_apic_set_dfr(apic, 0xffffffffU); in kvm_lapic_reset()
2703 apic_set_spiv(apic, 0xff); in kvm_lapic_reset()
2704 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); in kvm_lapic_reset()
2705 if (!apic_x2apic_mode(apic)) in kvm_lapic_reset()
2706 kvm_apic_set_ldr(apic, 0); in kvm_lapic_reset()
2707 kvm_lapic_set_reg(apic, APIC_ESR, 0); in kvm_lapic_reset()
2708 if (!apic_x2apic_mode(apic)) { in kvm_lapic_reset()
2709 kvm_lapic_set_reg(apic, APIC_ICR, 0); in kvm_lapic_reset()
2710 kvm_lapic_set_reg(apic, APIC_ICR2, 0); in kvm_lapic_reset()
2712 kvm_lapic_set_reg64(apic, APIC_ICR, 0); in kvm_lapic_reset()
2714 kvm_lapic_set_reg(apic, APIC_TDCR, 0); in kvm_lapic_reset()
2715 kvm_lapic_set_reg(apic, APIC_TMICT, 0); in kvm_lapic_reset()
2717 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); in kvm_lapic_reset()
2718 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); in kvm_lapic_reset()
2719 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); in kvm_lapic_reset()
2722 update_divide_count(apic); in kvm_lapic_reset()
2723 atomic_set(&apic->lapic_timer.pending, 0); in kvm_lapic_reset()
2726 apic_update_ppr(apic); in kvm_lapic_reset()
2727 if (apic->apicv_active) { in kvm_lapic_reset()
2745 static bool lapic_is_periodic(struct kvm_lapic *apic) in lapic_is_periodic() argument
2747 return apic_lvtt_period(apic); in lapic_is_periodic()
2752 struct kvm_lapic *apic = vcpu->arch.apic; in apic_has_pending_timer() local
2754 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) in apic_has_pending_timer()
2755 return atomic_read(&apic->lapic_timer.pending); in apic_has_pending_timer()
2760 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) in kvm_apic_local_deliver() argument
2762 u32 reg = kvm_lapic_get_reg(apic, lvt_type); in kvm_apic_local_deliver()
2766 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { in kvm_apic_local_deliver()
2771 r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL); in kvm_apic_local_deliver()
2773 kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED); in kvm_apic_local_deliver()
2781 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_nmi_wd_deliver() local
2783 if (apic) in kvm_apic_nmi_wd_deliver()
2784 kvm_apic_local_deliver(apic, APIC_LVT0); in kvm_apic_nmi_wd_deliver()
2795 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); in apic_timer_fn() local
2797 apic_timer_expired(apic, true); in apic_timer_fn()
2799 if (lapic_is_periodic(apic)) { in apic_timer_fn()
2800 advance_periodic_target_expiration(apic); in apic_timer_fn()
2809 struct kvm_lapic *apic; in kvm_create_lapic() local
2813 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2814 if (!apic) in kvm_create_lapic()
2817 vcpu->arch.apic = apic; in kvm_create_lapic()
2819 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT); in kvm_create_lapic()
2820 if (!apic->regs) { in kvm_create_lapic()
2821 printk(KERN_ERR "malloc apic regs error for vcpu %x\n", in kvm_create_lapic()
2825 apic->vcpu = vcpu; in kvm_create_lapic()
2827 apic->nr_lvt_entries = kvm_apic_calc_nr_lvt_entries(vcpu); in kvm_create_lapic()
2829 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, in kvm_create_lapic()
2831 apic->lapic_timer.timer.function = apic_timer_fn; in kvm_create_lapic()
2833 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT; in kvm_create_lapic()
2836 apic->lapic_timer.timer_advance_ns = timer_advance_ns; in kvm_create_lapic()
2841 * Stuff the APIC ENABLE bit in lieu of temporarily incrementing in kvm_create_lapic()
2846 kvm_iodevice_init(&apic->dev, &apic_mmio_ops); in kvm_create_lapic()
2850 kfree(apic); in kvm_create_lapic()
2851 vcpu->arch.apic = NULL; in kvm_create_lapic()
2858 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_has_interrupt() local
2864 __apic_update_ppr(apic, &ppr); in kvm_apic_has_interrupt()
2865 return apic_has_interrupt_for_ppr(apic, ppr); in kvm_apic_has_interrupt()
2871 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); in kvm_apic_accept_pic_intr()
2873 if (!kvm_apic_hw_enabled(vcpu->arch.apic)) in kvm_apic_accept_pic_intr()
2883 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_inject_apic_timer_irqs() local
2885 if (atomic_read(&apic->lapic_timer.pending) > 0) { in kvm_inject_apic_timer_irqs()
2886 kvm_apic_inject_pending_timer_irqs(apic); in kvm_inject_apic_timer_irqs()
2887 atomic_set(&apic->lapic_timer.pending, 0); in kvm_inject_apic_timer_irqs()
2894 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_get_apic_interrupt() local
2901 * We get here even with APIC virtualization enabled, if doing in kvm_get_apic_interrupt()
2907 apic_clear_irr(vector, apic); in kvm_get_apic_interrupt()
2914 apic_update_ppr(apic); in kvm_get_apic_interrupt()
2922 apic_set_isr(vector, apic); in kvm_get_apic_interrupt()
2923 __apic_update_ppr(apic, &ppr); in kvm_get_apic_interrupt()
2932 if (apic_x2apic_mode(vcpu->arch.apic)) { in kvm_apic_state_fixup()
2969 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s)); in kvm_apic_get_state()
2976 __apic_read(vcpu->arch.apic, APIC_TMCCT)); in kvm_apic_get_state()
2983 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_set_state() local
2990 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); in kvm_apic_set_state()
2997 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s)); in kvm_apic_set_state()
2999 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY); in kvm_apic_set_state()
3003 apic_update_ppr(apic); in kvm_apic_set_state()
3004 cancel_apic_timer(apic); in kvm_apic_set_state()
3005 apic->lapic_timer.expired_tscdeadline = 0; in kvm_apic_set_state()
3006 apic_update_lvtt(apic); in kvm_apic_set_state()
3007 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); in kvm_apic_set_state()
3008 update_divide_count(apic); in kvm_apic_set_state()
3009 __start_apic_timer(apic, APIC_TMCCT); in kvm_apic_set_state()
3010 kvm_lapic_set_reg(apic, APIC_TMCCT, 0); in kvm_apic_set_state()
3012 if (apic->apicv_active) { in kvm_apic_set_state()
3014 static_call_cond(kvm_x86_hwapic_irr_update)(vcpu, apic_find_highest_irr(apic)); in kvm_apic_set_state()
3015 static_call_cond(kvm_x86_hwapic_isr_update)(apic_find_highest_isr(apic)); in kvm_apic_set_state()
3034 timer = &vcpu->arch.apic->lapic_timer.timer; in __kvm_migrate_apic_timer()
3047 struct kvm_lapic *apic) in apic_sync_pv_eoi_from_guest() argument
3065 vector = apic_set_eoi(apic); in apic_sync_pv_eoi_from_guest()
3066 trace_kvm_pv_eoi(apic, vector); in apic_sync_pv_eoi_from_guest()
3074 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); in kvm_lapic_sync_from_vapic()
3079 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_from_vapic()
3083 apic_set_tpr(vcpu->arch.apic, data & 0xff); in kvm_lapic_sync_from_vapic()
3093 struct kvm_lapic *apic) in apic_sync_pv_eoi_to_guest() argument
3097 apic->irr_pending || in apic_sync_pv_eoi_to_guest()
3099 apic->highest_isr_cache == -1 || in apic_sync_pv_eoi_to_guest()
3101 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { in apic_sync_pv_eoi_to_guest()
3109 pv_eoi_set_pending(apic->vcpu); in apic_sync_pv_eoi_to_guest()
3116 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_lapic_sync_to_vapic() local
3118 apic_sync_pv_eoi_to_guest(vcpu, apic); in kvm_lapic_sync_to_vapic()
3123 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; in kvm_lapic_sync_to_vapic()
3124 max_irr = apic_find_highest_irr(apic); in kvm_lapic_sync_to_vapic()
3127 max_isr = apic_find_highest_isr(apic); in kvm_lapic_sync_to_vapic()
3132 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, in kvm_lapic_sync_to_vapic()
3140 &vcpu->arch.apic->vapic_cache, in kvm_lapic_set_vapic_addr()
3148 vcpu->arch.apic->vapic_addr = vapic_addr; in kvm_lapic_set_vapic_addr()
3152 int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data) in kvm_x2apic_icr_write() argument
3156 kvm_apic_send_ipi(apic, (u32)data, (u32)(data >> 32)); in kvm_x2apic_icr_write()
3157 kvm_lapic_set_reg64(apic, APIC_ICR, data); in kvm_x2apic_icr_write()
3162 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data) in kvm_lapic_msr_read() argument
3167 *data = kvm_lapic_get_reg64(apic, APIC_ICR); in kvm_lapic_msr_read()
3171 if (kvm_lapic_reg_read(apic, reg, 4, &low)) in kvm_lapic_msr_read()
3179 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data) in kvm_lapic_msr_write() argument
3187 return kvm_x2apic_icr_write(apic, data); in kvm_lapic_msr_write()
3193 return kvm_lapic_reg_write(apic, reg, (u32)data); in kvm_lapic_msr_write()
3198 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_write() local
3201 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) in kvm_x2apic_msr_write()
3204 return kvm_lapic_msr_write(apic, reg, data); in kvm_x2apic_msr_write()
3209 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_x2apic_msr_read() local
3212 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) in kvm_x2apic_msr_read()
3215 return kvm_lapic_msr_read(apic, reg, data); in kvm_x2apic_msr_read()
3223 return kvm_lapic_msr_write(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_write()
3231 return kvm_lapic_msr_read(vcpu->arch.apic, reg, data); in kvm_hv_vapic_msr_read()
3262 struct kvm_lapic *apic = vcpu->arch.apic; in kvm_apic_accept_events() local
3287 clear_bit(KVM_APIC_SIPI, &apic->pending_events); in kvm_apic_accept_events()
3291 if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) { in kvm_apic_accept_events()
3293 if (kvm_vcpu_is_bsp(apic->vcpu)) in kvm_apic_accept_events()
3298 if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events)) { in kvm_apic_accept_events()
3302 sipi_vector = apic->sipi_vector; in kvm_apic_accept_events()