Lines Matching +full:0 +full:x8030

37 	{ 249600000, 1750000000, 0 },
41 	.l = 0x18,
42 	.alpha = 0x6000,
43 	.config_ctl_val = 0x20485699,
44 	.config_ctl_hi_val = 0x00002261,
45 	.config_ctl_hi1_val = 0x2a9a699c,
46 	.test_ctl_val = 0x00000000,
47 	.test_ctl_hi_val = 0x00000000,
48 	.test_ctl_hi1_val = 0x01800000,
49 	.user_ctl_val = 0x00000000,
50 	.user_ctl_hi_val = 0x00000805,
51 	.user_ctl_hi1_val = 0x00000000,
59 	.offset = 0x0,
74 	.l = 0x1a,
75 	.alpha = 0xaaa,
76 	.config_ctl_val = 0x20485699,
77 	.config_ctl_hi_val = 0x00002261,
78 	.config_ctl_hi1_val = 0x2a9a699c,
79 	.test_ctl_val = 0x00000000,
80 	.test_ctl_hi_val = 0x00000000,
81 	.test_ctl_hi1_val = 0x01800000,
82 	.user_ctl_val = 0x00000000,
83 	.user_ctl_hi_val = 0x00000805,
84 	.user_ctl_hi1_val = 0x00000000,
88 	.offset = 0x100,
103 	{ P_BI_TCXO, 0 },
119 	{ P_BI_TCXO, 0 },
133 	F(19200000, P_BI_TCXO, 1, 0, 0),
134 	F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
135 	F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0),
140 	.cmd_rcgr = 0x1120,
141 	.mnd_width = 0,
155 	F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0),
156 	F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),
157 	F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),
162 	.cmd_rcgr = 0x117c,
163 	.mnd_width = 0,
177 	.reg = 0x11c0,
178 	.shift = 0,
192 	.reg = 0x11bc,
193 	.shift = 0,
207 	.halt_reg = 0x1078,
210 		.enable_reg = 0x1078,
211 		.enable_mask = BIT(0),
225 	.halt_reg = 0x1170,
228 		.enable_reg = 0x1170,
229 		.enable_mask = BIT(0),
238 	.halt_reg = 0x107c,
241 		.enable_reg = 0x107c,
242 		.enable_mask = BIT(0),
256 	.halt_reg = 0x1088,
259 		.enable_reg = 0x1088,
260 		.enable_mask = BIT(0),
269 	.halt_reg = 0x1098,
272 		.enable_reg = 0x1098,
273 		.enable_mask = BIT(0),
287 	.halt_reg = 0x1080,
290 		.enable_reg = 0x1080,
291 		.enable_mask = BIT(0),
300 	.halt_reg = 0x1094,
303 		.enable_reg = 0x1094,
304 		.enable_mask = BIT(0),
313 	.halt_reg = 0x1084,
316 		.enable_reg = 0x1084,
317 		.enable_mask = BIT(0),
326 	.halt_reg = 0x108c,
329 		.enable_reg = 0x108c,
330 		.enable_mask = BIT(0),
339 	.halt_reg = 0x1004,
342 		.enable_reg = 0x1004,
343 		.enable_mask = BIT(0),
352 	.halt_reg = 0x109c,
355 		.enable_reg = 0x109c,
356 		.enable_mask = BIT(0),
365 	.halt_reg = 0x120c,
368 		.enable_reg = 0x120c,
369 		.enable_mask = BIT(0),
378 	.halt_reg = 0x1064,
381 		.enable_reg = 0x1064,
382 		.enable_mask = BIT(0),
396 	.halt_reg = 0x105c,
399 		.enable_reg = 0x105c,
400 		.enable_mask = BIT(0),
409 	.halt_reg = 0x1058,
412 		.enable_reg = 0x1058,
413 		.enable_mask = BIT(0),
422 	.halt_reg = 0x5000,
425 		.enable_reg = 0x5000,
426 		.enable_mask = BIT(0),
435 	.halt_reg = 0x1178,
438 		.enable_reg = 0x1178,
439 		.enable_mask = BIT(0),
453 	.halt_reg = 0x1204,
456 		.enable_reg = 0x1204,
457 		.enable_mask = BIT(0),
471 	.halt_reg = 0x802c,
474 		.enable_reg = 0x802c,
475 		.enable_mask = BIT(0),
484 	.halt_reg = 0x8030,
487 		.enable_reg = 0x8030,
488 		.enable_mask = BIT(0),
497 	.halt_reg = 0x1090,
500 		.enable_reg = 0x1090,
501 		.enable_mask = BIT(0),
510 	.gdscr = 0x106c,
511 	.gds_hw_ctrl = 0x1540,
520 	.gdscr = 0x100c,
521 	.clamp_io_ctrl = 0x1508,
561 	[GPUCC_GPU_CC_ACD_BCR] = { 0x1160 },
562 	[GPUCC_GPU_CC_CB_BCR] = { 0x116c },
563 	[GPUCC_GPU_CC_CX_BCR] = { 0x1068 },
564 	[GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 },
565 	[GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 },
566 	[GPUCC_GPU_CC_GMU_BCR] = { 0x111c },
567 	[GPUCC_GPU_CC_GX_BCR] = { 0x1008 },
568 	[GPUCC_GPU_CC_XO_BCR] = { 0x1000 },
580 	.max_register = 0x8030,