Lines Matching +full:0 +full:x2104
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
43 UNIPHIER_CLK_GATE("emmc", (idx), NULL, 0x210c, 2)
46 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x2104, 10)
49 UNIPHIER_CLK_GATE("stdmac", (idx), NULL, 0x210c, 8)
52 UNIPHIER_CLK_GATE("hsc", (idx), NULL, 0x210c, 9)
55 UNIPHIER_CLK_GATE("gio", (idx), NULL, 0x2104, 6)
58 UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
62 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
66 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2104, 13)
70 UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
74 UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
78 UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
81 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x2104, 12)
84 UNIPHIER_CLK_GATE("ether", (idx), NULL, 0x210c, 6)
91 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 16),
108 UNIPHIER_CLK_FACTOR("uart", 0, "a2pll", 1, 8),
116 UNIPHIER_CLK_GATE("ether-gb", 7, "gpll", 0x2104, 5),
118 UNIPHIER_CLK_GATE("ether-phy", 10, "ref", 0x2260, 0),
120 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
125 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 18),
126 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x2104, 19),
135 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 20),
150 UNIPHIER_CLK_FACTOR("uart", 0, "dapll2", 1, 40),
158 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
160 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x2108, 2),
167 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 27),
175 /* GIO is always clock-enabled: no function for 0x2104 bit6 */
176 UNIPHIER_PRO4_SYS_CLK_USB3(14, 0),
178 /* The document mentions 0x2104 bit 18, but not functional */
179 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x2104, 19),
182 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x2104, 20),
184 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x2104, 22),
194 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
213 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
216 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
229 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
240 /* GIO is always clock-enabled: no function for 0x210c bit5 */
245 UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
246 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 12),
247 UNIPHIER_CLK_GATE("usb30-hsphy1", 17, NULL, 0x210c, 13),
250 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 4),
258 UNIPHIER_CLK_CPUGEAR("cpu-ca72", 32, 0x8000, 0xf, 8,
261 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
264 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
274 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 34),
281 UNIPHIER_CLK_GATE("ether0", 6, NULL, 0x210c, 9),
282 UNIPHIER_CLK_GATE("ether1", 7, NULL, 0x210c, 10),
283 UNIPHIER_CLK_GATE("usb30", 12, NULL, 0x210c, 4), /* =GIO0 */
284 UNIPHIER_CLK_GATE("usb31-0", 13, NULL, 0x210c, 5), /* =GIO1 */
285 UNIPHIER_CLK_GATE("usb31-1", 14, NULL, 0x210c, 6), /* =GIO1-1 */
286 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 16),
287 UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 18),
288 UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 20),
289 UNIPHIER_CLK_GATE("usb31-hsphy0", 20, NULL, 0x210c, 17),
290 UNIPHIER_CLK_GATE("usb31-ssphy0", 21, NULL, 0x210c, 19),
291 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 3),
292 UNIPHIER_CLK_GATE("sata0", 28, NULL, 0x210c, 7),
293 UNIPHIER_CLK_GATE("sata1", 29, NULL, 0x210c, 8),
294 UNIPHIER_CLK_GATE("sata-phy", 30, NULL, 0x210c, 21),
301 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 8,
304 UNIPHIER_CLK_CPUGEAR("cpu-ipp", 34, 0x8100, 0xf, 8,
313 UNIPHIER_CLK_FACTOR("uart", 0, "spll", 1, 6),
316 UNIPHIER_CLK_GATE("emmc", 4, NULL, 0x2108, 8),
317 UNIPHIER_CLK_GATE("ether", 6, NULL, 0x210c, 0),
318 UNIPHIER_CLK_GATE("usb30-0", 12, NULL, 0x210c, 16), /* =GIO */
319 UNIPHIER_CLK_GATE("usb30-1", 13, NULL, 0x210c, 20), /* =GIO1P */
320 UNIPHIER_CLK_GATE("usb30-hsphy0", 16, NULL, 0x210c, 24),
321 UNIPHIER_CLK_GATE("usb30-ssphy0", 17, NULL, 0x210c, 25),
322 UNIPHIER_CLK_GATE("usb30-ssphy1", 18, NULL, 0x210c, 26),
323 UNIPHIER_CLK_GATE("pcie", 24, NULL, 0x210c, 8),
324 UNIPHIER_CLK_GATE("voc", 52, NULL, 0x2110, 0),
325 UNIPHIER_CLK_GATE("hdmitx", 58, NULL, 0x2110, 8),
328 UNIPHIER_CLK_CPUGEAR("cpu-ca53", 33, 0x8080, 0xf, 5,
339 .idx = 0,
343 .reg = 0x1a28,
344 .masks = { 0x1, 0x1, },
345 .vals = { 0x0, 0x1, },