Lines Matching +full:0 +full:x100008
21 #define QM_VF_AEQ_INT_SOURCE 0x0
22 #define QM_VF_AEQ_INT_MASK 0x4
23 #define QM_VF_EQ_INT_SOURCE 0x8
24 #define QM_VF_EQ_INT_MASK 0xc
26 #define QM_IRQ_VECTOR_MASK GENMASK(15, 0)
27 #define QM_IRQ_TYPE_MASK GENMASK(15, 0)
29 #define QM_ABN_IRQ_TYPE_MASK GENMASK(7, 0)
32 #define QM_MB_PING_ALL_VFS 0xffff
34 #define QM_MB_CMD_DATA_MASK GENMASK(31, 0)
38 #define QM_SQ_HOP_NUM_SHIFT 0
42 #define QM_SQ_PRIORITY_SHIFT 0
45 #define QM_QC_PASID_ENABLE 0x1
48 #define QM_SQ_TYPE_MASK GENMASK(3, 0)
49 #define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc)->w11) >> 6) & 0x1)
52 #define QM_CQ_HOP_NUM_SHIFT 0
56 #define QM_CQ_PHASE_SHIFT 0
59 #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
61 #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc)->w11) >> 6) & 0x1)
67 #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
68 #define QM_EQE_CQN_MASK GENMASK(15, 0)
70 #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
72 #define QM_AEQE_CQN_MASK GENMASK(15, 0)
73 #define QM_CQ_OVERFLOW 0
78 #define QM_XQ_DEPTH_MASK GENMASK(15, 0)
80 #define QM_DOORBELL_CMD_SQ 0
85 #define QM_DOORBELL_BASE_V1 0x340
89 #define QM_PAGE_SIZE 0x0034
90 #define QM_QP_DB_INTERVAL 0x10000
91 #define QM_DB_TIMEOUT_CFG 0x100074
92 #define QM_DB_TIMEOUT_SET 0x1fffff
94 #define QM_MEM_START_INIT 0x100040
95 #define QM_MEM_INIT_DONE 0x100044
96 #define QM_VFT_CFG_RDY 0x10006c
97 #define QM_VFT_CFG_OP_WR 0x100058
98 #define QM_VFT_CFG_TYPE 0x10005c
99 #define QM_VFT_CFG 0x100060
100 #define QM_VFT_CFG_OP_ENABLE 0x100054
101 #define QM_PM_CTRL 0x100148
104 #define QM_VFT_CFG_DATA_L 0x100064
105 #define QM_VFT_CFG_DATA_H 0x100068
118 #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(15, 0)
120 #define QM_SQC_VFT_NUM_MASK_V2 GENMASK(9, 0)
122 #define QM_ABNORMAL_INT_SOURCE 0x100000
123 #define QM_ABNORMAL_INT_MASK 0x100004
124 #define QM_ABNORMAL_INT_MASK_VALUE 0x7fff
125 #define QM_ABNORMAL_INT_STATUS 0x100008
126 #define QM_ABNORMAL_INT_SET 0x10000c
127 #define QM_ABNORMAL_INF00 0x100010
128 #define QM_FIFO_OVERFLOW_TYPE 0xc0
130 #define QM_FIFO_OVERFLOW_VF 0x3f
131 #define QM_ABNORMAL_INF01 0x100014
132 #define QM_DB_TIMEOUT_TYPE 0xc0
134 #define QM_DB_TIMEOUT_VF 0x3f
135 #define QM_RAS_CE_ENABLE 0x1000ec
136 #define QM_RAS_FE_ENABLE 0x1000f0
137 #define QM_RAS_NFE_ENABLE 0x1000f4
138 #define QM_RAS_CE_THRESHOLD 0x1000f8
140 #define QM_OOO_SHUTDOWN_SEL 0x1040f8
146 #define QM_PEH_VENDOR_ID 0x1000d8
147 #define ACC_VENDOR_ID_VALUE 0x5a5a
148 #define QM_PEH_DFX_INFO0 0x1000fc
149 #define QM_PEH_DFX_INFO1 0x100100
150 #define QM_PEH_DFX_MASK (BIT(0) | BIT(2))
153 #define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
154 #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
156 #define ACC_MASTER_TRANS_RETURN 0x300150
157 #define ACC_MASTER_GLOBAL_CTRL 0x300000
158 #define ACC_AM_CFG_PORT_WR_EN 0x30001c
160 #define ACC_AM_ROB_ECC_INT_STS 0x300104
165 #define QM_IFC_READY_STATUS 0x100128
166 #define QM_IFC_INT_SET_P 0x100130
167 #define QM_IFC_INT_CFG 0x100134
168 #define QM_IFC_INT_SOURCE_P 0x100138
169 #define QM_IFC_INT_SOURCE_V 0x0020
170 #define QM_IFC_INT_MASK 0x0024
171 #define QM_IFC_INT_STATUS 0x0028
172 #define QM_IFC_INT_SET_V 0x002C
173 #define QM_IFC_SEND_ALL_VFS GENMASK(6, 0)
174 #define QM_IFC_INT_SOURCE_CLR GENMASK(63, 0)
175 #define QM_IFC_INT_SOURCE_MASK BIT(0)
176 #define QM_IFC_INT_DISABLE BIT(0)
177 #define QM_IFC_INT_STATUS_MASK BIT(0)
178 #define QM_IFC_INT_SET_MASK BIT(0)
192 #define QM_CACHE_WB_START 0x204
193 #define QM_CACHE_WB_DONE 0x208
194 #define QM_FUNC_CAPS_REG 0x3100
195 #define QM_CAPBILITY_VERSION GENMASK(7, 0)
202 #define QM_PCI_COMMAND_INVALID ~0
213 #define QM_SHAPER_CIR_B_MASK GENMASK(7, 0)
224 #define QM_QOS_TICK 0x300U
225 #define QM_QOS_DIVISOR_CLK 0x1f40U
257 (qc)->head = 0; \
258 (qc)->tail = 0; \
261 (qc)->dw3 = 0; \
262 (qc)->w8 = 0; \
263 (qc)->rsvd0 = 0; \
265 (qc)->w11 = 0; \
266 (qc)->rsvd1 = 0; \
267 } while (0)
270 SQC_VFT = 0,
287 QM_PF_FLR_PREPARE = 0x01,
299 QM_TOTAL_QP_NUM_CAP = 0x0,
312 QM_EQ_IRQ_TYPE_CAP_IDX = 0x0,
319 {QM_SUPPORT_DB_ISOLATION, 0x30, 0, BIT(0), 0x0, 0x0, 0x0},
320 {QM_SUPPORT_FUNC_QOS, 0x3100, 0, BIT(8), 0x0, 0x0, 0x1},
321 {QM_SUPPORT_STOP_QP, 0x3100, 0, BIT(9), 0x0, 0x0, 0x1},
322 {QM_SUPPORT_MB_COMMAND, 0x3100, 0, BIT(11), 0x0, 0x0, 0x1},
323 {QM_SUPPORT_SVA_PREFETCH, 0x3100, 0, BIT(14), 0x0, 0x0, 0x1},
327 {QM_SUPPORT_RPM, 0x3100, 0, BIT(13), 0x0, 0x0, 0x1},
331 {QM_SUPPORT_RPM, 0x3100, 0, BIT(12), 0x0, 0x0, 0x0},
335 {QM_TOTAL_QP_NUM_CAP, 0x100158, 0, GENMASK(10, 0), 0x1000, 0x400, 0x400},
336 {QM_FUNC_MAX_QP_CAP, 0x100158, 11, GENMASK(10, 0), 0x1000, 0x400, 0x400},
337 {QM_XEQ_DEPTH_CAP, 0x3104, 0, GENMASK(31, 0), 0x800, 0x4000800, 0x4000800},
338 {QM_QP_DEPTH_CAP, 0x3108, 0, GENMASK(31, 0), 0x4000400, 0x4000400, 0x4000400},
339 {QM_EQ_IRQ_TYPE_CAP, 0x310c, 0, GENMASK(31, 0), 0x10000, 0x10000, 0x10000},
340 {QM_AEQ_IRQ_TYPE_CAP, 0x3110, 0, GENMASK(31, 0), 0x0, 0x10001, 0x10001},
341 {QM_ABN_IRQ_TYPE_CAP, 0x3114, 0, GENMASK(31, 0), 0x0, 0x10003, 0x10003},
342 {QM_PF2VF_IRQ_TYPE_CAP, 0x3118, 0, GENMASK(31, 0), 0x0, 0x0, 0x10002},
343 {QM_PF_IRQ_NUM_CAP, 0x311c, 16, GENMASK(15, 0), 0x1, 0x4, 0x4},
344 {QM_VF_IRQ_NUM_CAP, 0x311c, 0, GENMASK(15, 0), 0x1, 0x2, 0x3},
402 { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
444 {1100, 100000, 0},
495 enum qp_state qp_curr = 0; in qm_qp_avail_state()
564 int delay = 0; in qm_wait_reset_finish()
573 return 0; in qm_wait_reset_finish()
606 ((op) ? 0x1 << QM_MB_OP_SHIFT : 0) | in qm_mb_pre_init()
607 (0x1 << QM_MB_BUSY_SHIFT)); in qm_mb_pre_init()
611 mailbox->rsvd = 0; in qm_mb_pre_init()
614 /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
621 0x1), POLL_PERIOD, POLL_TIMEOUT); in hisi_qm_wait_mb_ready()
631 unsigned long tmp0 = 0, tmp1 = 0; in qm_mb_write()
641 asm volatile("ldp %0, %1, %3\n" in qm_mb_write()
642 "stp %0, %1, %2\n" in qm_mb_write()
678 return 0; in qm_mb_nolock()
718 u16 randata = 0; in qm_db_v2()
760 writel(0x1, qm->io_base + QM_MEM_START_INIT); in qm_dev_mem_reset()
762 val & BIT(0), POLL_PERIOD, in qm_dev_mem_reset()
771 * @is_read: Whether read from reg, 0: not support read from reg.
814 return 0; in hisi_qm_set_algs()
826 for (i = 0; i < dev_algs_size; i++) in hisi_qm_set_algs()
832 *ptr = '\0'; in hisi_qm_set_algs()
836 return 0; in hisi_qm_set_algs()
854 return 0; in qm_pm_get_sync()
857 if (ret < 0) { in qm_pm_get_sync()
862 return 0; in qm_pm_get_sync()
880 qp->qp_status.cq_head = 0; in qm_cq_head_update()
898 qp->qp_status.cq_head, 0); in qm_poll_req_cb()
917 for (i = eqe_num - 1; i >= 0; i--) { in qm_work_process()
937 u16 cqn, eqe_num = 0; in qm_get_complete_eqe_num()
941 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_get_complete_eqe_num()
958 qm->status.eq_head = 0; in qm_get_complete_eqe_num()
970 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_get_complete_eqe_num()
1089 qm->status.aeq_head = 0; in qm_aeq_thread()
1096 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); in qm_aeq_thread()
1105 qp_status->sq_tail = 0; in qm_init_qp_status()
1106 qp_status->cq_head = 0; in qm_init_qp_status()
1108 atomic_set(&qp_status->used, 0); in qm_init_qp_status()
1114 u32 page_type = 0x0; in qm_init_prefetch()
1121 page_type = 0x0; in qm_init_prefetch()
1124 page_type = 0x1; in qm_init_prefetch()
1127 page_type = 0x2; in qm_init_prefetch()
1158 for (i = 0; i < table_size; i++) { in acc_shaper_calc_cbs_s()
1171 for (i = 0; i < table_size; i++) { in acc_shaper_calc_cir_s()
1176 return 0; in acc_shaper_calc_cir_s()
1188 for (cir_u = 0; cir_u <= QM_QOS_MAX_CIR_U; cir_u++) { in qm_get_shaper_para()
1196 return 0; in qm_get_shaper_para()
1207 u64 tmp = 0; in qm_vft_data_cfg()
1209 if (number > 0) { in qm_vft_data_cfg()
1261 val & BIT(0), POLL_PERIOD, in qm_set_vft_common()
1266 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR); in qm_set_vft_common()
1275 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_set_vft_common()
1276 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_set_vft_common()
1279 val & BIT(0), POLL_PERIOD, in qm_set_vft_common()
1301 return 0; in qm_shaper_init_vft()
1323 return 0; in qm_set_sqc_cqc_vft()
1326 qm_set_vft_common(qm, i, fun_num, 0, 0); in qm_set_sqc_cqc_vft()
1336 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1); in qm_get_vft_v2()
1346 return 0; in qm_get_vft_v2()
1449 writel(0x0, qm->io_base + QM_OOO_SHUTDOWN_SEL); in qm_hw_error_uninit_v3()
1459 for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) { in qm_log_hw_error()
1464 dev_err(dev, "%s [error status=0x%x] found\n", in qm_log_hw_error()
1517 qm_mb_pre_init(&mailbox, QM_MB_CMD_DST, 0, fun_num, 0); in qm_get_mb_cmd()
1577 int cnt = 0; in qm_wait_vf_prepare_finish()
1578 int ret = 0; in qm_wait_vf_prepare_finish()
1583 return 0; in qm_wait_vf_prepare_finish()
1640 int cnt = 0; in qm_ping_single_vf()
1644 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, fun_num, 0); in qm_ping_single_vf()
1677 u64 val = 0; in qm_ping_all_vfs()
1678 int cnt = 0; in qm_ping_all_vfs()
1682 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, QM_MB_PING_ALL_VFS, 0); in qm_ping_all_vfs()
1699 return 0; in qm_ping_all_vfs()
1720 int cnt = 0; in qm_ping_pf()
1724 qm_mb_pre_init(&mailbox, QM_MB_CMD_SRC, cmd, 0, 0); in qm_ping_pf()
1753 return hisi_qm_mb(qp->qm, QM_MB_CMD_STOP_QP, 0, qp->qp_id, 0); in qm_stop_qp()
1762 0); in qm_set_msi()
1768 return 0; in qm_set_msi()
1775 return 0; in qm_set_msi()
1781 u32 cmd = ~0; in qm_wait_msi_finish()
1782 int cnt = 0; in qm_wait_msi_finish()
1827 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_msi_v3()
1830 return 0; in qm_set_msi_v3()
1837 ret = 0; in qm_set_msi_v3()
1884 *addr = 0; in hisi_qm_unset_hw_reset()
1903 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC); in qm_create_qp_nolock()
1904 if (qp_id < 0) { in qm_create_qp_nolock()
1913 memset(qp->cqe, 0, sizeof(struct qm_cqe) * qp->cq_depth); in qm_create_qp_nolock()
1992 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size)); in qm_sq_ctx_cfg()
1996 sqc->w8 = 0; /* rand_qc */ in qm_sq_ctx_cfg()
1999 sqc->w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type)); in qm_sq_ctx_cfg()
2012 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0); in qm_sq_ctx_cfg()
2034 cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, in qm_cq_ctx_cfg()
2039 cqc->w8 = 0; /* rand_qc */ in qm_cq_ctx_cfg()
2053 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0); in qm_cq_ctx_cfg()
2091 return 0; in qm_start_qp_nolock()
2099 * After this function, qp can receive request from user. Return 0 if
2131 for (i = 0; i < qp_used; i++) { in qp_stop_fail_cb()
2153 int ret = 0, i = 0; in qm_drain_qp()
2158 return 0; in qm_drain_qp()
2221 return 0; in qm_stop_qp_nolock()
2240 return 0; in qm_stop_qp_nolock()
2247 * This function is reverse of hisi_qm_start_qp. Return 0 if successful.
2274 * done function should clear used sqe to 0.
2295 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0); in hisi_qp_send()
2299 return 0; in hisi_qp_send()
2310 writel(0x1, qm->io_base + QM_CACHE_WB_START); in hisi_qm_cache_wb()
2312 val, val & BIT(0), POLL_PERIOD, in hisi_qm_cache_wb()
2339 for (i = 0; i < qm->qp_num; i++) in hisi_qm_set_hw_reset()
2349 u8 alg_type = 0; in hisi_qm_uacce_get_queue()
2362 return 0; in hisi_qm_uacce_get_queue()
2411 * dma_mmap_coherent() requires vm_pgoff as 0 in hisi_qm_uacce_mmap()
2415 vma->vm_pgoff = 0; in hisi_qm_uacce_mmap()
2442 int updated = 0; in hisi_qm_is_q_updated()
2477 if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1) in hisi_qm_uacce_ioctl()
2487 return 0; in hisi_qm_uacce_ioctl()
2501 return 0; in hisi_qm_uacce_ioctl()
2516 u32 count = 0; in qm_hw_err_isolate()
2524 return 0; in qm_hw_err_isolate()
2553 return 0; in qm_hw_err_isolate()
2598 return 0; in hisi_qm_isolate_threshold_write()
2654 if (ret < 0) in qm_alloc_uacce()
2701 return 0; in qm_alloc_uacce()
2714 return 0; in qm_frozen()
2722 return 0; in qm_frozen()
2735 int ret = 0; in qm_try_frozen_vfs()
2791 for (i = num - 1; i >= 0; i--) { in hisi_qp_memory_uninit()
2830 return 0; in hisi_qp_memory_init()
2851 qm->qp_in_used = 0; in hisi_qm_pre_init()
2999 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
3001 * (VF function number 0x2)
3019 status->eq_head = 0; in qm_init_eq_aeq_status()
3020 status->aeq_head = 0; in qm_init_eq_aeq_status()
3028 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0); in qm_enable_eq_aeq_interrupts()
3029 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0); in qm_enable_eq_aeq_interrupts()
3031 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK); in qm_enable_eq_aeq_interrupts()
3032 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK); in qm_enable_eq_aeq_interrupts()
3037 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK); in qm_disable_eq_aeq_interrupts()
3038 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK); in qm_disable_eq_aeq_interrupts()
3065 ret = hisi_qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0); in qm_eq_ctx_cfg()
3094 ret = hisi_qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0); in qm_aeq_ctx_cfg()
3124 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num); in __hisi_qm_start()
3133 ret = hisi_qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0); in __hisi_qm_start()
3137 ret = hisi_qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0); in __hisi_qm_start()
3144 return 0; in __hisi_qm_start()
3156 int ret = 0; in hisi_qm_start()
3168 dev_err(dev, "qp_num should not be 0\n"); in hisi_qm_start()
3191 if (ret < 0) in qm_restart()
3195 for (i = 0; i < qm->qp_num; i++) { in qm_restart()
3199 ret = qm_start_qp_nolock(qp, 0); in qm_restart()
3200 if (ret < 0) { in qm_restart()
3211 return 0; in qm_restart()
3221 for (i = 0; i < qm->qp_num; i++) { in qm_stop_started_qp()
3226 if (ret < 0) { in qm_stop_started_qp()
3233 return 0; in qm_stop_started_qp()
3248 for (i = 0; i < qm->qp_num; i++) { in qm_clear_queues()
3251 memset(qp->qdma.va, 0, qp->qdma.size); in qm_clear_queues()
3254 memset(qm->qdma.va, 0, qm->qdma.size); in qm_clear_queues()
3269 int ret = 0; in hisi_qm_stop()
3283 if (ret < 0) { in hisi_qm_stop()
3292 ret = hisi_qm_set_vft(qm, 0, 0, 0); in hisi_qm_stop()
3293 if (ret < 0) { in hisi_qm_stop()
3390 if (!qps || qp_num <= 0) in hisi_qm_free_qps()
3393 for (i = qp_num - 1; i >= 0; i--) in hisi_qm_free_qps()
3421 if (dev_node < 0) in hisi_qm_sort_devices()
3422 dev_node = 0; in hisi_qm_sort_devices()
3440 return 0; in hisi_qm_sort_devices()
3463 if (!qps || !qm_list || qp_num <= 0) in hisi_qm_alloc_qps_node()
3473 for (i = 0; i < qp_num; i++) { in hisi_qm_alloc_qps_node()
3482 ret = 0; in hisi_qm_alloc_qps_node()
3517 for (i = num_vfs; i > 0; i--) { in qm_vf_q_assign()
3524 remain_q_num = 0; in qm_vf_q_assign()
3525 } else if (remain_q_num > 0) { in qm_vf_q_assign()
3536 hisi_qm_set_vft(qm, j, 0, 0); in qm_vf_q_assign()
3542 return 0; in qm_vf_q_assign()
3551 ret = hisi_qm_set_vft(qm, i, 0, 0); in qm_clear_vft_config()
3555 qm->vfs_num = 0; in qm_clear_vft_config()
3557 return 0; in qm_clear_vft_config()
3587 return 0; in qm_func_shaper_enable()
3592 u64 cir_u = 0, cir_b = 0, cir_s = 0; in qm_get_shaper_vft_qos()
3599 val & BIT(0), POLL_PERIOD, in qm_get_shaper_vft_qos()
3602 return 0; in qm_get_shaper_vft_qos()
3604 writel(0x1, qm->io_base + QM_VFT_CFG_OP_WR); in qm_get_shaper_vft_qos()
3608 writel(0x0, qm->io_base + QM_VFT_CFG_RDY); in qm_get_shaper_vft_qos()
3609 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE); in qm_get_shaper_vft_qos()
3612 val & BIT(0), POLL_PERIOD, in qm_get_shaper_vft_qos()
3615 return 0; in qm_get_shaper_vft_qos()
3634 return 0; in qm_get_shaper_vft_qos()
3661 int cnt = 0; in qm_vf_read_qos()
3665 qm->mb_qos = 0; in qm_vf_read_qos()
3708 ir = qm_get_shaper_vft_qos(qm, 0); in qm_algqos_read()
3733 char tbuf_bdf[QM_DBG_READ_LEN] = {0}; in qm_get_qos_value()
3734 char val_buf[QM_DBG_READ_LEN] = {0}; in qm_get_qos_value()
3744 if (ret || *val == 0 || *val > QM_QOS_MAX_VAL) { in qm_get_qos_value()
3759 return 0; in qm_get_qos_value()
3771 if (*pos != 0) in qm_algqos_write()
3772 return 0; in qm_algqos_write()
3778 if (len < 0) in qm_algqos_write()
3781 tbuf[len] = '\0'; in qm_algqos_write()
3940 return 0; in hisi_qm_sriov_disable()
3949 * Enable SR-IOV according to num_vfs, 0 means disable.
3953 if (num_vfs == 0) in hisi_qm_sriov_configure()
4039 return 0; in qm_check_req_recv()
4073 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_pf_mse()
4076 return 0; in qm_set_pf_mse()
4099 for (i = 0; i < MAX_WAIT_COUNTS; i++) { in qm_set_vf_mse()
4103 return 0; in qm_set_vf_mse()
4118 int ret = 0; in qm_vf_reset_prepare()
4148 return 0; in qm_try_stop_vfs()
4202 return 0; in qm_controller_reset_prepare()
4207 u32 nfe_enb = 0; in qm_dev_ecc_mbit_handle()
4279 unsigned long long value = 0; in qm_soft_reset()
4299 return 0; in qm_soft_reset()
4308 int ret = 0; in qm_vf_reset_done()
4337 return 0; in qm_try_start_vfs()
4477 return 0; in qm_controller_reset_done()
4509 return 0; in qm_controller_reset()
4551 u32 delay = 0; in hisi_qm_reset_prepare()
4770 val == BIT(0), QM_VF_RESET_WAIT_US, in qm_wait_pf_reset_finish()
4782 ret = qm_get_mb_cmd(qm, &msg, 0); in qm_wait_pf_reset_finish()
4783 qm_clear_cmd_interrupt(qm, 0); in qm_wait_pf_reset_finish()
4884 qm_handle_cmd_msg(qm, 0); in qm_cmd_process()
4898 int flag = 0; in hisi_qm_alg_register()
4899 int ret = 0; in hisi_qm_alg_register()
4909 return 0; in hisi_qm_alg_register()
4971 return 0; in qm_register_abnormal_irq()
4975 return 0; in qm_register_abnormal_irq()
4978 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_abnormal_irq, 0, qm->dev_name, qm); in qm_register_abnormal_irq()
5006 return 0; in qm_register_mb_cmd_irq()
5009 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_mb_cmd_irq, 0, qm->dev_name, qm); in qm_register_mb_cmd_irq()
5037 return 0; in qm_register_aeq_irq()
5069 return 0; in qm_register_eq_irq()
5072 ret = request_irq(pci_irq_vector(pdev, irq_vector), qm_eq_irq, 0, qm->dev_name, qm); in qm_register_eq_irq()
5107 return 0; in qm_irqs_register()
5129 return 0; in qm_get_qp_num()
5138 return 0; in qm_get_qp_num()
5152 return 0; in qm_get_qp_num()
5166 for (i = 0; i < size; i++) { in qm_pre_store_irq_type_caps()
5174 return 0; in qm_pre_store_irq_type_caps()
5203 for (i = 0; i < size; i++) { in qm_get_hw_caps()
5220 if (ret < 0) { in qm_get_pci_res()
5248 qm->db_interval = 0; in qm_get_pci_res()
5255 return 0; in qm_get_pci_res()
5275 if (ret < 0) { in hisi_qm_pci_init()
5285 if (ret < 0) in hisi_qm_pci_init()
5291 if (ret < 0) { in hisi_qm_pci_init()
5296 return 0; in hisi_qm_pci_init()
5309 for (i = 0; i < qm->qp_num; i++) in hisi_qm_init_work()
5326 return 0; in hisi_qm_init_work()
5351 for (i = 0; i < qm->qp_num; i++) { in hisi_qp_alloc_memory()
5360 return 0; in hisi_qp_alloc_memory()
5371 size_t off = 0; in hisi_qm_memory_init()
5380 qm->factor[0].func_qos = QM_QOS_MAX_VAL; in hisi_qm_memory_init()
5387 } while (0) in hisi_qm_memory_init()
5412 return 0; in hisi_qm_memory_init()
5459 if (ret < 0) in hisi_qm_init()
5474 return 0; in hisi_qm_init()
5678 return 0; in hisi_qm_resume()