1 // SPDX-License-Identifier: GPL-2.0
3  * Renesas RZ/G2L IRQC Driver
7  * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
67 	return data->domain->host_data;  in irq_data_to_priv()
72 	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;  in rzg2l_irq_eoi()
77 	reg = readl_relaxed(priv->base + ISCR);  in rzg2l_irq_eoi()
79 		writel_relaxed(reg & ~bit, priv->base + ISCR);  in rzg2l_irq_eoi()
84 	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_TINT_START;  in rzg2l_tint_eoi()
89 	reg = readl_relaxed(priv->base + TSCR);  in rzg2l_tint_eoi()
91 		writel_relaxed(reg & ~bit, priv->base + TSCR);  in rzg2l_tint_eoi()
99 	raw_spin_lock(&priv->lock);  in rzg2l_irqc_eoi()
104 	raw_spin_unlock(&priv->lock);  in rzg2l_irqc_eoi()
114 		u32 offset = hw_irq - IRQC_TINT_START;  in rzg2l_irqc_irq_disable()
119 		raw_spin_lock(&priv->lock);  in rzg2l_irqc_irq_disable()
120 		reg = readl_relaxed(priv->base + TSSR(tssr_index));  in rzg2l_irqc_irq_disable()
122 		writel_relaxed(reg, priv->base + TSSR(tssr_index));  in rzg2l_irqc_irq_disable()
123 		raw_spin_unlock(&priv->lock);  in rzg2l_irqc_irq_disable()
135 		u32 offset = hw_irq - IRQC_TINT_START;  in rzg2l_irqc_irq_enable()
140 		raw_spin_lock(&priv->lock);  in rzg2l_irqc_irq_enable()
141 		reg = readl_relaxed(priv->base + TSSR(tssr_index));  in rzg2l_irqc_irq_enable()
143 		writel_relaxed(reg, priv->base + TSSR(tssr_index));  in rzg2l_irqc_irq_enable()
144 		raw_spin_unlock(&priv->lock);  in rzg2l_irqc_irq_enable()
151 	unsigned int hw_irq = irqd_to_hwirq(d) - IRQC_IRQ_START;  in rzg2l_irq_set_type()
173 		return -EINVAL;  in rzg2l_irq_set_type()
176 	raw_spin_lock(&priv->lock);  in rzg2l_irq_set_type()
177 	tmp = readl_relaxed(priv->base + IITSR);  in rzg2l_irq_set_type()
180 	writel_relaxed(tmp, priv->base + IITSR);  in rzg2l_irq_set_type()
181 	raw_spin_unlock(&priv->lock);  in rzg2l_irq_set_type()
190 	u32 titseln = hwirq - IRQC_TINT_START;  in rzg2l_tint_set_edge()
205 		return -EINVAL;  in rzg2l_tint_set_edge()
210 		titseln -= TITSR0_MAX_INT;  in rzg2l_tint_set_edge()
214 	raw_spin_lock(&priv->lock);  in rzg2l_tint_set_edge()
215 	reg = readl_relaxed(priv->base + offset);  in rzg2l_tint_set_edge()
218 	writel_relaxed(reg, priv->base + offset);  in rzg2l_tint_set_edge()
219 	raw_spin_unlock(&priv->lock);  in rzg2l_tint_set_edge()
227 	int ret = -EINVAL;  in rzg2l_irqc_set_type()
240 	.name			= "rzg2l-irqc",
258 	struct rzg2l_irqc_priv *priv = domain->host_data;  in rzg2l_irqc_alloc()
269 	 * For TINT interrupts ie where pinctrl driver is child of irqc domain  in rzg2l_irqc_alloc()
270 	 * the hwirq and TINT are encoded in fwspec->param[0].  in rzg2l_irqc_alloc()
271 	 * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT  in rzg2l_irqc_alloc()
272 	 * from 16-31 bits. TINT from the pinctrl driver needs to be programmed  in rzg2l_irqc_alloc()
273 	 * in IRQC registers to enable a given gpio pin as interrupt.  in rzg2l_irqc_alloc()
280 			return -EINVAL;  in rzg2l_irqc_alloc()
283 	if (hwirq > (IRQC_NUM_IRQ - 1))  in rzg2l_irqc_alloc()
284 		return -EINVAL;  in rzg2l_irqc_alloc()
291 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);  in rzg2l_irqc_alloc()
312 					  &priv->fwspec[i]);  in rzg2l_irqc_parse_interrupts()
328 		return -ENODEV;  in rzg2l_irqc_init()
332 		dev_err(&pdev->dev, "cannot find parent domain\n");  in rzg2l_irqc_init()
333 		return -ENODEV;  in rzg2l_irqc_init()
336 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in rzg2l_irqc_init()
338 		return -ENOMEM;  in rzg2l_irqc_init()
340 	priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);  in rzg2l_irqc_init()
341 	if (IS_ERR(priv->base))  in rzg2l_irqc_init()
342 		return PTR_ERR(priv->base);  in rzg2l_irqc_init()
346 		dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);  in rzg2l_irqc_init()
350 	resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);  in rzg2l_irqc_init()
356 		dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);  in rzg2l_irqc_init()
360 	pm_runtime_enable(&pdev->dev);  in rzg2l_irqc_init()
361 	ret = pm_runtime_resume_and_get(&pdev->dev);  in rzg2l_irqc_init()
363 		dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);  in rzg2l_irqc_init()
367 	raw_spin_lock_init(&priv->lock);  in rzg2l_irqc_init()
373 		dev_err(&pdev->dev, "failed to add irq domain\n");  in rzg2l_irqc_init()
374 		ret = -ENOMEM;  in rzg2l_irqc_init()
381 	pm_runtime_put(&pdev->dev);  in rzg2l_irqc_init()
383 	pm_runtime_disable(&pdev->dev);  in rzg2l_irqc_init()
389 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
391 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
392 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");