Lines Matching +full:mt7530 +full:- +full:dsa +full:- +full:port
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Mediatek MT7530 DSA Switch driver
23 #include <net/dsa.h>
25 #include "mt7530.h"
85 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
104 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
108 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
117 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_write_mmd_indirect()
136 ret = bus->write(bus, 0, MII_MMD_DATA, data); in core_write_mmd_indirect()
139 dev_err(&bus->dev, in core_write_mmd_indirect()
147 if (priv->bus) in mt7530_mutex_lock()
148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
154 if (priv->bus) in mt7530_mutex_unlock()
155 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
200 ret = regmap_write(priv->regmap, reg, val); in mt7530_mii_write()
203 dev_err(priv->dev, in mt7530_mii_write()
204 "failed to write mt7530 register\n"); in mt7530_mii_write()
215 ret = regmap_read(priv->regmap, reg, &val); in mt7530_mii_read()
218 dev_err(priv->dev, in mt7530_mii_read()
219 "failed to read mt7530 register\n"); in mt7530_mii_read()
239 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
247 mt7530_mutex_lock(p->priv); in _mt7530_read()
249 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
251 mt7530_mutex_unlock(p->priv); in _mt7530_read()
271 regmap_update_bits(priv->regmap, reg, mask, set); in mt7530_rmw()
303 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
312 return -EINVAL; in mt7530_fdb_cmd()
330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
376 /* Set up switch core clock for MT7530 */
402 /* If port 6 is available as a CPU port, always prefer that as the default,
416 /* Setup port 6 interface mode and TRGMII TX circuit */
420 struct mt7530_priv *priv = ds->priv; in mt7530_pad_clk_setup()
426 dev_err(priv->dev, in mt7530_pad_clk_setup()
427 "%s: MT7530 with a 20MHz XTAL is not supported!\n", in mt7530_pad_clk_setup()
429 return -EINVAL; in mt7530_pad_clk_setup()
442 if (priv->id == ID_MT7621) { in mt7530_pad_clk_setup()
456 dev_err(priv->dev, "xMII interface %d not supported\n", in mt7530_pad_clk_setup()
458 return -EINVAL; in mt7530_pad_clk_setup()
465 /* Disable the MT7530 TRGMII clocks */ in mt7530_pad_clk_setup()
468 /* Setup the MT7530 TRGMII Tx Clock */ in mt7530_pad_clk_setup()
483 /* Enable the MT7530 TRGMII clocks */ in mt7530_pad_clk_setup()
598 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
604 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) in mt7530_phy_read_c22() argument
606 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read_c22()
609 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, in mt7530_phy_write_c22() argument
612 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write_c22()
615 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, in mt7530_phy_read_c45() argument
618 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); in mt7530_phy_read_c45()
621 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, in mt7530_phy_write_c45() argument
624 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); in mt7530_phy_write_c45()
628 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_read() argument
642 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
646 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_read()
653 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
657 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_read()
664 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
676 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, in mt7531_ind_c45_phy_write() argument
690 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
694 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_write()
701 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
705 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c45_phy_write()
712 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
723 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) in mt7531_ind_c22_phy_read() argument
736 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
740 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c22_phy_read()
748 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
760 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, in mt7531_ind_c22_phy_write() argument
774 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
778 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | in mt7531_ind_c22_phy_write()
786 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
797 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) in mt753x_phy_read_c22() argument
799 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c22()
801 return priv->info->phy_read_c22(priv, port, regnum); in mt753x_phy_read_c22()
805 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) in mt753x_phy_read_c45() argument
807 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c45()
809 return priv->info->phy_read_c45(priv, port, devad, regnum); in mt753x_phy_read_c45()
813 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) in mt753x_phy_write_c22() argument
815 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c22()
817 return priv->info->phy_write_c22(priv, port, regnum, val); in mt753x_phy_write_c22()
821 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, in mt753x_phy_write_c45() argument
824 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c45()
826 return priv->info->phy_write_c45(priv, port, devad, regnum, val); in mt753x_phy_write_c45()
830 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, in mt7530_get_strings() argument
844 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, in mt7530_get_ethtool_stats() argument
847 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; in mt7530_get_ethtool_stats()
857 if (mib->size == 2) { in mt7530_get_ethtool_stats()
865 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) in mt7530_get_sset_count() argument
876 struct mt7530_priv *priv = ds->priv; in mt7530_set_ageing_time()
879 unsigned int error = -1; in mt7530_set_ageing_time()
885 return -ERANGE; in mt7530_set_ageing_time()
889 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; in mt7530_set_ageing_time()
892 unsigned int tmp_error = secs - in mt7530_set_ageing_time()
933 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
937 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
944 switch (priv->p5_intf_sel) { in mt7530_setup_port5()
946 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ in mt7530_setup_port5()
950 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ in mt7530_setup_port5()
953 /* Setup the MAC by default for the cpu port */ in mt7530_setup_port5()
957 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ in mt7530_setup_port5()
964 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", in mt7530_setup_port5()
965 priv->p5_intf_sel); in mt7530_setup_port5()
976 /* Don't set delay in DSA mode */ in mt7530_setup_port5()
977 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
993 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", in mt7530_setup_port5()
994 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); in mt7530_setup_port5()
996 priv->p5_interface = interface; in mt7530_setup_port5()
999 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
1005 /* Trap BPDUs to the CPU port(s) */ in mt753x_trap_frames()
1009 /* Trap 802.1X PAE frames to the CPU port(s) */ in mt753x_trap_frames()
1013 /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ in mt753x_trap_frames()
1019 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) in mt753x_cpu_port_enable() argument
1021 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
1024 /* Setup max capability of CPU port at first */ in mt753x_cpu_port_enable()
1025 if (priv->info->cpu_port_config) { in mt753x_cpu_port_enable()
1026 ret = priv->info->cpu_port_config(ds, port); in mt753x_cpu_port_enable()
1031 /* Enable Mediatek header mode on the cpu port */ in mt753x_cpu_port_enable()
1032 mt7530_write(priv, MT7530_PVC_P(port), in mt753x_cpu_port_enable()
1035 /* Enable flooding on the CPU port */ in mt753x_cpu_port_enable()
1036 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | in mt753x_cpu_port_enable()
1037 UNU_FFP(BIT(port))); in mt753x_cpu_port_enable()
1039 /* Set CPU port number */ in mt753x_cpu_port_enable()
1040 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) in mt753x_cpu_port_enable()
1041 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); in mt753x_cpu_port_enable()
1043 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on in mt753x_cpu_port_enable()
1044 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that in mt753x_cpu_port_enable()
1045 * is affine to the inbound user port. in mt753x_cpu_port_enable()
1047 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) in mt753x_cpu_port_enable()
1048 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); in mt753x_cpu_port_enable()
1050 /* CPU port gets connected to all user ports of in mt753x_cpu_port_enable()
1053 mt7530_write(priv, MT7530_PCR_P(port), in mt753x_cpu_port_enable()
1054 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
1057 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt753x_cpu_port_enable()
1064 mt7530_port_enable(struct dsa_switch *ds, int port, in mt7530_port_enable() argument
1067 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_enable()
1068 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
1070 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
1072 /* Allow the user port gets connected to the cpu port and also in mt7530_port_enable()
1073 * restore the port matrix if the port is the member of a certain in mt7530_port_enable()
1077 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_enable()
1079 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_enable()
1081 priv->ports[port].enable = true; in mt7530_port_enable()
1082 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_enable()
1083 priv->ports[port].pm); in mt7530_port_enable()
1084 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); in mt7530_port_enable()
1086 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1092 mt7530_port_disable(struct dsa_switch *ds, int port) in mt7530_port_disable() argument
1094 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1096 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1098 /* Clear up all port matrix which could be restored in the next in mt7530_port_disable()
1099 * enablement for the port. in mt7530_port_disable()
1101 priv->ports[port].enable = false; in mt7530_port_disable()
1102 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_disable()
1104 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); in mt7530_port_disable()
1106 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1110 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) in mt7530_port_change_mtu() argument
1112 struct mt7530_priv *priv = ds->priv; in mt7530_port_change_mtu()
1116 /* When a new MTU is set, DSA always set the CPU port's MTU to the in mt7530_port_change_mtu()
1118 * RX length register, only allowing CPU port here is enough. in mt7530_port_change_mtu()
1120 if (!dsa_is_cpu_port(ds, port)) in mt7530_port_change_mtu()
1150 mt7530_port_max_mtu(struct dsa_switch *ds, int port) in mt7530_port_max_mtu() argument
1156 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) in mt7530_stp_state_set() argument
1158 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1180 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), in mt7530_stp_state_set()
1185 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, in mt7530_port_pre_bridge_flags() argument
1191 return -EINVAL; in mt7530_port_pre_bridge_flags()
1197 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, in mt7530_port_bridge_flags() argument
1201 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_flags()
1204 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, in mt7530_port_bridge_flags()
1208 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), in mt7530_port_bridge_flags()
1209 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1212 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), in mt7530_port_bridge_flags()
1213 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1216 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), in mt7530_port_bridge_flags()
1217 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); in mt7530_port_bridge_flags()
1223 mt7530_port_bridge_join(struct dsa_switch *ds, int port, in mt7530_port_bridge_join() argument
1227 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; in mt7530_port_bridge_join()
1228 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_bridge_join()
1229 u32 port_bitmap = BIT(cpu_dp->index); in mt7530_port_bridge_join()
1230 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1232 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1235 int other_port = other_dp->index; in mt7530_port_bridge_join()
1240 /* Add this port to the port matrix of the other ports in the in mt7530_port_bridge_join()
1241 * same bridge. If the port is disabled, port matrix is kept in mt7530_port_bridge_join()
1242 * and not being setup until the port becomes enabled. in mt7530_port_bridge_join()
1247 if (priv->ports[other_port].enable) in mt7530_port_bridge_join()
1249 PCR_MATRIX(BIT(port))); in mt7530_port_bridge_join()
1250 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); in mt7530_port_bridge_join()
1255 /* Add the all other ports to this port matrix. */ in mt7530_port_bridge_join()
1256 if (priv->ports[port].enable) in mt7530_port_bridge_join()
1257 mt7530_rmw(priv, MT7530_PCR_P(port), in mt7530_port_bridge_join()
1259 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); in mt7530_port_bridge_join()
1262 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_bridge_join()
1265 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1271 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_unaware() argument
1273 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1277 /* This is called after .port_bridge_leave when leaving a VLAN-aware in mt7530_port_set_vlan_unaware()
1280 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) in mt7530_port_set_vlan_unaware()
1281 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_unaware()
1284 mt7530_rmw(priv, MT7530_PVC_P(port), in mt7530_port_set_vlan_unaware()
1291 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_set_vlan_unaware()
1302 /* CPU port also does the same thing until all user ports belonging to in mt7530_port_set_vlan_unaware()
1303 * the CPU port get out of VLAN filtering mode. in mt7530_port_set_vlan_unaware()
1306 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_set_vlan_unaware()
1307 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_set_vlan_unaware()
1309 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), in mt7530_port_set_vlan_unaware()
1310 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1311 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG in mt7530_port_set_vlan_unaware()
1317 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) in mt7530_port_set_vlan_aware() argument
1319 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1324 if (dsa_is_user_port(ds, port)) { in mt7530_port_set_vlan_aware()
1325 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_set_vlan_aware()
1327 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_set_vlan_aware()
1328 G0_PORT_VID(priv->ports[port].pvid)); in mt7530_port_set_vlan_aware()
1331 if (!priv->ports[port].pvid) in mt7530_port_set_vlan_aware()
1332 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_set_vlan_aware()
1335 /* Set the port as a user port which is to be able to recognize in mt7530_port_set_vlan_aware()
1339 mt7530_rmw(priv, MT7530_PVC_P(port), in mt7530_port_set_vlan_aware()
1344 /* Also set CPU ports to the "user" VLAN port attribute, to in mt7530_port_set_vlan_aware()
1351 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, in mt7530_port_set_vlan_aware()
1357 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, in mt7530_port_bridge_leave() argument
1360 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; in mt7530_port_bridge_leave()
1361 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_bridge_leave()
1362 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1364 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1367 int other_port = other_dp->index; in mt7530_port_bridge_leave()
1372 /* Remove this port from the port matrix of the other ports in mt7530_port_bridge_leave()
1373 * in the same bridge. If the port is disabled, port matrix in mt7530_port_bridge_leave()
1374 * is kept and not being setup until the port becomes enabled. in mt7530_port_bridge_leave()
1379 if (priv->ports[other_port].enable) in mt7530_port_bridge_leave()
1381 PCR_MATRIX(BIT(port))); in mt7530_port_bridge_leave()
1382 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); in mt7530_port_bridge_leave()
1385 /* Set the cpu port to be the only one in the port matrix of in mt7530_port_bridge_leave()
1386 * this port. in mt7530_port_bridge_leave()
1388 if (priv->ports[port].enable) in mt7530_port_bridge_leave()
1389 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, in mt7530_port_bridge_leave()
1390 PCR_MATRIX(BIT(cpu_dp->index))); in mt7530_port_bridge_leave()
1391 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_bridge_leave()
1393 /* When a port is removed from the bridge, the port would be set up in mt7530_port_bridge_leave()
1394 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_bridge_leave()
1395 * port. in mt7530_port_bridge_leave()
1397 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, in mt7530_port_bridge_leave()
1400 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1404 mt7530_port_fdb_add(struct dsa_switch *ds, int port, in mt7530_port_fdb_add() argument
1408 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1410 u8 port_mask = BIT(port); in mt7530_port_fdb_add()
1412 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1413 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1415 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1421 mt7530_port_fdb_del(struct dsa_switch *ds, int port, in mt7530_port_fdb_del() argument
1425 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1427 u8 port_mask = BIT(port); in mt7530_port_fdb_del()
1429 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1430 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1432 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1438 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, in mt7530_port_fdb_dump() argument
1441 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1447 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1456 if (_fdb.port_mask & BIT(port)) { in mt7530_port_fdb_dump()
1463 } while (--cnt && in mt7530_port_fdb_dump()
1467 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1473 mt7530_port_mdb_add(struct dsa_switch *ds, int port, in mt7530_port_mdb_add() argument
1477 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_add()
1478 const u8 *addr = mdb->addr; in mt7530_port_mdb_add()
1479 u16 vid = mdb->vid; in mt7530_port_mdb_add()
1483 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_add()
1490 port_mask |= BIT(port); in mt7530_port_mdb_add()
1491 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_mdb_add()
1494 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_add()
1500 mt7530_port_mdb_del(struct dsa_switch *ds, int port, in mt7530_port_mdb_del() argument
1504 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_del()
1505 const u8 *addr = mdb->addr; in mt7530_port_mdb_del()
1506 u16 vid = mdb->vid; in mt7530_port_mdb_del()
1510 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_del()
1517 port_mask &= ~BIT(port); in mt7530_port_mdb_del()
1518 mt7530_fdb_write(priv, vid, port_mask, addr, -1, in mt7530_port_mdb_del()
1522 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_del()
1541 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1547 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1548 return -EINVAL; in mt7530_vlan_cmd()
1555 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, in mt7530_port_vlan_filtering() argument
1558 struct dsa_port *dp = dsa_to_port(ds, port); in mt7530_port_vlan_filtering()
1559 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_vlan_filtering()
1562 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1564 * port and the corresponding CPU port is required the setup in mt7530_port_vlan_filtering()
1565 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1567 mt7530_port_set_vlan_aware(ds, port); in mt7530_port_vlan_filtering()
1568 mt7530_port_set_vlan_aware(ds, cpu_dp->index); in mt7530_port_vlan_filtering()
1570 mt7530_port_set_vlan_unaware(ds, port); in mt7530_port_vlan_filtering()
1580 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); in mt7530_hw_vlan_add()
1584 new_members = entry->old_members | BIT(entry->port); in mt7530_hw_vlan_add()
1587 * VLAN and joining the port as one of the port members. in mt7530_hw_vlan_add()
1594 * port inside the VLAN. in mt7530_hw_vlan_add()
1595 * CPU port is always taken as a tagged port for serving more than one in mt7530_hw_vlan_add()
1598 * DSA tag. in mt7530_hw_vlan_add()
1602 else if (entry->untagged) in mt7530_hw_vlan_add()
1607 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1608 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1618 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1622 dev_err(priv->dev, in mt7530_hw_vlan_del()
1649 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1674 mt7530_port_vlan_add(struct dsa_switch *ds, int port, in mt7530_port_vlan_add() argument
1678 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1679 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1681 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1683 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1685 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); in mt7530_port_vlan_add()
1686 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); in mt7530_port_vlan_add()
1689 priv->ports[port].pvid = vlan->vid; in mt7530_port_vlan_add()
1692 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_add()
1696 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_add()
1697 mt7530_rmw(priv, MT7530_PPBV1_P(port), in mt7530_port_vlan_add()
1699 G0_PORT_VID(vlan->vid)); in mt7530_port_vlan_add()
1700 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_add()
1702 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_add()
1704 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_add()
1705 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_add()
1706 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_add()
1709 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_vlan_add()
1713 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1719 mt7530_port_vlan_del(struct dsa_switch *ds, int port, in mt7530_port_vlan_del() argument
1723 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1725 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1727 mt7530_hw_vlan_entry_init(&target_entry, port, 0); in mt7530_port_vlan_del()
1728 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, in mt7530_port_vlan_del()
1731 /* PVID is being restored to the default whenever the PVID port in mt7530_port_vlan_del()
1734 if (priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_del()
1735 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_del()
1737 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_del()
1738 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) in mt7530_port_vlan_del()
1739 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, in mt7530_port_vlan_del()
1742 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, in mt7530_port_vlan_del()
1747 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
1764 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, in mt753x_port_mirror_add() argument
1768 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
1773 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
1774 return -EEXIST; in mt753x_port_mirror_add()
1776 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
1778 /* MT7530 only supports one monitor port */ in mt753x_port_mirror_add()
1779 monitor_port = mt753x_mirror_port_get(priv->id, val); in mt753x_port_mirror_add()
1780 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
1781 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
1782 return -EEXIST; in mt753x_port_mirror_add()
1784 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
1785 val &= ~MT753X_MIRROR_MASK(priv->id); in mt753x_port_mirror_add()
1786 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
1787 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1789 val = mt7530_read(priv, MT7530_PCR_P(port)); in mt753x_port_mirror_add()
1792 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
1795 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
1797 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_add()
1802 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, in mt753x_port_mirror_del() argument
1805 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
1808 val = mt7530_read(priv, MT7530_PCR_P(port)); in mt753x_port_mirror_del()
1809 if (mirror->ingress) { in mt753x_port_mirror_del()
1811 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
1814 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
1816 mt7530_write(priv, MT7530_PCR_P(port), val); in mt753x_port_mirror_del()
1818 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
1819 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
1820 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
1821 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
1826 mtk_get_tag_protocol(struct dsa_switch *ds, int port, in mtk_get_tag_protocol() argument
1837 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 in mt7530_gpio_to_bit()
1838 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 in mt7530_gpio_to_bit()
1839 * [10: 8] port 2 LED 0..2 as GPIO 6..8 in mt7530_gpio_to_bit()
1840 * [14:12] port 3 LED 0..2 as GPIO 9..11 in mt7530_gpio_to_bit()
1841 * [18:16] port 4 LED 0..2 as GPIO 12..14 in mt7530_gpio_to_bit()
1910 struct device *dev = priv->dev; in mt7530_setup_gpio()
1915 return -ENOMEM; in mt7530_setup_gpio()
1921 gc->label = "mt7530"; in mt7530_setup_gpio()
1922 gc->parent = dev; in mt7530_setup_gpio()
1923 gc->owner = THIS_MODULE; in mt7530_setup_gpio()
1924 gc->get_direction = mt7530_gpio_get_direction; in mt7530_setup_gpio()
1925 gc->direction_input = mt7530_gpio_direction_input; in mt7530_setup_gpio()
1926 gc->direction_output = mt7530_gpio_direction_output; in mt7530_setup_gpio()
1927 gc->get = mt7530_gpio_get; in mt7530_setup_gpio()
1928 gc->set = mt7530_gpio_set; in mt7530_setup_gpio()
1929 gc->base = -1; in mt7530_setup_gpio()
1930 gc->ngpio = 15; in mt7530_setup_gpio()
1931 gc->can_sleep = true; in mt7530_setup_gpio()
1954 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_irq_thread_fn()
1968 priv->irq_enable &= ~BIT(d->hwirq); in mt7530_irq_mask()
1976 priv->irq_enable |= BIT(d->hwirq); in mt7530_irq_unmask()
1992 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7530_irq_bus_sync_unlock()
2008 irq_set_chip_data(irq, domain->host_data); in mt7530_irq_map()
2026 priv->irq_enable &= ~BIT(d->hwirq); in mt7988_irq_mask()
2027 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7988_irq_mask()
2035 priv->irq_enable |= BIT(d->hwirq); in mt7988_irq_unmask()
2036 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7988_irq_unmask()
2049 irq_set_chip_data(irq, domain->host_data); in mt7988_irq_map()
2065 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio_irq()
2069 if (BIT(p) & ds->phys_mii_mask) { in mt7530_setup_mdio_irq()
2072 irq = irq_create_mapping(priv->irq_domain, p); in mt7530_setup_mdio_irq()
2073 ds->slave_mii_bus->irq[p] = irq; in mt7530_setup_mdio_irq()
2081 struct device *dev = priv->dev; in mt7530_setup_irq()
2082 struct device_node *np = dev->of_node; in mt7530_setup_irq()
2085 if (!of_property_read_bool(np, "interrupt-controller")) { in mt7530_setup_irq()
2090 priv->irq = of_irq_get(np, 0); in mt7530_setup_irq()
2091 if (priv->irq <= 0) { in mt7530_setup_irq()
2092 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); in mt7530_setup_irq()
2093 return priv->irq ? : -EINVAL; in mt7530_setup_irq()
2096 if (priv->id == ID_MT7988) in mt7530_setup_irq()
2097 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
2101 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
2105 if (!priv->irq_domain) { in mt7530_setup_irq()
2107 return -ENOMEM; in mt7530_setup_irq()
2110 /* This register must be set for MT7530 to properly fire interrupts */ in mt7530_setup_irq()
2111 if (priv->id != ID_MT7531) in mt7530_setup_irq()
2114 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, in mt7530_setup_irq()
2117 irq_domain_remove(priv->irq_domain); in mt7530_setup_irq()
2131 if (BIT(p) & priv->ds->phys_mii_mask) { in mt7530_free_mdio_irq()
2134 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_free_mdio_irq()
2143 free_irq(priv->irq, priv); in mt7530_free_irq_common()
2144 irq_domain_remove(priv->irq_domain); in mt7530_free_irq_common()
2157 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio()
2158 struct device *dev = priv->dev; in mt7530_setup_mdio()
2165 return -ENOMEM; in mt7530_setup_mdio()
2167 ds->slave_mii_bus = bus; in mt7530_setup_mdio()
2168 bus->priv = priv; in mt7530_setup_mdio()
2169 bus->name = KBUILD_MODNAME "-mii"; in mt7530_setup_mdio()
2170 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); in mt7530_setup_mdio()
2171 bus->read = mt753x_phy_read_c22; in mt7530_setup_mdio()
2172 bus->write = mt753x_phy_write_c22; in mt7530_setup_mdio()
2173 bus->read_c45 = mt753x_phy_read_c45; in mt7530_setup_mdio()
2174 bus->write_c45 = mt753x_phy_write_c45; in mt7530_setup_mdio()
2175 bus->parent = dev; in mt7530_setup_mdio()
2176 bus->phy_mask = ~ds->phys_mii_mask; in mt7530_setup_mdio()
2178 if (priv->irq) in mt7530_setup_mdio()
2184 if (priv->irq) in mt7530_setup_mdio()
2194 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
2209 dn = cpu_dp->master->dev.of_node->parent; in mt7530_setup()
2210 /* It doesn't matter which CPU port is found first, in mt7530_setup()
2217 dev_err(ds->dev, "parent OF node of DSA master not found"); in mt7530_setup()
2218 return -EINVAL; in mt7530_setup()
2221 ds->assisted_learning_on_cpu_port = true; in mt7530_setup()
2222 ds->mtu_enforcement_ingress = true; in mt7530_setup()
2224 if (priv->id == ID_MT7530) { in mt7530_setup()
2225 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
2226 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
2228 dev_err(priv->dev, in mt7530_setup()
2233 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
2234 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
2236 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
2242 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
2245 if (priv->mcm) { in mt7530_setup()
2246 reset_control_assert(priv->rstc); in mt7530_setup()
2248 reset_control_deassert(priv->rstc); in mt7530_setup()
2250 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
2252 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
2255 /* Waiting for MT7530 got to stable */ in mt7530_setup()
2260 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
2267 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
2268 return -ENODEV; in mt7530_setup()
2287 /* Enable port 6 */ in mt7530_setup()
2293 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7530_setup()
2324 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7530_setup()
2329 /* Setup port 5 */ in mt7530_setup()
2330 priv->p5_intf_sel = P5_DISABLED; in mt7530_setup()
2334 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7530_setup()
2335 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); in mt7530_setup()
2336 if (ret && ret != -ENODEV) in mt7530_setup()
2342 "mediatek,eth-mac")) in mt7530_setup()
2349 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
2353 if (phy_node->parent == priv->dev->of_node->parent) { in mt7530_setup()
2355 if (ret && ret != -ENODEV) { in mt7530_setup()
2360 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
2362 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; in mt7530_setup()
2364 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; in mt7530_setup()
2373 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { in mt7530_setup()
2393 struct mt7530_priv *priv = ds->priv; in mt7531_setup_common()
2443 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
2448 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
2451 if (priv->mcm) { in mt7531_setup()
2452 reset_control_assert(priv->rstc); in mt7531_setup()
2454 reset_control_deassert(priv->rstc); in mt7531_setup()
2456 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
2458 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
2461 /* Waiting for MT7530 got to stable */ in mt7531_setup()
2466 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
2474 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
2475 return -ENODEV; in mt7531_setup()
2478 /* all MACs must be forced link-down before sw reset */ in mt7531_setup()
2490 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; in mt7531_setup()
2492 /* Let ds->slave_mii_bus be able to access external phy. */ in mt7531_setup()
2498 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7531_setup()
2500 dev_dbg(ds->dev, "P5 support %s interface\n", in mt7531_setup()
2501 p5_intf_modes(priv->p5_intf_sel)); in mt7531_setup()
2507 priv->p5_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
2508 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
2524 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7531_setup()
2529 ds->assisted_learning_on_cpu_port = true; in mt7531_setup()
2530 ds->mtu_enforcement_ingress = true; in mt7531_setup()
2535 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7530_mac_port_get_caps() argument
2538 switch (port) { in mt7530_mac_port_get_caps()
2541 config->supported_interfaces); in mt7530_mac_port_get_caps()
2544 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ in mt7530_mac_port_get_caps()
2545 phy_interface_set_rgmii(config->supported_interfaces); in mt7530_mac_port_get_caps()
2547 config->supported_interfaces); in mt7530_mac_port_get_caps()
2549 config->supported_interfaces); in mt7530_mac_port_get_caps()
2552 case 6: /* 1st cpu port */ in mt7530_mac_port_get_caps()
2554 config->supported_interfaces); in mt7530_mac_port_get_caps()
2556 config->supported_interfaces); in mt7530_mac_port_get_caps()
2561 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) in mt7531_is_rgmii_port() argument
2563 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); in mt7531_is_rgmii_port()
2566 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7531_mac_port_get_caps() argument
2569 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_get_caps()
2571 switch (port) { in mt7531_mac_port_get_caps()
2574 config->supported_interfaces); in mt7531_mac_port_get_caps()
2577 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ in mt7531_mac_port_get_caps()
2578 if (mt7531_is_rgmii_port(priv, port)) { in mt7531_mac_port_get_caps()
2579 phy_interface_set_rgmii(config->supported_interfaces); in mt7531_mac_port_get_caps()
2584 case 6: /* 1st cpu port supports sgmii/8023z only */ in mt7531_mac_port_get_caps()
2586 config->supported_interfaces); in mt7531_mac_port_get_caps()
2588 config->supported_interfaces); in mt7531_mac_port_get_caps()
2590 config->supported_interfaces); in mt7531_mac_port_get_caps()
2592 config->mac_capabilities |= MAC_2500FD; in mt7531_mac_port_get_caps()
2597 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, in mt7988_mac_port_get_caps() argument
2600 phy_interface_zero(config->supported_interfaces); in mt7988_mac_port_get_caps()
2602 switch (port) { in mt7988_mac_port_get_caps()
2605 config->supported_interfaces); in mt7988_mac_port_get_caps()
2610 config->supported_interfaces); in mt7988_mac_port_get_caps()
2611 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in mt7988_mac_port_get_caps()
2619 struct mt7530_priv *priv = ds->priv; in mt753x_pad_setup()
2621 return priv->info->pad_setup(ds, state->interface); in mt753x_pad_setup()
2625 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7530_mac_config() argument
2628 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
2631 if (port != 5) in mt7530_mac_config()
2634 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
2639 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, in mt7531_rgmii_setup() argument
2645 if (!mt7531_is_rgmii_port(priv, port)) { in mt7531_rgmii_setup()
2646 dev_err(priv->dev, "RGMII mode is not available for port %d\n", in mt7531_rgmii_setup()
2647 port); in mt7531_rgmii_setup()
2648 return -EINVAL; in mt7531_rgmii_setup()
2678 return -EINVAL; in mt7531_rgmii_setup()
2686 static bool mt753x_is_mac_port(u32 port) in mt753x_is_mac_port() argument
2688 return (port == 5 || port == 6); in mt753x_is_mac_port()
2692 mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7988_mac_config() argument
2695 if (dsa_is_cpu_port(ds, port) && in mt7988_mac_config()
2699 return -EINVAL; in mt7988_mac_config()
2703 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt7531_mac_config() argument
2706 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2710 if (!mt753x_is_mac_port(port)) { in mt7531_mac_config()
2711 dev_err(priv->dev, "port %d is not a MAC port\n", port); in mt7531_mac_config()
2712 return -EINVAL; in mt7531_mac_config()
2720 dp = dsa_to_port(ds, port); in mt7531_mac_config()
2721 phydev = dp->slave->phydev; in mt7531_mac_config()
2722 return mt7531_rgmii_setup(priv, port, interface, phydev); in mt7531_mac_config()
2730 return -EINVAL; in mt7531_mac_config()
2733 return -EINVAL; in mt7531_mac_config()
2737 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt753x_mac_config() argument
2740 struct mt7530_priv *priv = ds->priv; in mt753x_mac_config()
2742 return priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_mac_config()
2746 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, in mt753x_phylink_mac_select_pcs() argument
2749 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_select_pcs()
2753 return &priv->pcs[port].pcs; in mt753x_phylink_mac_select_pcs()
2757 return priv->ports[port].sgmii_pcs; in mt753x_phylink_mac_select_pcs()
2764 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, in mt753x_phylink_mac_config() argument
2767 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_config()
2770 switch (port) { in mt753x_phylink_mac_config()
2772 if (state->interface != PHY_INTERFACE_MODE_GMII && in mt753x_phylink_mac_config()
2773 state->interface != PHY_INTERFACE_MODE_INTERNAL) in mt753x_phylink_mac_config()
2776 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ in mt753x_phylink_mac_config()
2777 if (priv->p5_interface == state->interface) in mt753x_phylink_mac_config()
2780 if (mt753x_mac_config(ds, port, mode, state) < 0) in mt753x_phylink_mac_config()
2783 if (priv->p5_intf_sel != P5_DISABLED) in mt753x_phylink_mac_config()
2784 priv->p5_interface = state->interface; in mt753x_phylink_mac_config()
2786 case 6: /* 1st cpu port */ in mt753x_phylink_mac_config()
2787 if (priv->p6_interface == state->interface) in mt753x_phylink_mac_config()
2792 if (mt753x_mac_config(ds, port, mode, state) < 0) in mt753x_phylink_mac_config()
2795 priv->p6_interface = state->interface; in mt753x_phylink_mac_config()
2799 dev_err(ds->dev, "%s: unsupported %s port: %i\n", in mt753x_phylink_mac_config()
2800 __func__, phy_modes(state->interface), port); in mt753x_phylink_mac_config()
2804 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); in mt753x_phylink_mac_config()
2808 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); in mt753x_phylink_mac_config()
2811 if (port == 5 && dsa_is_user_port(ds, 5)) in mt753x_phylink_mac_config()
2815 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); in mt753x_phylink_mac_config()
2818 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, in mt753x_phylink_mac_link_down() argument
2822 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_down()
2824 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); in mt753x_phylink_mac_link_down()
2832 if (pcs->ops->pcs_link_up) in mt753x_phylink_pcs_link_up()
2833 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); in mt753x_phylink_pcs_link_up()
2836 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, in mt753x_phylink_mac_link_up() argument
2843 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_up()
2848 /* MT753x MAC works in 1G full duplex mode for all up-clocked in mt753x_phylink_mac_link_up()
2884 mt7530_set(priv, MT7530_PMCR_P(port), mcr); in mt753x_phylink_mac_link_up()
2888 mt7531_cpu_port_config(struct dsa_switch *ds, int port) in mt7531_cpu_port_config() argument
2890 struct mt7530_priv *priv = ds->priv; in mt7531_cpu_port_config()
2895 switch (port) { in mt7531_cpu_port_config()
2897 if (mt7531_is_rgmii_port(priv, port)) in mt7531_cpu_port_config()
2902 priv->p5_interface = interface; in mt7531_cpu_port_config()
2907 priv->p6_interface = interface; in mt7531_cpu_port_config()
2910 return -EINVAL; in mt7531_cpu_port_config()
2918 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); in mt7531_cpu_port_config()
2921 mt7530_write(priv, MT7530_PMCR_P(port), in mt7531_cpu_port_config()
2922 PMCR_CPU_PORT_SETTING(priv->id)); in mt7531_cpu_port_config()
2923 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, in mt7531_cpu_port_config()
2925 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, in mt7531_cpu_port_config()
2932 mt7988_cpu_port_config(struct dsa_switch *ds, int port) in mt7988_cpu_port_config() argument
2934 struct mt7530_priv *priv = ds->priv; in mt7988_cpu_port_config()
2936 mt7530_write(priv, MT7530_PMCR_P(port), in mt7988_cpu_port_config()
2937 PMCR_CPU_PORT_SETTING(priv->id)); in mt7988_cpu_port_config()
2939 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, in mt7988_cpu_port_config()
2946 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, in mt753x_phylink_get_caps() argument
2949 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_get_caps()
2951 /* This switch only supports full-duplex at 1Gbps */ in mt753x_phylink_get_caps()
2952 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in mt753x_phylink_get_caps()
2955 priv->info->mac_port_get_caps(ds, port, config); in mt753x_phylink_get_caps()
2963 if (state->interface == PHY_INTERFACE_MODE_TRGMII || in mt753x_pcs_validate()
2964 phy_interface_mode_is_8023z(state->interface)) in mt753x_pcs_validate()
2973 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; in mt7530_pcs_get_state()
2974 int port = pcs_to_mt753x_pcs(pcs)->port; in mt7530_pcs_get_state() local
2977 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); in mt7530_pcs_get_state()
2979 state->link = (pmsr & PMSR_LINK); in mt7530_pcs_get_state()
2980 state->an_complete = state->link; in mt7530_pcs_get_state()
2981 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_pcs_get_state()
2985 state->speed = SPEED_10; in mt7530_pcs_get_state()
2988 state->speed = SPEED_100; in mt7530_pcs_get_state()
2991 state->speed = SPEED_1000; in mt7530_pcs_get_state()
2994 state->speed = SPEED_UNKNOWN; in mt7530_pcs_get_state()
2998 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_pcs_get_state()
3000 state->pause |= MLO_PAUSE_RX; in mt7530_pcs_get_state()
3002 state->pause |= MLO_PAUSE_TX; in mt7530_pcs_get_state()
3027 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
3031 for (i = 0; i < priv->ds->num_ports; i++) { in mt753x_setup()
3032 priv->pcs[i].pcs.ops = priv->info->pcs_ops; in mt753x_setup()
3033 priv->pcs[i].pcs.neg_mode = true; in mt753x_setup()
3034 priv->pcs[i].priv = priv; in mt753x_setup()
3035 priv->pcs[i].port = i; in mt753x_setup()
3038 ret = priv->info->sw_setup(ds); in mt753x_setup()
3047 if (ret && priv->irq) in mt753x_setup()
3050 if (priv->create_sgmii) { in mt753x_setup()
3051 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); in mt753x_setup()
3052 if (ret && priv->irq) in mt753x_setup()
3059 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, in mt753x_get_mac_eee() argument
3062 struct mt7530_priv *priv = ds->priv; in mt753x_get_mac_eee()
3063 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); in mt753x_get_mac_eee()
3065 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); in mt753x_get_mac_eee()
3066 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); in mt753x_get_mac_eee()
3071 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, in mt753x_set_mac_eee() argument
3074 struct mt7530_priv *priv = ds->priv; in mt753x_set_mac_eee()
3077 if (e->tx_lpi_timer > 0xFFF) in mt753x_set_mac_eee()
3078 return -EINVAL; in mt753x_set_mac_eee()
3080 set = SET_LPI_THRESH(e->tx_lpi_timer); in mt753x_set_mac_eee()
3081 if (!e->tx_lpi_enabled) in mt753x_set_mac_eee()
3084 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); in mt753x_set_mac_eee()
3096 struct mt7530_priv *priv = ds->priv; in mt7988_setup()
3099 reset_control_assert(priv->rstc); in mt7988_setup()
3101 reset_control_deassert(priv->rstc); in mt7988_setup()
3204 struct device *dev = priv->dev; in mt7530_probe_common()
3206 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe_common()
3207 if (!priv->ds) in mt7530_probe_common()
3208 return -ENOMEM; in mt7530_probe_common()
3210 priv->ds->dev = dev; in mt7530_probe_common()
3211 priv->ds->num_ports = MT7530_NUM_PORTS; in mt7530_probe_common()
3216 priv->info = of_device_get_match_data(dev); in mt7530_probe_common()
3217 if (!priv->info) in mt7530_probe_common()
3218 return -EINVAL; in mt7530_probe_common()
3223 if (!priv->info->sw_setup || !priv->info->pad_setup || in mt7530_probe_common()
3224 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || in mt7530_probe_common()
3225 !priv->info->mac_port_get_caps || in mt7530_probe_common()
3226 !priv->info->mac_port_config) in mt7530_probe_common()
3227 return -EINVAL; in mt7530_probe_common()
3229 priv->id = priv->info->id; in mt7530_probe_common()
3230 priv->dev = dev; in mt7530_probe_common()
3231 priv->ds->priv = priv; in mt7530_probe_common()
3232 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe_common()
3233 mutex_init(&priv->reg_mutex); in mt7530_probe_common()
3243 if (priv->irq) in mt7530_remove_common()
3246 dsa_unregister_switch(priv->ds); in mt7530_remove_common()
3248 mutex_destroy(&priv->reg_mutex); in mt7530_remove_common()
3253 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");