Lines Matching +full:0 +full:x40e
12 #define MT7530_ALL_MEMBERS 0xff
18 ID_MT7530 = 0,
26 #define TRGMII_BASE(x) (0x10000 + (x))
29 #define ETHSYS_CLKCFG0 0x2c
32 #define SYSC_REG_RSTCTRL 0x34
36 #define MT7530_MFC 0x10
37 #define BC_FFP(x) (((x) & 0xff) << 24)
38 #define BC_FFP_MASK BC_FFP(~0)
39 #define UNM_FFP(x) (((x) & 0xff) << 16)
40 #define UNM_FFP_MASK UNM_FFP(~0)
41 #define UNU_FFP(x) (((x) & 0xff) << 8)
42 #define UNU_FFP_MASK UNU_FFP(~0)
45 #define CPU_MASK (0xf << 4)
47 #define MIRROR_PORT(x) ((x) & 0x7)
48 #define MIRROR_MASK 0x7
51 #define MT7531_CFC 0x4
56 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
67 #define MT753X_BPC 0x24
68 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
72 /* Register for :03 and :0E MAC DA frame control */
73 #define MT753X_RGAC2 0x2c
86 #define MT7530_ATA1 0x74
87 #define STATIC_EMP 0
89 #define MT7530_ATA2 0x78
91 #define ATA2_FID(x) (((x) & 0x7) << 12)
94 #define MT7530_ATWD 0x7c
97 #define MT7530_ATC 0x80
98 #define ATC_HASH (((x) & 0xfff) << 16)
103 #define ATC_MAT(x) (((x) & 0xf) << 8)
104 #define ATC_MAT_MACTAB ATC_MAT(0)
107 MT7530_FDB_READ = 0,
115 #define MT7530_TSRA1 0x84
119 #define MAC_BYTE_3 0
120 #define MAC_BYTE_MASK 0xff
122 #define MT7530_TSRA2 0x88
125 #define CVID 0
126 #define CVID_MASK 0xfff
128 #define MT7530_ATRD 0x8C
130 #define AGE_TIMER_MASK 0xff
132 #define PORT_MAP_MASK 0xff
134 #define ENT_STATUS_MASK 0x3
137 #define MT7530_VTCR 0x90
140 #define VTCR_FUNC(x) (((x) & 0xf) << 12)
141 #define VTCR_VID ((x) & 0xfff)
147 MT7530_VTCR_RD_VID = 0,
152 #define MT7530_VAWD1 0x94
161 #define PORT_MEM(x) (((x) & 0xff) << 16)
163 #define FID(x) (((x) & 0x7) << 1)
165 #define VLAN_VALID BIT(0)
167 #define PORT_MEM_MASK 0xff
170 FID_STANDALONE = 0,
174 #define MT7530_VAWD2 0x98
176 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
180 MT7530_VLAN_EGRESS_UNTAG = 0,
186 #define MT7530_AAC 0xa0
191 #define AGE_CNT_MAX 0xff
194 #define AGE_UNIT_MASK GENMASK(11, 0)
195 #define AGE_UNIT_MAX 0xfff
199 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
200 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
201 #define FID_PST_MASK(fid) FID_PST(fid, 0x3)
204 MT7530_STP_DISABLED = 0,
212 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
215 #define PORT_VLAN(x) ((x) & 0x3)
219 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
233 #define PCR_MATRIX(x) (((x) & 0xff) << 16)
234 #define PORT_PRI(x) (((x) & 0x7) << 24)
235 #define EG_TAG(x) (((x) & 0x3) << 28)
236 #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
237 #define PCR_MATRIX_CLR PCR_MATRIX(0)
241 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
245 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
247 #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
249 #define VLAN_ATTR(x) (((x) & 0x3) << 6)
251 #define ACC_FRM_MASK GENMASK(1, 0)
254 MT7530_VLAN_EG_DISABLED = 0,
259 MT7530_VLAN_USER = 0,
264 MT7530_VLAN_ACC_ALL = 0,
269 #define STAG_VPID (((x) & 0xffff) << 16)
272 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
273 #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
274 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
275 #define G0_PORT_VID_DEF G0_PORT_VID(0)
278 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
279 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
294 #define PMCR_FORCE_LNK BIT(0)
322 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100)
323 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24)
324 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16)
329 #define LPI_MODE_EN BIT(0)
331 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
338 #define PMSR_SPEED_10 0x00
341 #define PMSR_LINK BIT(0)
344 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
347 #define MT7530_GMACCR 0x30e0
350 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
351 #define MAX_RX_PKT_LEN_1522 0x0
352 #define MAX_RX_PKT_LEN_1536 0x1
353 #define MAX_RX_PKT_LEN_1552 0x2
354 #define MAX_RX_PKT_LEN_JUMBO 0x3
357 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
358 #define MT7530_MIB_CCR 0x4fe0
375 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
376 #define MT7531_PHYA_CTRL_SIGNAL3 0x128
379 #define MT7530_SYS_CTRL 0x7000
382 #define SYS_CTRL_REG_RST BIT(0)
385 #define MT7530_SYS_INT_EN 0x7008
388 #define MT7530_SYS_INT_STS 0x700c
391 #define MT7531_PHY_IAC 0x701C
393 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
394 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
395 #define MT7531_MDIO_CMD_MASK (0x3 << 18)
396 #define MT7531_MDIO_ST_MASK (0x3 << 16)
397 #define MT7531_MDIO_RW_DATA_MASK (0xffff)
398 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
399 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
400 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
401 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
402 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
405 MT7531_MDIO_ADDR = 0,
413 MT7531_MDIO_ST_CL45 = 0,
429 #define MT7531_CLKGEN_CTRL 0x7500
430 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
432 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
436 #define GP_MODE(x) (((x) & 0x3) << 1)
438 #define GP_CLK_EN BIT(0)
441 MT7531_GP_MODE_RGMII = 0,
447 MT7531_CLK_SKEW_NO_CHG = 0,
454 #define MT7530_HWTRAP 0x7800
460 #define MT7531_HWTRAP 0x7800
463 #define HWTRAP_XTAL_FSEL_40MHZ 0
471 #define MT7530_MHWTRAP 0x7804
481 #define MT7530_TOP_SIG_CTRL 0x7808
484 #define MT7531_TOP_SIG_SR 0x780c
486 #define PAD_MCM_SMI_EN BIT(0)
488 #define MT7530_IO_DRV_CR 0x7810
489 #define P5_IO_CLK_DRV(x) ((x) & 0x3)
490 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
492 #define MT7531_CHIP_REV 0x781C
494 #define MT7531_PLLGP_EN 0x7820
497 #define SW_PLLGP BIT(0)
499 #define MT7530_P6ECR 0x7830
500 #define P6_INTF_MODE_MASK 0x3
501 #define P6_INTF_MODE(x) ((x) & 0x3)
503 #define MT7531_PLLGP_CR0 0x78a8
506 #define RG_COREPLL_POSDIV_M 0x3800000
508 #define RG_COREPLL_SDM_PCW_M 0x3ffffe
509 #define RG_COREPLL_SDM_PCW_CHG BIT(0)
512 #define MT7531_ANA_PLLGP_CR2 0x78b0
513 #define MT7531_ANA_PLLGP_CR5 0x78bc
516 #define MT7530_TRGMII_RCK_CTRL 0x7a00
519 #define DQSI1_TAP_MASK (0x7f << 8)
520 #define DQSI0_TAP_MASK 0x7f
521 #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
522 #define DQSI0_TAP(x) ((x) & 0x7f)
524 #define MT7530_TRGMII_RCK_RTT 0x7a04
528 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
531 #define RD_TAP_MASK 0x7f
532 #define RD_TAP(x) ((x) & 0x7f)
534 #define MT7530_TRGMII_TXCTRL 0x7a40
539 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
540 #define TD_DM_DRVP(x) ((x) & 0xf)
541 #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
543 #define MT7530_TRGMII_TCK_CTRL 0x7a78
544 #define TCK_TAP(x) (((x) & 0xf) << 8)
546 #define MT7530_P5RGMIIRXCR 0x7b00
548 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
550 #define MT7530_P5RGMIITXCR 0x7b04
551 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
554 #define MT7531_GPIO_MODE0 0x7c0c
555 #define MT7531_GPIO0_MASK GENMASK(3, 0)
558 #define MT7531_GPIO_MODE1 0x7c10
566 * [ 2: 0] port 0
573 /* LED enable, 0: Disable, 1: Enable (Default) */
574 #define MT7530_LED_EN 0x7d00
575 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
576 #define MT7530_LED_IO_MODE 0x7d04
577 /* GPIO direction, 0: Input, 1: Output */
578 #define MT7530_LED_GPIO_DIR 0x7d10
579 /* GPIO output enable, 0: Disable, 1: Enable */
580 #define MT7530_LED_GPIO_OE 0x7d14
581 /* GPIO value, 0: Low, 1: High */
582 #define MT7530_LED_GPIO_DATA 0x7d18
584 #define MT7530_CREV 0x7ffc
586 #define MT7530_ID 0x7530
588 #define MT7531_CREV 0x781C
589 #define CHIP_REV_M 0x0f
590 #define MT7531_ID 0x7531
593 #define CORE_PLL_GROUP2 0x401
597 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
599 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
600 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
602 #define RT_SYSPLL_EN_AFE_OLT BIT(0)
604 #define CORE_PLL_GROUP4 0x403
611 #define MT753X_CTRL_PHY_ADDR 0
613 #define CORE_PLL_GROUP5 0x404
614 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
616 #define CORE_PLL_GROUP6 0x405
617 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
619 #define CORE_PLL_GROUP7 0x406
622 #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
625 #define CORE_PLL_GROUP10 0x409
626 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
628 #define CORE_PLL_GROUP11 0x40a
629 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
631 #define CORE_GSWPLL_GRP1 0x40d
632 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
633 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
638 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
640 #define CORE_GSWPLL_GRP2 0x40e
641 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
642 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
644 #define CORE_TRGMII_GSW_CLK_CG 0x410
645 #define REG_GSWCK_EN BIT(0)
686 P5_DISABLED = 0,