Lines Matching full:mgbe
11 "rx-pcs", "tx", "tx-pcs", "mac-divider", "mac", "mgbe", "ptp-ref", "mac"
57 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev); in tegra_mgbe_suspend() local
64 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_suspend()
66 return reset_control_assert(mgbe->rst_mac); in tegra_mgbe_suspend()
71 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(dev); in tegra_mgbe_resume() local
75 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
79 err = reset_control_deassert(mgbe->rst_mac); in tegra_mgbe_resume()
84 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); in tegra_mgbe_resume()
87 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); in tegra_mgbe_resume()
89 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_resume()
91 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
93 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_resume()
96 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, in tegra_mgbe_resume()
100 dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); in tegra_mgbe_resume()
101 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
107 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_resume()
114 struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data; in mgbe_uphy_lane_bringup_serdes_up() local
118 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
120 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
122 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
124 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
126 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
128 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
130 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
132 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
134 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
136 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
138 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL, value, in mgbe_uphy_lane_bringup_serdes_up()
142 dev_err(mgbe->dev, "timeout waiting for RX calibration to become enabled\n"); in mgbe_uphy_lane_bringup_serdes_up()
146 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
148 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
150 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
152 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
154 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
156 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
158 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
160 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_up()
162 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_IRQ_STATUS, value, in mgbe_uphy_lane_bringup_serdes_up()
166 dev_err(mgbe->dev, "timeout waiting for link to become ready\n"); in mgbe_uphy_lane_bringup_serdes_up()
171 writel(value, mgbe->xpcs + XPCS_WRAP_IRQ_STATUS); in mgbe_uphy_lane_bringup_serdes_up()
178 struct tegra_mgbe *mgbe = (struct tegra_mgbe *)mgbe_data; in mgbe_uphy_lane_bringup_serdes_down() local
181 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
183 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
185 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
187 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
189 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
191 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
193 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
195 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
197 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
199 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_RX_CONTROL); in mgbe_uphy_lane_bringup_serdes_down()
206 struct tegra_mgbe *mgbe; in tegra_mgbe_probe() local
210 mgbe = devm_kzalloc(&pdev->dev, sizeof(*mgbe), GFP_KERNEL); in tegra_mgbe_probe()
211 if (!mgbe) in tegra_mgbe_probe()
214 mgbe->dev = &pdev->dev; in tegra_mgbe_probe()
222 mgbe->hv = devm_platform_ioremap_resource_byname(pdev, "hypervisor"); in tegra_mgbe_probe()
223 if (IS_ERR(mgbe->hv)) in tegra_mgbe_probe()
224 return PTR_ERR(mgbe->hv); in tegra_mgbe_probe()
226 mgbe->regs = devm_platform_ioremap_resource_byname(pdev, "mac"); in tegra_mgbe_probe()
227 if (IS_ERR(mgbe->regs)) in tegra_mgbe_probe()
228 return PTR_ERR(mgbe->regs); in tegra_mgbe_probe()
230 mgbe->xpcs = devm_platform_ioremap_resource_byname(pdev, "xpcs"); in tegra_mgbe_probe()
231 if (IS_ERR(mgbe->xpcs)) in tegra_mgbe_probe()
232 return PTR_ERR(mgbe->xpcs); in tegra_mgbe_probe()
234 res.addr = mgbe->regs; in tegra_mgbe_probe()
237 mgbe->clks = devm_kcalloc(&pdev->dev, ARRAY_SIZE(mgbe_clks), in tegra_mgbe_probe()
238 sizeof(*mgbe->clks), GFP_KERNEL); in tegra_mgbe_probe()
239 if (!mgbe->clks) in tegra_mgbe_probe()
243 mgbe->clks[i].id = mgbe_clks[i]; in tegra_mgbe_probe()
245 err = devm_clk_bulk_get(mgbe->dev, ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_probe()
249 err = clk_bulk_prepare_enable(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_probe()
254 mgbe->rst_mac = devm_reset_control_get(&pdev->dev, "mac"); in tegra_mgbe_probe()
255 if (IS_ERR(mgbe->rst_mac)) { in tegra_mgbe_probe()
256 err = PTR_ERR(mgbe->rst_mac); in tegra_mgbe_probe()
260 err = reset_control_assert(mgbe->rst_mac); in tegra_mgbe_probe()
266 err = reset_control_deassert(mgbe->rst_mac); in tegra_mgbe_probe()
271 mgbe->rst_pcs = devm_reset_control_get(&pdev->dev, "pcs"); in tegra_mgbe_probe()
272 if (IS_ERR(mgbe->rst_pcs)) { in tegra_mgbe_probe()
273 err = PTR_ERR(mgbe->rst_pcs); in tegra_mgbe_probe()
277 err = reset_control_assert(mgbe->rst_pcs); in tegra_mgbe_probe()
283 err = reset_control_deassert(mgbe->rst_pcs); in tegra_mgbe_probe()
296 plat->bsp_priv = mgbe; in tegra_mgbe_probe()
312 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_STATUS); in tegra_mgbe_probe()
314 value = readl(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_probe()
316 writel(value, mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL); in tegra_mgbe_probe()
319 err = readl_poll_timeout(mgbe->xpcs + XPCS_WRAP_UPHY_HW_INIT_CTRL, value, in tegra_mgbe_probe()
323 dev_err(mgbe->dev, "timeout waiting for TX lane to become enabled\n"); in tegra_mgbe_probe()
336 writel(MAC_SBD_INTR, mgbe->regs + MGBE_WRAP_COMMON_INTR_ENABLE); in tegra_mgbe_probe()
339 writel(MGBE_SID, mgbe->hv + MGBE_WRAP_AXI_ASID0_CTRL); in tegra_mgbe_probe()
352 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_probe()
359 struct tegra_mgbe *mgbe = get_stmmac_bsp_priv(&pdev->dev); in tegra_mgbe_remove() local
361 clk_bulk_disable_unprepare(ARRAY_SIZE(mgbe_clks), mgbe->clks); in tegra_mgbe_remove()
367 { .compatible = "nvidia,tegra234-mgbe", },
378 .name = "tegra-mgbe",
386 MODULE_DESCRIPTION("NVIDIA Tegra MGBE driver");