Lines Matching +full:12 +full:bit
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
228 rtw_write8_set(rtwdev, REG_INIRTS_RATE_SEL, BIT(5)); in rtw8821c_mac_init()
258 rtw_write8_set(rtwdev, REG_WMAC_TRXPTCL_CTL_H, BIT(1)); in rtw8821c_mac_init()
272 ldo_pwr = enable ? ldo_pwr | BIT(7) : ldo_pwr & ~BIT(7); in rtw8821c_cfg_ldo25()
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
358 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); in rtw8821c_set_channel_rf()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
391 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
392 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
393 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
411 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
412 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
413 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
441 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
445 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
447 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); in rtw8821c_set_channel_bb()
455 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
464 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
472 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
473 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
481 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
482 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
580 else if (rxsc >= 9 && rxsc <= 12) in query_phy_status_page1()
703 cck_enable = rtw_read32(rtwdev, REG_RXPSEL) & BIT(28); in rtw8821c_false_alarm_statistics()
738 rtw_write32_set(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
739 rtw_write32_clr(rtwdev, REG_FAS, BIT(17)); in rtw8821c_false_alarm_statistics()
740 rtw_write32_clr(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
741 rtw_write32_set(rtwdev, REG_RXDESC, BIT(15)); in rtw8821c_false_alarm_statistics()
742 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
743 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
767 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); in rtw8821c_do_iqk()
946 case 12: /* 1-Ant, Aux, BTG */ in rtw8821c_coex_cfg_rfe_type()
1195 RTW_PWR_CMD_WRITE, BIT(0), 0},
1200 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1205 RTW_PWR_CMD_WRITE, BIT(0), 0},
1210 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1233 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1243 RTW_PWR_CMD_WRITE, BIT(5), 0},
1248 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1253 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1258 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)},
1263 RTW_PWR_CMD_WRITE, BIT(0), 0},
1268 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1273 RTW_PWR_CMD_WRITE, BIT(7), 0},
1278 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1283 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1288 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1293 RTW_PWR_CMD_POLLING, BIT(0), 0},
1298 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)},
1303 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1308 RTW_PWR_CMD_WRITE, BIT(1), 0},
1313 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)),
1314 (BIT(7) | BIT(6) | BIT(5))},
1319 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1324 RTW_PWR_CMD_WRITE, BIT(1), 0},
1337 RTW_PWR_CMD_WRITE, BIT(3), 0},
1347 RTW_PWR_CMD_WRITE, BIT(1), 0},
1352 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1357 RTW_PWR_CMD_WRITE, BIT(1), 0},
1362 RTW_PWR_CMD_WRITE, BIT(0), 0},
1367 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)},
1372 RTW_PWR_CMD_POLLING, BIT(1), 0},
1377 RTW_PWR_CMD_WRITE, BIT(3), 0},
1382 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)},
1400 RTW_PWR_CMD_WRITE, BIT(5), 0},
1405 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)},
1410 RTW_PWR_CMD_WRITE, BIT(0), 0},
1415 RTW_PWR_CMD_WRITE, BIT(5), 0},
1420 RTW_PWR_CMD_WRITE, BIT(4), 0},
1425 RTW_PWR_CMD_WRITE, BIT(0), 0},
1430 RTW_PWR_CMD_WRITE, BIT(1), 0},
1435 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)},
1440 RTW_PWR_CMD_WRITE, BIT(2), 0},
1445 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)},
1450 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)},
1455 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1460 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)},
1465 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1470 RTW_PWR_CMD_POLLING, BIT(1), 0},
1475 RTW_PWR_CMD_WRITE, BIT(1), 0},
1800 11, 11, 12, 12, 12, 12, 12},
1802 11, 12, 12, 12, 12, 12, 12, 12},
1804 11, 12, 12, 12, 12, 12, 12},
1809 12, 12, 12, 12, 12, 12, 12},
1811 12, 12, 12, 12, 12, 12, 12, 12},
1813 11, 12, 12, 12, 12, 12, 12, 12},
1818 11, 11, 12, 12, 12, 12, 12},
1820 11, 12, 12, 12, 12, 12, 12, 12},
1822 11, 12, 12, 12, 12, 12, 12},
1827 12, 12, 12, 12, 12, 12, 12},
1829 12, 12, 12, 12, 12, 12, 12, 12},
1831 11, 12, 12, 12, 12, 12, 12, 12},
1906 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1909 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1910 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1911 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1912 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1917 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1946 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK),