Lines Matching +full:0 +full:x1324
10 #define MDIO_PG0_G1 0
14 #define RAC_CTRL_PPR 0x00
15 #define RAC_ANA0A 0x0A
17 #define RAC_ANA0C 0x0C
19 #define RAC_ANA10 0x10
21 #define RAC_REG_REV2 0x1B
23 #define PCIE_DPHY_DLY_25US 0x1
24 #define RAC_ANA19 0x19
26 #define RAC_REG_FLD_0 0x1D
28 #define PCIE_AUTOK_4 0x3
29 #define RAC_ANA1F 0x1F
30 #define RAC_ANA24 0x24
32 #define RAC_ANA26 0x26
34 #define RAC_CTRL_PPR_V1 0x30
38 #define RAC_SET_PPR_V1 0x31
40 #define R_AX_DBI_FLAG 0x1090
45 #define R_AX_DBI_WDATA 0x1094
46 #define R_AX_DBI_RDATA 0x1098
48 #define R_AX_MDIO_WDATA 0x10A4
49 #define R_AX_MDIO_RDATA 0x10A6
51 #define R_AX_PCIE_PS_CTRL_V1 0x3008
56 #define B_AX_SEL_REQ_EXIT_L1 BIT(0)
58 #define R_AX_PCIE_MIX_CFG_V1 0x300C
66 #define B_AX_L1SUB_DISABLE BIT(0)
68 #define R_AX_L1_CLK_CTRL 0x3010
71 #define R_AX_PCIE_BG_CLR 0x303C
74 #define R_AX_PCIE_LAT_CTRL 0x3044
76 #define B_AX_CLK_REQ_SEL BIT(0)
78 #define R_AX_PCIE_IO_RCY_M1 0x3100
82 #define B_AX_PCIE_IO_RCY_TRIG_M1 BIT(0)
84 #define R_AX_PCIE_WDT_TIMER_M1 0x3104
85 #define B_AX_PCIE_WDT_TIMER_M1_MASK GENMASK(31, 0)
87 #define R_AX_PCIE_IO_RCY_M2 0x310C
91 #define B_AX_PCIE_IO_RCY_TRIG_M2 BIT(0)
93 #define R_AX_PCIE_WDT_TIMER_M2 0x3110
94 #define B_AX_PCIE_WDT_TIMER_M2_MASK GENMASK(31, 0)
96 #define R_AX_PCIE_IO_RCY_E0 0x3118
100 #define B_AX_PCIE_IO_RCY_TRIG_E0 BIT(0)
102 #define R_AX_PCIE_WDT_TIMER_E0 0x311C
103 #define B_AX_PCIE_WDT_TIMER_E0_MASK GENMASK(31, 0)
105 #define R_AX_PCIE_IO_RCY_S1 0x3124
112 #define B_AX_PCIE_IO_RCY_WTRIG_S1 BIT(0)
114 #define R_AX_PCIE_WDT_TIMER_S1 0x3128
115 #define B_AX_PCIE_WDT_TIMER_S1_MASK GENMASK(31, 0)
117 #define R_RAC_DIRECT_OFFSET_G1 0x3800
119 #define R_RAC_DIRECT_OFFSET_G2 0x3880
126 #define R_AX_HIMR0 0x01A0
129 #define R_AX_HISR0 0x01A4
131 #define R_AX_HIMR1 0x01A8
134 #define B_AX_GPIO16_INT_EN BIT(0)
136 #define R_AX_HISR1 0x01AC
139 #define B_AX_GPIO16_INT BIT(0)
141 #define R_AX_MDIO_CFG 0x10A0
145 #define B_AX_MDIO_ADDR_MASK GENMASK(4, 0)
147 #define R_AX_PCIE_HIMR00 0x10B0
148 #define R_AX_HAXI_HIMR00 0x10B0
175 #define B_AX_RXDMA_INT_EN BIT(0)
177 #define R_AX_PCIE_HISR00 0x10B4
178 #define R_AX_HAXI_HISR00 0x10B4
204 #define B_AX_RXDMA_INT BIT(0)
206 #define R_AX_HAXI_IDCT_MSK 0x10B8
210 #define B_AX_TXMDA_STUCK_IDCT_MSK BIT(0)
212 #define R_AX_HAXI_IDCT 0x10BC
216 #define B_AX_TXMDA_STUCK_IDCT BIT(0)
218 #define R_AX_HAXI_HIMR10 0x11E0
220 #define B_AX_TXDMA_CH10_INT_EN_V1 BIT(0)
222 #define R_AX_PCIE_HIMR10 0x13B0
227 #define R_AX_PCIE_HISR10 0x13B4
232 #define R_AX_PCIE_HIMR00_V1 0x30B0
240 #define R_AX_PCIE_HISR00_V1 0x30B4
249 #define R_AX_DRV_FW_HSK_0 0x01B0
250 #define R_AX_DRV_FW_HSK_1 0x01B4
251 #define R_AX_DRV_FW_HSK_2 0x01B8
252 #define R_AX_DRV_FW_HSK_3 0x01BC
253 #define R_AX_DRV_FW_HSK_4 0x01C0
254 #define R_AX_DRV_FW_HSK_5 0x01C4
255 #define R_AX_DRV_FW_HSK_6 0x01C8
256 #define R_AX_DRV_FW_HSK_7 0x01CC
258 #define R_AX_RXQ_RXBD_IDX 0x1050
259 #define R_AX_RPQ_RXBD_IDX 0x1054
260 #define R_AX_ACH0_TXBD_IDX 0x1058
261 #define R_AX_ACH1_TXBD_IDX 0x105C
262 #define R_AX_ACH2_TXBD_IDX 0x1060
263 #define R_AX_ACH3_TXBD_IDX 0x1064
264 #define R_AX_ACH4_TXBD_IDX 0x1068
265 #define R_AX_ACH5_TXBD_IDX 0x106C
266 #define R_AX_ACH6_TXBD_IDX 0x1070
267 #define R_AX_ACH7_TXBD_IDX 0x1074
268 #define R_AX_CH8_TXBD_IDX 0x1078 /* Management Queue band 0 */
269 #define R_AX_CH9_TXBD_IDX 0x107C /* HI Queue band 0 */
270 #define R_AX_CH10_TXBD_IDX 0x137C /* Management Queue band 1 */
271 #define R_AX_CH11_TXBD_IDX 0x1380 /* HI Queue band 1 */
272 #define R_AX_CH12_TXBD_IDX 0x1080 /* FWCMD Queue */
273 #define R_AX_CH10_TXBD_IDX_V1 0x11D0
274 #define R_AX_CH11_TXBD_IDX_V1 0x11D4
275 #define R_AX_RXQ_RXBD_IDX_V1 0x1218
276 #define R_AX_RPQ_RXBD_IDX_V1 0x121C
278 #define TXBD_HOST_IDX_MASK GENMASK(11, 0)
280 #define R_AX_ACH0_TXBD_DESA_L 0x1110
281 #define R_AX_ACH0_TXBD_DESA_H 0x1114
282 #define R_AX_ACH1_TXBD_DESA_L 0x1118
283 #define R_AX_ACH1_TXBD_DESA_H 0x111C
284 #define R_AX_ACH2_TXBD_DESA_L 0x1120
285 #define R_AX_ACH2_TXBD_DESA_H 0x1124
286 #define R_AX_ACH3_TXBD_DESA_L 0x1128
287 #define R_AX_ACH3_TXBD_DESA_H 0x112C
288 #define R_AX_ACH4_TXBD_DESA_L 0x1130
289 #define R_AX_ACH4_TXBD_DESA_H 0x1134
290 #define R_AX_ACH5_TXBD_DESA_L 0x1138
291 #define R_AX_ACH5_TXBD_DESA_H 0x113C
292 #define R_AX_ACH6_TXBD_DESA_L 0x1140
293 #define R_AX_ACH6_TXBD_DESA_H 0x1144
294 #define R_AX_ACH7_TXBD_DESA_L 0x1148
295 #define R_AX_ACH7_TXBD_DESA_H 0x114C
296 #define R_AX_CH8_TXBD_DESA_L 0x1150
297 #define R_AX_CH8_TXBD_DESA_H 0x1154
298 #define R_AX_CH9_TXBD_DESA_L 0x1158
299 #define R_AX_CH9_TXBD_DESA_H 0x115C
300 #define R_AX_CH10_TXBD_DESA_L 0x1358
301 #define R_AX_CH10_TXBD_DESA_H 0x135C
302 #define R_AX_CH11_TXBD_DESA_L 0x1360
303 #define R_AX_CH11_TXBD_DESA_H 0x1364
304 #define R_AX_CH12_TXBD_DESA_L 0x1160
305 #define R_AX_CH12_TXBD_DESA_H 0x1164
306 #define R_AX_RXQ_RXBD_DESA_L 0x1100
307 #define R_AX_RXQ_RXBD_DESA_H 0x1104
308 #define R_AX_RPQ_RXBD_DESA_L 0x1108
309 #define R_AX_RPQ_RXBD_DESA_H 0x110C
310 #define R_AX_RXQ_RXBD_DESA_L_V1 0x1220
311 #define R_AX_RXQ_RXBD_DESA_H_V1 0x1224
312 #define R_AX_RPQ_RXBD_DESA_L_V1 0x1228
313 #define R_AX_RPQ_RXBD_DESA_H_V1 0x122C
314 #define R_AX_ACH0_TXBD_DESA_L_V1 0x1230
315 #define R_AX_ACH0_TXBD_DESA_H_V1 0x1234
316 #define R_AX_ACH1_TXBD_DESA_L_V1 0x1238
317 #define R_AX_ACH1_TXBD_DESA_H_V1 0x123C
318 #define R_AX_ACH2_TXBD_DESA_L_V1 0x1240
319 #define R_AX_ACH2_TXBD_DESA_H_V1 0x1244
320 #define R_AX_ACH3_TXBD_DESA_L_V1 0x1248
321 #define R_AX_ACH3_TXBD_DESA_H_V1 0x124C
322 #define R_AX_ACH4_TXBD_DESA_L_V1 0x1250
323 #define R_AX_ACH4_TXBD_DESA_H_V1 0x1254
324 #define R_AX_ACH5_TXBD_DESA_L_V1 0x1258
325 #define R_AX_ACH5_TXBD_DESA_H_V1 0x125C
326 #define R_AX_ACH6_TXBD_DESA_L_V1 0x1260
327 #define R_AX_ACH6_TXBD_DESA_H_V1 0x1264
328 #define R_AX_ACH7_TXBD_DESA_L_V1 0x1268
329 #define R_AX_ACH7_TXBD_DESA_H_V1 0x126C
330 #define R_AX_CH8_TXBD_DESA_L_V1 0x1270
331 #define R_AX_CH8_TXBD_DESA_H_V1 0x1274
332 #define R_AX_CH9_TXBD_DESA_L_V1 0x1278
333 #define R_AX_CH9_TXBD_DESA_H_V1 0x127C
334 #define R_AX_CH12_TXBD_DESA_L_V1 0x1280
335 #define R_AX_CH12_TXBD_DESA_H_V1 0x1284
336 #define R_AX_CH10_TXBD_DESA_L_V1 0x1458
337 #define R_AX_CH10_TXBD_DESA_H_V1 0x145C
338 #define R_AX_CH11_TXBD_DESA_L_V1 0x1460
339 #define R_AX_CH11_TXBD_DESA_H_V1 0x1464
340 #define B_AX_DESC_NUM_MSK GENMASK(11, 0)
342 #define R_AX_RXQ_RXBD_NUM 0x1020
343 #define R_AX_RPQ_RXBD_NUM 0x1022
344 #define R_AX_ACH0_TXBD_NUM 0x1024
345 #define R_AX_ACH1_TXBD_NUM 0x1026
346 #define R_AX_ACH2_TXBD_NUM 0x1028
347 #define R_AX_ACH3_TXBD_NUM 0x102A
348 #define R_AX_ACH4_TXBD_NUM 0x102C
349 #define R_AX_ACH5_TXBD_NUM 0x102E
350 #define R_AX_ACH6_TXBD_NUM 0x1030
351 #define R_AX_ACH7_TXBD_NUM 0x1032
352 #define R_AX_CH8_TXBD_NUM 0x1034
353 #define R_AX_CH9_TXBD_NUM 0x1036
354 #define R_AX_CH10_TXBD_NUM 0x1338
355 #define R_AX_CH11_TXBD_NUM 0x133A
356 #define R_AX_CH12_TXBD_NUM 0x1038
357 #define R_AX_RXQ_RXBD_NUM_V1 0x1210
358 #define R_AX_RPQ_RXBD_NUM_V1 0x1212
359 #define R_AX_CH10_TXBD_NUM_V1 0x1438
360 #define R_AX_CH11_TXBD_NUM_V1 0x143A
362 #define R_AX_ACH0_BDRAM_CTRL 0x1200
363 #define R_AX_ACH1_BDRAM_CTRL 0x1204
364 #define R_AX_ACH2_BDRAM_CTRL 0x1208
365 #define R_AX_ACH3_BDRAM_CTRL 0x120C
366 #define R_AX_ACH4_BDRAM_CTRL 0x1210
367 #define R_AX_ACH5_BDRAM_CTRL 0x1214
368 #define R_AX_ACH6_BDRAM_CTRL 0x1218
369 #define R_AX_ACH7_BDRAM_CTRL 0x121C
370 #define R_AX_CH8_BDRAM_CTRL 0x1220
371 #define R_AX_CH9_BDRAM_CTRL 0x1224
372 #define R_AX_CH10_BDRAM_CTRL 0x1320
373 #define R_AX_CH11_BDRAM_CTRL 0x1324
374 #define R_AX_CH12_BDRAM_CTRL 0x1228
375 #define R_AX_ACH0_BDRAM_CTRL_V1 0x1300
376 #define R_AX_ACH1_BDRAM_CTRL_V1 0x1304
377 #define R_AX_ACH2_BDRAM_CTRL_V1 0x1308
378 #define R_AX_ACH3_BDRAM_CTRL_V1 0x130C
379 #define R_AX_ACH4_BDRAM_CTRL_V1 0x1310
380 #define R_AX_ACH5_BDRAM_CTRL_V1 0x1314
381 #define R_AX_ACH6_BDRAM_CTRL_V1 0x1318
382 #define R_AX_ACH7_BDRAM_CTRL_V1 0x131C
383 #define R_AX_CH8_BDRAM_CTRL_V1 0x1320
384 #define R_AX_CH9_BDRAM_CTRL_V1 0x1324
385 #define R_AX_CH12_BDRAM_CTRL_V1 0x1328
386 #define R_AX_CH10_BDRAM_CTRL_V1 0x1420
387 #define R_AX_CH11_BDRAM_CTRL_V1 0x1424
388 #define BDRAM_SIDX_MASK GENMASK(7, 0)
392 #define R_AX_PCIE_INIT_CFG1 0x1000
409 #define R_AX_TXDMA_ADDR_H 0x10F0
410 #define R_AX_RXDMA_ADDR_H 0x10F4
412 #define R_AX_PCIE_DMA_STOP1 0x1010
427 #define B_AX_STOP_RXQ BIT(0)
440 #define R_AX_PCIE_DMA_STOP2 0x1310
442 #define B_AX_STOP_CH10 BIT(0)
443 #define B_AX_TX_STOP2_ALL GENMASK(1, 0)
445 #define R_AX_TXBD_RWPTR_CLR1 0x1014
456 #define B_AX_CLR_ACH0_IDX BIT(0)
457 #define B_AX_TXBD_CLR1_ALL GENMASK(10, 0)
459 #define R_AX_RXBD_RWPTR_CLR 0x1018
461 #define B_AX_CLR_RXQ_IDX BIT(0)
462 #define B_AX_RXBD_CLR_ALL GENMASK(1, 0)
464 #define R_AX_TXBD_RWPTR_CLR2 0x1314
466 #define B_AX_CLR_CH10_IDX BIT(0)
467 #define B_AX_TXBD_CLR2_ALL GENMASK(1, 0)
469 #define R_AX_PCIE_DMA_BUSY1 0x101C
486 #define B_AX_RXQ_BUSY BIT(0)
495 #define R_AX_PCIE_DMA_BUSY2 0x131C
497 #define B_AX_CH10_BUSY BIT(0)
500 #define R_AX_PCIE_INIT_CFG2 0x1004
503 #define B_AX_PCIE_RX_APPLEN_MASK GENMASK(13, 0)
505 #define R_AX_PCIE_PS_CTRL 0x1008
508 #define R_AX_INT_MIT_RX 0x10D4
512 #define AX_RXTIMER_UNIT_64US 0
517 #define B_AX_RXTIMER_MATCH_MASK GENMASK(7, 0)
519 #define R_AX_DBG_ERR_FLAG 0x11C4
528 #define B_AX_PCIE_TXBD_4KBOUD_LENERR BIT(0)
530 #define R_AX_TXBD_RWPTR_CLR2_V1 0x11C4
532 #define B_AX_CLR_CH10_IDX BIT(0)
534 #define R_AX_LBC_WATCHDOG 0x11D8
537 #define B_AX_LBC_EN BIT(0)
539 #define R_AX_RXBD_RWPTR_CLR_V1 0x1200
541 #define B_AX_CLR_RXQ_IDX BIT(0)
543 #define R_AX_HAXI_EXP_CTRL 0x1204
544 #define B_AX_MAX_TAG_NUM_V1_MASK GENMASK(2, 0)
546 #define R_AX_PCIE_EXP_CTRL 0x13F0
551 #define R_AX_PCIE_RX_PREF_ADV 0x13F4
552 #define B_AX_RXDMA_PREF_ADV_EN BIT(0)
554 #define R_AX_PCIE_HRPWM_V1 0x30C0
555 #define R_AX_PCIE_CRPWM 0x30C4
568 #define RTW89_PCIE_L1_STS_V1 0x80
570 #define RTW89_PCIE_GEN1_SPEED 0x01
571 #define RTW89_PCIE_GEN2_SPEED 0x02
572 #define RTW89_PCIE_PHY_RATE 0x82
573 #define RTW89_PCIE_PHY_RATE_MASK GENMASK(1, 0)
574 #define RTW89_PCIE_L1SS_STS_V1 0x0168
578 #define RTW89_PCIE_BIT_PCI_L12 BIT(0)
579 #define RTW89_PCIE_ASPM_CTRL 0x070F
581 #define RTW89_L0DLY_MASK GENMASK(2, 0)
582 #define RTW89_PCIE_TIMER_CTRL 0x0718
584 #define RTW89_PCIE_L1_CTRL 0x0719
587 #define RTW89_PCIE_CLK_CTRL 0x0725
588 #define RTW89_PCIE_RST_MSTATE 0x0B48
589 #define RTW89_PCIE_BIT_CFG_RST_MSTATE BIT(0)
597 PCIE_PHY_GEN1_UNDEFINE = 0x7F,
601 PCIE_L0SDLY_1US = 0,
618 PCIE_CLKDLY_HW_0 = 0,
619 PCIE_CLKDLY_HW_30US = 0x1,
620 PCIE_CLKDLY_HW_50US = 0x2,
621 PCIE_CLKDLY_HW_100US = 0x3,
622 PCIE_CLKDLY_HW_150US = 0x4,
623 PCIE_CLKDLY_HW_200US = 0x5,
629 MAC_AX_BD_DEF = 0xFE
635 MAC_AX_RXBD_DEF = 0xFE
641 MAC_AX_TAG_DEF = 0xFE
645 MAC_AX_TX_BURST_16B = 0,
648 MAC_AX_TX_BURST_V1_64B = 0,
656 MAC_AX_TX_BURST_DEF = 0xFE
660 MAC_AX_RX_BURST_16B = 0,
663 MAC_AX_RX_BURST_V1_64B = 0,
666 MAC_AX_RX_BURST_V1_256B = 0,
667 MAC_AX_RX_BURST_DEF = 0xFE
681 MAC_AX_WD_DMA_INTVL_DEF = 0xFE
693 MAC_AX_TAG_NUM_DEF = 0xFE
697 MAC_AX_LBC_TMR_8US = 0,
708 MAC_AX_LBC_TMR_DEF = 0xFE
712 MAC_AX_PCIE_DISABLE = 0,
714 MAC_AX_PCIE_DEFAULT = 0xFE,
715 MAC_AX_PCIE_IGNORE = 0xFF
722 MAC_AX_IO_RCY_ANA_TMR_DEF = 0xFE
838 #define RTW89_PCI_ADDR_NUM(x) ((x) & GENMASK(5, 0))
850 #define B_PCIADDR_LEN_V1_MASK GENMASK(10, 0)
861 #define RTW89_TX_DONE 0x0
862 #define RTW89_TX_RETRY_LIMIT 0x1
863 #define RTW89_TX_LIFE_TIME 0x2
864 #define RTW89_TX_MACID_DROP 0x3
866 #define RTW89_PCI_RPP_MACID GENMASK(7, 0)
880 #define RTW89_PCI_RXBD_WRITE_SIZE GENMASK(13, 0)
921 #define RTW89_RX_TAG_MAX 0x1fff
929 u16 tag; /* range from 0x0001 ~ 0x1fff */
1037 txwd->len = 0; in rtw89_pci_dequeue_txwd()
1049 memset(txwd->vaddr, 0, wd_ring->page_size); in rtw89_pci_enqueue_txwd()
1056 return val == 0xffffffff || val == 0xeaeaeaea; in rtw89_pci_ltr_is_err_reg_val()