Lines Matching +full:pio +full:- +full:pins
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include "pinctrl-at91.h"
43 * @pioc_hwirq: PIO bank interrupt identifier on AIC
44 * @pioc_virq: PIO bank Linux virtual interrupt
45 * @regbase: PIO bank virtual address
92 * from the corresponding device datasheet. This value is different for pins
115 * struct at91_pmx_func - describes AT91 pinmux functions
135 * struct at91_pmx_pin - describes an At91 pin mux
149 * struct at91_pin_group - describes an At91 pin group
152 * array is the same as pins.
153 * @pins: an array of discrete physical pins used in this group, taken
154 * from the driver-local pin enumeration space
155 * @npins: the number of pins in this group array, i.e. the number of
156 * elements in .pins so we can iterate over that array
161 unsigned int *pins; member
166 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
191 enum at91_mux (*get_periph)(void __iomem *pio, unsigned mask);
192 void (*mux_A_periph)(void __iomem *pio, unsigned mask);
193 void (*mux_B_periph)(void __iomem *pio, unsigned mask);
194 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
195 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
196 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
197 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
198 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
199 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
200 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
201 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
202 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
203 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
204 unsigned (*get_drivestrength)(void __iomem *pio, unsigned pin);
205 void (*set_drivestrength)(void __iomem *pio, unsigned pin,
207 unsigned (*get_slewrate)(void __iomem *pio, unsigned pin);
208 void (*set_slewrate)(void __iomem *pio, unsigned pin, u32 slewrate);
241 for (i = 0; i < info->ngroups; i++) { in at91_pinctrl_find_group_by_name()
242 if (strcmp(info->groups[i].name, name)) in at91_pinctrl_find_group_by_name()
245 grp = &info->groups[i]; in at91_pinctrl_find_group_by_name()
246 dev_dbg(info->dev, "%s: %d 0:%d\n", name, grp->npins, grp->pins[0]); in at91_pinctrl_find_group_by_name()
257 return info->ngroups; in at91_get_groups_count()
265 return info->groups[selector].name; in at91_get_group_name()
269 const unsigned **pins, in at91_get_group_pins() argument
274 if (selector >= info->ngroups) in at91_get_group_pins()
275 return -EINVAL; in at91_get_group_pins()
277 *pins = info->groups[selector].pins; in at91_get_group_pins()
278 *npins = info->groups[selector].npins; in at91_get_group_pins()
286 seq_printf(s, "%s", dev_name(pctldev->dev)); in at91_pin_dbg_show()
302 * config maps for pins in at91_dt_node_to_map()
304 grp = at91_pinctrl_find_group_by_name(info, np->name); in at91_dt_node_to_map()
306 dev_err(info->dev, "unable to find group for node %pOFn\n", in at91_dt_node_to_map()
308 return -EINVAL; in at91_dt_node_to_map()
311 map_num += grp->npins; in at91_dt_node_to_map()
312 new_map = devm_kcalloc(pctldev->dev, map_num, sizeof(*new_map), in at91_dt_node_to_map()
315 return -ENOMEM; in at91_dt_node_to_map()
323 devm_kfree(pctldev->dev, new_map); in at91_dt_node_to_map()
324 return -EINVAL; in at91_dt_node_to_map()
327 new_map[0].data.mux.function = parent->name; in at91_dt_node_to_map()
328 new_map[0].data.mux.group = np->name; in at91_dt_node_to_map()
333 for (i = 0; i < grp->npins; i++) { in at91_dt_node_to_map()
336 pin_get_name(pctldev, grp->pins[i]); in at91_dt_node_to_map()
337 new_map[i].data.configs.configs = &grp->pins_conf[i].conf; in at91_dt_node_to_map()
341 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", in at91_dt_node_to_map()
342 (*map)->data.mux.function, (*map)->data.mux.group, map_num); in at91_dt_node_to_map()
367 return gpio_chips[bank]->regbase; in pin_to_controller()
385 ? pin - MAX_NB_GPIO_PER_BANK/2 : pin); in two_bit_pin_value_shift_amount()
404 static void at91_mux_disable_interrupt(void __iomem *pio, unsigned mask) in at91_mux_disable_interrupt() argument
406 writel_relaxed(mask, pio + PIO_IDR); in at91_mux_disable_interrupt()
409 static unsigned at91_mux_get_pullup(void __iomem *pio, unsigned pin) in at91_mux_get_pullup() argument
411 return !((readl_relaxed(pio + PIO_PUSR) >> pin) & 0x1); in at91_mux_get_pullup()
414 static void at91_mux_set_pullup(void __iomem *pio, unsigned mask, bool on) in at91_mux_set_pullup() argument
417 writel_relaxed(mask, pio + PIO_PPDDR); in at91_mux_set_pullup()
419 writel_relaxed(mask, pio + (on ? PIO_PUER : PIO_PUDR)); in at91_mux_set_pullup()
422 static bool at91_mux_get_output(void __iomem *pio, unsigned int pin, bool *val) in at91_mux_get_output() argument
424 *val = (readl_relaxed(pio + PIO_ODSR) >> pin) & 0x1; in at91_mux_get_output()
425 return (readl_relaxed(pio + PIO_OSR) >> pin) & 0x1; in at91_mux_get_output()
428 static void at91_mux_set_output(void __iomem *pio, unsigned int mask, in at91_mux_set_output() argument
431 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_mux_set_output()
432 writel_relaxed(mask, pio + (is_on ? PIO_OER : PIO_ODR)); in at91_mux_set_output()
435 static unsigned at91_mux_get_multidrive(void __iomem *pio, unsigned pin) in at91_mux_get_multidrive() argument
437 return (readl_relaxed(pio + PIO_MDSR) >> pin) & 0x1; in at91_mux_get_multidrive()
440 static void at91_mux_set_multidrive(void __iomem *pio, unsigned mask, bool on) in at91_mux_set_multidrive() argument
442 writel_relaxed(mask, pio + (on ? PIO_MDER : PIO_MDDR)); in at91_mux_set_multidrive()
445 static void at91_mux_set_A_periph(void __iomem *pio, unsigned mask) in at91_mux_set_A_periph() argument
447 writel_relaxed(mask, pio + PIO_ASR); in at91_mux_set_A_periph()
450 static void at91_mux_set_B_periph(void __iomem *pio, unsigned mask) in at91_mux_set_B_periph() argument
452 writel_relaxed(mask, pio + PIO_BSR); in at91_mux_set_B_periph()
455 static void at91_mux_pio3_set_A_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_A_periph() argument
458 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, in at91_mux_pio3_set_A_periph()
459 pio + PIO_ABCDSR1); in at91_mux_pio3_set_A_periph()
460 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_A_periph()
461 pio + PIO_ABCDSR2); in at91_mux_pio3_set_A_periph()
464 static void at91_mux_pio3_set_B_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_B_periph() argument
466 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, in at91_mux_pio3_set_B_periph()
467 pio + PIO_ABCDSR1); in at91_mux_pio3_set_B_periph()
468 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) & ~mask, in at91_mux_pio3_set_B_periph()
469 pio + PIO_ABCDSR2); in at91_mux_pio3_set_B_periph()
472 static void at91_mux_pio3_set_C_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_C_periph() argument
474 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); in at91_mux_pio3_set_C_periph()
475 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); in at91_mux_pio3_set_C_periph()
478 static void at91_mux_pio3_set_D_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_set_D_periph() argument
480 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); in at91_mux_pio3_set_D_periph()
481 writel_relaxed(readl_relaxed(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); in at91_mux_pio3_set_D_periph()
484 static enum at91_mux at91_mux_pio3_get_periph(void __iomem *pio, unsigned mask) in at91_mux_pio3_get_periph() argument
488 if (readl_relaxed(pio + PIO_PSR) & mask) in at91_mux_pio3_get_periph()
491 select = !!(readl_relaxed(pio + PIO_ABCDSR1) & mask); in at91_mux_pio3_get_periph()
492 select |= (!!(readl_relaxed(pio + PIO_ABCDSR2) & mask) << 1); in at91_mux_pio3_get_periph()
497 static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask) in at91_mux_get_periph() argument
501 if (readl_relaxed(pio + PIO_PSR) & mask) in at91_mux_get_periph()
504 select = readl_relaxed(pio + PIO_ABSR) & mask; in at91_mux_get_periph()
509 static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) in at91_mux_get_deglitch() argument
511 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1; in at91_mux_get_deglitch()
514 static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_set_deglitch() argument
516 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); in at91_mux_set_deglitch()
519 static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_deglitch() argument
521 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) in at91_mux_pio3_get_deglitch()
522 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); in at91_mux_pio3_get_deglitch()
527 static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_pio3_set_deglitch() argument
530 writel_relaxed(mask, pio + PIO_IFSCDR); in at91_mux_pio3_set_deglitch()
531 at91_mux_set_deglitch(pio, mask, is_on); in at91_mux_pio3_set_deglitch()
534 static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) in at91_mux_pio3_get_debounce() argument
536 *div = readl_relaxed(pio + PIO_SCDR); in at91_mux_pio3_get_debounce()
538 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) && in at91_mux_pio3_get_debounce()
539 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1); in at91_mux_pio3_get_debounce()
542 static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, in at91_mux_pio3_set_debounce() argument
546 writel_relaxed(mask, pio + PIO_IFSCER); in at91_mux_pio3_set_debounce()
547 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR); in at91_mux_pio3_set_debounce()
548 writel_relaxed(mask, pio + PIO_IFER); in at91_mux_pio3_set_debounce()
550 writel_relaxed(mask, pio + PIO_IFSCDR); in at91_mux_pio3_set_debounce()
553 static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_pulldown() argument
555 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1); in at91_mux_pio3_get_pulldown()
558 static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) in at91_mux_pio3_set_pulldown() argument
561 writel_relaxed(mask, pio + PIO_PUDR); in at91_mux_pio3_set_pulldown()
563 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); in at91_mux_pio3_set_pulldown()
566 static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) in at91_mux_pio3_disable_schmitt_trig() argument
568 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); in at91_mux_pio3_disable_schmitt_trig()
571 static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) in at91_mux_pio3_get_schmitt_trig() argument
573 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1; in at91_mux_pio3_get_schmitt_trig()
585 static unsigned at91_mux_sama5d3_get_drivestrength(void __iomem *pio, in at91_mux_sama5d3_get_drivestrength() argument
588 unsigned tmp = read_drive_strength(pio + in at91_mux_sama5d3_get_drivestrength()
599 static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio, in at91_mux_sam9x5_get_drivestrength() argument
602 unsigned tmp = read_drive_strength(pio + in at91_mux_sam9x5_get_drivestrength()
607 tmp = DRIVE_STRENGTH_BIT_MSK(HI) - tmp; in at91_mux_sam9x5_get_drivestrength()
612 static unsigned at91_mux_sam9x60_get_drivestrength(void __iomem *pio, in at91_mux_sam9x60_get_drivestrength() argument
615 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); in at91_mux_sam9x60_get_drivestrength()
623 static unsigned at91_mux_sam9x60_get_slewrate(void __iomem *pio, unsigned pin) in at91_mux_sam9x60_get_slewrate() argument
625 unsigned tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); in at91_mux_sam9x60_get_slewrate()
644 static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sama5d3_set_drivestrength() argument
652 set_drive_strength(pio + sama5d3_get_drive_register(pin), pin, setting); in at91_mux_sama5d3_set_drivestrength()
655 static void at91_mux_sam9x5_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sam9x5_set_drivestrength() argument
664 setting = DRIVE_STRENGTH_BIT_MSK(HI) - setting; in at91_mux_sam9x5_set_drivestrength()
666 set_drive_strength(pio + at91sam9x5_get_drive_register(pin), pin, in at91_mux_sam9x5_set_drivestrength()
670 static void at91_mux_sam9x60_set_drivestrength(void __iomem *pio, unsigned pin, in at91_mux_sam9x60_set_drivestrength() argument
680 tmp = readl_relaxed(pio + SAM9X60_PIO_DRIVER1); in at91_mux_sam9x60_set_drivestrength()
688 writel_relaxed(tmp, pio + SAM9X60_PIO_DRIVER1); in at91_mux_sam9x60_set_drivestrength()
691 static void at91_mux_sam9x60_set_slewrate(void __iomem *pio, unsigned pin, in at91_mux_sam9x60_set_slewrate() argument
699 tmp = readl_relaxed(pio + SAM9X60_PIO_SLEWR); in at91_mux_sam9x60_set_slewrate()
706 writel_relaxed(tmp, pio + SAM9X60_PIO_SLEWR); in at91_mux_sam9x60_set_slewrate()
779 if (pin->mux) { in at91_pin_dbg()
780 dev_dbg(dev, "pio%c%d configured as periph%c with conf = 0x%lx\n", in at91_pin_dbg()
781 pin->bank + 'A', pin->pin, pin->mux - 1 + 'A', pin->conf); in at91_pin_dbg()
783 dev_dbg(dev, "pio%c%d configured as gpio with conf = 0x%lx\n", in at91_pin_dbg()
784 pin->bank + 'A', pin->pin, pin->conf); in at91_pin_dbg()
794 if (pin->bank >= gpio_banks) { in pin_check_config()
795 dev_err(info->dev, "%s: pin conf %d bank_id %d >= nbanks %d\n", in pin_check_config()
796 name, index, pin->bank, gpio_banks); in pin_check_config()
797 return -EINVAL; in pin_check_config()
800 if (!gpio_chips[pin->bank]) { in pin_check_config()
801 dev_err(info->dev, "%s: pin conf %d bank_id %d not enabled\n", in pin_check_config()
802 name, index, pin->bank); in pin_check_config()
803 return -ENXIO; in pin_check_config()
806 if (pin->pin >= MAX_NB_GPIO_PER_BANK) { in pin_check_config()
807 dev_err(info->dev, "%s: pin conf %d pin_bank_id %d >= %d\n", in pin_check_config()
808 name, index, pin->pin, MAX_NB_GPIO_PER_BANK); in pin_check_config()
809 return -EINVAL; in pin_check_config()
812 if (!pin->mux) in pin_check_config()
815 mux = pin->mux - 1; in pin_check_config()
817 if (mux >= info->nmux) { in pin_check_config()
818 dev_err(info->dev, "%s: pin conf %d mux_id %d >= nmux %d\n", in pin_check_config()
819 name, index, mux, info->nmux); in pin_check_config()
820 return -EINVAL; in pin_check_config()
823 if (!(info->mux_mask[pin->bank * info->nmux + mux] & 1 << pin->pin)) { in pin_check_config()
824 dev_err(info->dev, "%s: pin conf %d mux_id %d not supported for pio%c%d\n", in pin_check_config()
825 name, index, mux, pin->bank + 'A', pin->pin); in pin_check_config()
826 return -EINVAL; in pin_check_config()
832 static void at91_mux_gpio_disable(void __iomem *pio, unsigned mask) in at91_mux_gpio_disable() argument
834 writel_relaxed(mask, pio + PIO_PDR); in at91_mux_gpio_disable()
837 static void at91_mux_gpio_enable(void __iomem *pio, unsigned mask, bool input) in at91_mux_gpio_enable() argument
839 writel_relaxed(mask, pio + PIO_PER); in at91_mux_gpio_enable()
840 writel_relaxed(mask, pio + (input ? PIO_ODR : PIO_OER)); in at91_mux_gpio_enable()
847 const struct at91_pmx_pin *pins_conf = info->groups[group].pins_conf; in at91_pmx_set()
849 uint32_t npins = info->groups[group].npins; in at91_pmx_set()
852 void __iomem *pio; in at91_pmx_set() local
854 dev_dbg(info->dev, "enable function %s group %s\n", in at91_pmx_set()
855 info->functions[selector].name, info->groups[group].name); in at91_pmx_set()
857 /* first check that all the pins of the group are valid with a valid in at91_pmx_set()
861 ret = pin_check_config(info, info->groups[group].name, i, pin); in at91_pmx_set()
868 at91_pin_dbg(info->dev, pin); in at91_pmx_set()
869 pio = pin_to_controller(info, pin->bank); in at91_pmx_set()
871 if (!pio) in at91_pmx_set()
874 mask = pin_to_mask(pin->pin); in at91_pmx_set()
875 at91_mux_disable_interrupt(pio, mask); in at91_pmx_set()
876 switch (pin->mux) { in at91_pmx_set()
878 at91_mux_gpio_enable(pio, mask, 1); in at91_pmx_set()
881 info->ops->mux_A_periph(pio, mask); in at91_pmx_set()
884 info->ops->mux_B_periph(pio, mask); in at91_pmx_set()
887 if (!info->ops->mux_C_periph) in at91_pmx_set()
888 return -EINVAL; in at91_pmx_set()
889 info->ops->mux_C_periph(pio, mask); in at91_pmx_set()
892 if (!info->ops->mux_D_periph) in at91_pmx_set()
893 return -EINVAL; in at91_pmx_set()
894 info->ops->mux_D_periph(pio, mask); in at91_pmx_set()
897 if (pin->mux) in at91_pmx_set()
898 at91_mux_gpio_disable(pio, mask); in at91_pmx_set()
908 return info->nfunctions; in at91_pmx_get_funcs_count()
916 return info->functions[selector].name; in at91_pmx_get_func_name()
925 *groups = info->functions[selector].groups; in at91_pmx_get_groups()
926 *num_groups = info->functions[selector].ngroups; in at91_pmx_get_groups()
941 dev_err(npct->dev, "invalid range\n"); in at91_gpio_request_enable()
942 return -EINVAL; in at91_gpio_request_enable()
944 if (!range->gc) { in at91_gpio_request_enable()
945 dev_err(npct->dev, "missing GPIO chip in range\n"); in at91_gpio_request_enable()
946 return -EINVAL; in at91_gpio_request_enable()
948 chip = range->gc; in at91_gpio_request_enable()
951 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); in at91_gpio_request_enable()
953 mask = 1 << (offset - chip->base); in at91_gpio_request_enable()
955 dev_dbg(npct->dev, "enable pin %u as PIO%c%d 0x%x\n", in at91_gpio_request_enable()
956 offset, 'A' + range->id, offset - chip->base, mask); in at91_gpio_request_enable()
958 writel_relaxed(mask, at91_chip->regbase + PIO_PER); in at91_gpio_request_enable()
969 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); in at91_gpio_disable_free()
986 void __iomem *pio; in at91_pinconf_get() local
992 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id); in at91_pinconf_get()
993 pio = pin_to_controller(info, pin_to_bank(pin_id)); in at91_pinconf_get()
995 if (!pio) in at91_pinconf_get()
996 return -EINVAL; in at91_pinconf_get()
1000 if (at91_mux_get_multidrive(pio, pin)) in at91_pinconf_get()
1003 if (at91_mux_get_pullup(pio, pin)) in at91_pinconf_get()
1006 if (info->ops->get_deglitch && info->ops->get_deglitch(pio, pin)) in at91_pinconf_get()
1008 if (info->ops->get_debounce && info->ops->get_debounce(pio, pin, &div)) in at91_pinconf_get()
1010 if (info->ops->get_pulldown && info->ops->get_pulldown(pio, pin)) in at91_pinconf_get()
1012 if (info->ops->get_schmitt_trig && info->ops->get_schmitt_trig(pio, pin)) in at91_pinconf_get()
1014 if (info->ops->get_drivestrength) in at91_pinconf_get()
1015 *config |= (info->ops->get_drivestrength(pio, pin) in at91_pinconf_get()
1017 if (info->ops->get_slewrate) in at91_pinconf_get()
1018 *config |= (info->ops->get_slewrate(pio, pin) << SLEWRATE_SHIFT); in at91_pinconf_get()
1019 if (at91_mux_get_output(pio, pin, &out)) in at91_pinconf_get()
1031 void __iomem *pio; in at91_pinconf_set() local
1039 dev_dbg(info->dev, in at91_pinconf_set()
1042 pio = pin_to_controller(info, pin_to_bank(pin_id)); in at91_pinconf_set()
1044 if (!pio) in at91_pinconf_set()
1045 return -EINVAL; in at91_pinconf_set()
1051 return -EINVAL; in at91_pinconf_set()
1053 at91_mux_set_output(pio, mask, config & OUTPUT, in at91_pinconf_set()
1055 at91_mux_set_pullup(pio, mask, config & PULL_UP); in at91_pinconf_set()
1056 at91_mux_set_multidrive(pio, mask, config & MULTI_DRIVE); in at91_pinconf_set()
1057 if (info->ops->set_deglitch) in at91_pinconf_set()
1058 info->ops->set_deglitch(pio, mask, config & DEGLITCH); in at91_pinconf_set()
1059 if (info->ops->set_debounce) in at91_pinconf_set()
1060 info->ops->set_debounce(pio, mask, config & DEBOUNCE, in at91_pinconf_set()
1062 if (info->ops->set_pulldown) in at91_pinconf_set()
1063 info->ops->set_pulldown(pio, mask, config & PULL_DOWN); in at91_pinconf_set()
1064 if (info->ops->disable_schmitt_trig && config & DIS_SCHMIT) in at91_pinconf_set()
1065 info->ops->disable_schmitt_trig(pio, mask); in at91_pinconf_set()
1066 if (info->ops->set_drivestrength) in at91_pinconf_set()
1067 info->ops->set_drivestrength(pio, pin, in at91_pinconf_set()
1070 if (info->ops->set_slewrate) in at91_pinconf_set()
1071 info->ops->set_slewrate(pio, pin, in at91_pinconf_set()
1145 static const char *gpio_compat = "atmel,at91rm9200-gpio";
1155 info->nactive_banks++; in at91_pinctrl_child_count()
1157 info->nfunctions++; in at91_pinctrl_child_count()
1158 info->ngroups += of_get_child_count(child); in at91_pinctrl_child_count()
1170 list = of_get_property(np, "atmel,mux-mask", &size); in at91_pinctrl_mux_mask()
1172 dev_err(info->dev, "can not read the mux-mask of %d\n", size); in at91_pinctrl_mux_mask()
1173 return -EINVAL; in at91_pinctrl_mux_mask()
1178 dev_err(info->dev, "wrong mux mask array should be by %d\n", gpio_banks); in at91_pinctrl_mux_mask()
1179 return -EINVAL; in at91_pinctrl_mux_mask()
1181 info->nmux = size / gpio_banks; in at91_pinctrl_mux_mask()
1183 info->mux_mask = devm_kcalloc(info->dev, size, sizeof(u32), in at91_pinctrl_mux_mask()
1185 if (!info->mux_mask) in at91_pinctrl_mux_mask()
1186 return -ENOMEM; in at91_pinctrl_mux_mask()
1188 ret = of_property_read_u32_array(np, "atmel,mux-mask", in at91_pinctrl_mux_mask()
1189 info->mux_mask, size); in at91_pinctrl_mux_mask()
1191 dev_err(info->dev, "can not read the mux-mask of %d\n", size); in at91_pinctrl_mux_mask()
1204 dev_dbg(info->dev, "group(%d): %pOFn\n", index, np); in at91_pinctrl_parse_groups()
1207 grp->name = np->name; in at91_pinctrl_parse_groups()
1210 * the binding format is atmel,pins = <bank pin mux CONFIG ...>, in at91_pinctrl_parse_groups()
1211 * do sanity check and calculate pins number in at91_pinctrl_parse_groups()
1213 list = of_get_property(np, "atmel,pins", &size); in at91_pinctrl_parse_groups()
1217 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); in at91_pinctrl_parse_groups()
1218 return -EINVAL; in at91_pinctrl_parse_groups()
1221 grp->npins = size / 4; in at91_pinctrl_parse_groups()
1222 pin = grp->pins_conf = devm_kcalloc(info->dev, in at91_pinctrl_parse_groups()
1223 grp->npins, in at91_pinctrl_parse_groups()
1226 grp->pins = devm_kcalloc(info->dev, grp->npins, sizeof(unsigned int), in at91_pinctrl_parse_groups()
1228 if (!grp->pins_conf || !grp->pins) in at91_pinctrl_parse_groups()
1229 return -ENOMEM; in at91_pinctrl_parse_groups()
1232 pin->bank = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1233 pin->pin = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1234 grp->pins[j] = pin->bank * MAX_NB_GPIO_PER_BANK + pin->pin; in at91_pinctrl_parse_groups()
1235 pin->mux = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1236 pin->conf = be32_to_cpu(*list++); in at91_pinctrl_parse_groups()
1238 at91_pin_dbg(info->dev, pin); in at91_pinctrl_parse_groups()
1255 dev_dbg(info->dev, "parse function(%d): %pOFn\n", index, np); in at91_pinctrl_parse_functions()
1257 func = &info->functions[index]; in at91_pinctrl_parse_functions()
1260 func->name = np->name; in at91_pinctrl_parse_functions()
1261 func->ngroups = of_get_child_count(np); in at91_pinctrl_parse_functions()
1262 if (func->ngroups == 0) { in at91_pinctrl_parse_functions()
1263 dev_err(info->dev, "no groups defined\n"); in at91_pinctrl_parse_functions()
1264 return -EINVAL; in at91_pinctrl_parse_functions()
1266 func->groups = devm_kcalloc(info->dev, in at91_pinctrl_parse_functions()
1267 func->ngroups, sizeof(char *), GFP_KERNEL); in at91_pinctrl_parse_functions()
1268 if (!func->groups) in at91_pinctrl_parse_functions()
1269 return -ENOMEM; in at91_pinctrl_parse_functions()
1272 func->groups[i] = child->name; in at91_pinctrl_parse_functions()
1273 grp = &info->groups[grp_index++]; in at91_pinctrl_parse_functions()
1285 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1286 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1287 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
1288 { .compatible = "microchip,sam9x60-pinctrl", .data = &sam9x60_ops },
1295 struct device *dev = &pdev->dev; in at91_pinctrl_probe_dt()
1299 struct device_node *np = dev->of_node; in at91_pinctrl_probe_dt()
1303 return -ENODEV; in at91_pinctrl_probe_dt()
1305 info->dev = dev; in at91_pinctrl_probe_dt()
1306 info->ops = of_device_get_match_data(dev); in at91_pinctrl_probe_dt()
1318 if (ngpio_chips_enabled < info->nactive_banks) in at91_pinctrl_probe_dt()
1319 return -EPROBE_DEFER; in at91_pinctrl_probe_dt()
1325 dev_dbg(dev, "nmux = %d\n", info->nmux); in at91_pinctrl_probe_dt()
1327 dev_dbg(dev, "mux-mask\n"); in at91_pinctrl_probe_dt()
1328 tmp = info->mux_mask; in at91_pinctrl_probe_dt()
1330 for (j = 0; j < info->nmux; j++, tmp++) { in at91_pinctrl_probe_dt()
1335 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); in at91_pinctrl_probe_dt()
1336 dev_dbg(dev, "ngroups = %d\n", info->ngroups); in at91_pinctrl_probe_dt()
1337 info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), in at91_pinctrl_probe_dt()
1339 if (!info->functions) in at91_pinctrl_probe_dt()
1340 return -ENOMEM; in at91_pinctrl_probe_dt()
1342 info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), in at91_pinctrl_probe_dt()
1344 if (!info->groups) in at91_pinctrl_probe_dt()
1345 return -ENOMEM; in at91_pinctrl_probe_dt()
1348 dev_dbg(dev, "nfunctions = %d\n", info->nfunctions); in at91_pinctrl_probe_dt()
1349 dev_dbg(dev, "ngroups = %d\n", info->ngroups); in at91_pinctrl_probe_dt()
1368 struct device *dev = &pdev->dev; in at91_pinctrl_probe()
1375 return -ENOMEM; in at91_pinctrl_probe()
1383 at91_pinctrl_desc.pins = pdesc = in at91_pinctrl_probe()
1385 if (!at91_pinctrl_desc.pins) in at91_pinctrl_probe()
1386 return -ENOMEM; in at91_pinctrl_probe()
1391 names = devm_kasprintf_strarray(dev, "pio", MAX_NB_GPIO_PER_BANK); in at91_pinctrl_probe()
1398 strreplace(name, '-', i + 'A'); in at91_pinctrl_probe()
1400 pdesc->number = k; in at91_pinctrl_probe()
1401 pdesc->name = name; in at91_pinctrl_probe()
1407 info->pctl = devm_pinctrl_register(dev, &at91_pinctrl_desc, info); in at91_pinctrl_probe()
1408 if (IS_ERR(info->pctl)) in at91_pinctrl_probe()
1409 return dev_err_probe(dev, PTR_ERR(info->pctl), "could not register AT91 pinctrl driver\n"); in at91_pinctrl_probe()
1411 /* We will handle a range of GPIO pins */ in at91_pinctrl_probe()
1414 pinctrl_add_gpio_range(info->pctl, &gpio_chips[i]->range); in at91_pinctrl_probe()
1424 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get_direction() local
1428 osr = readl_relaxed(pio + PIO_OSR); in at91_gpio_get_direction()
1438 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_input() local
1441 writel_relaxed(mask, pio + PIO_ODR); in at91_gpio_direction_input()
1448 void __iomem *pio = at91_gpio->regbase; in at91_gpio_get() local
1452 pdsr = readl_relaxed(pio + PIO_PDSR); in at91_gpio_get()
1460 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set() local
1463 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_gpio_set()
1470 void __iomem *pio = at91_gpio->regbase; in at91_gpio_set_multiple() local
1472 #define BITS_MASK(bits) (((bits) == 32) ? ~0U : (BIT(bits) - 1)) in at91_gpio_set_multiple()
1473 /* Mask additionally to ngpio as not all GPIO controllers have 32 pins */ in at91_gpio_set_multiple()
1474 uint32_t set_mask = (*mask & *bits) & BITS_MASK(chip->ngpio); in at91_gpio_set_multiple()
1475 uint32_t clear_mask = (*mask & ~(*bits)) & BITS_MASK(chip->ngpio); in at91_gpio_set_multiple()
1477 writel_relaxed(set_mask, pio + PIO_SODR); in at91_gpio_set_multiple()
1478 writel_relaxed(clear_mask, pio + PIO_CODR); in at91_gpio_set_multiple()
1485 void __iomem *pio = at91_gpio->regbase; in at91_gpio_direction_output() local
1488 writel_relaxed(mask, pio + (val ? PIO_SODR : PIO_CODR)); in at91_gpio_direction_output()
1489 writel_relaxed(mask, pio + PIO_OER); in at91_gpio_direction_output()
1500 void __iomem *pio = at91_gpio->regbase; in at91_gpio_dbg_show() local
1506 mode = at91_gpio->ops->get_periph(pio, mask); in at91_gpio_dbg_show()
1508 gpio_label, chip->label, i); in at91_gpio_dbg_show()
1512 readl_relaxed(pio + PIO_OSR) & mask ? in at91_gpio_dbg_show()
1515 readl_relaxed(pio + PIO_PDSR) & mask ? in at91_gpio_dbg_show()
1519 mode + 'A' - 1); in at91_gpio_dbg_show()
1531 return gpiochip_lock_as_irq(&at91_gpio->chip, irqd_to_hwirq(d)); in gpio_irq_request_resources()
1538 gpiochip_unlock_as_irq(&at91_gpio->chip, irqd_to_hwirq(d)); in gpio_irq_release_resources()
1550 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
1558 void __iomem *pio = at91_gpio->regbase; in gpio_irq_mask() local
1559 unsigned mask = 1 << d->hwirq; in gpio_irq_mask()
1562 gpiochip_disable_irq(&at91_gpio->chip, gpio); in gpio_irq_mask()
1564 if (pio) in gpio_irq_mask()
1565 writel_relaxed(mask, pio + PIO_IDR); in gpio_irq_mask()
1571 void __iomem *pio = at91_gpio->regbase; in gpio_irq_unmask() local
1572 unsigned mask = 1 << d->hwirq; in gpio_irq_unmask()
1575 gpiochip_enable_irq(&at91_gpio->chip, gpio); in gpio_irq_unmask()
1577 if (pio) in gpio_irq_unmask()
1578 writel_relaxed(mask, pio + PIO_IER); in gpio_irq_unmask()
1588 return -EINVAL; in gpio_irq_type()
1596 void __iomem *pio = at91_gpio->regbase; in alt_gpio_irq_type() local
1597 unsigned mask = 1 << d->hwirq; in alt_gpio_irq_type()
1602 writel_relaxed(mask, pio + PIO_ESR); in alt_gpio_irq_type()
1603 writel_relaxed(mask, pio + PIO_REHLSR); in alt_gpio_irq_type()
1607 writel_relaxed(mask, pio + PIO_ESR); in alt_gpio_irq_type()
1608 writel_relaxed(mask, pio + PIO_FELLSR); in alt_gpio_irq_type()
1612 writel_relaxed(mask, pio + PIO_LSR); in alt_gpio_irq_type()
1613 writel_relaxed(mask, pio + PIO_FELLSR); in alt_gpio_irq_type()
1617 writel_relaxed(mask, pio + PIO_LSR); in alt_gpio_irq_type()
1618 writel_relaxed(mask, pio + PIO_REHLSR); in alt_gpio_irq_type()
1626 writel_relaxed(mask, pio + PIO_AIMDR); in alt_gpio_irq_type()
1630 pr_warn("AT91: No type for GPIO irq offset %d\n", d->irq); in alt_gpio_irq_type()
1631 return -EINVAL; in alt_gpio_irq_type()
1635 writel_relaxed(mask, pio + PIO_AIMER); in alt_gpio_irq_type()
1648 unsigned mask = 1 << d->hwirq; in gpio_irq_set_wake()
1651 at91_gpio->wakeups |= mask; in gpio_irq_set_wake()
1653 at91_gpio->wakeups &= ~mask; in gpio_irq_set_wake()
1655 irq_set_irq_wake(at91_gpio->pioc_virq, state); in gpio_irq_set_wake()
1663 void __iomem *pio = at91_chip->regbase; in at91_gpio_suspend() local
1665 at91_chip->backups = readl_relaxed(pio + PIO_IMR); in at91_gpio_suspend()
1666 writel_relaxed(at91_chip->backups, pio + PIO_IDR); in at91_gpio_suspend()
1667 writel_relaxed(at91_chip->wakeups, pio + PIO_IER); in at91_gpio_suspend()
1669 if (!at91_chip->wakeups) in at91_gpio_suspend()
1670 clk_disable_unprepare(at91_chip->clock); in at91_gpio_suspend()
1672 dev_dbg(dev, "GPIO-%c may wake for %08x\n", in at91_gpio_suspend()
1673 'A' + at91_chip->id, at91_chip->wakeups); in at91_gpio_suspend()
1681 void __iomem *pio = at91_chip->regbase; in at91_gpio_resume() local
1683 if (!at91_chip->wakeups) in at91_gpio_resume()
1684 clk_prepare_enable(at91_chip->clock); in at91_gpio_resume()
1686 writel_relaxed(at91_chip->wakeups, pio + PIO_IDR); in at91_gpio_resume()
1687 writel_relaxed(at91_chip->backups, pio + PIO_IER); in at91_gpio_resume()
1697 void __iomem *pio = at91_gpio->regbase; in gpio_irq_handler() local
1707 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); in gpio_irq_handler()
1709 if (!at91_gpio->next) in gpio_irq_handler()
1711 at91_gpio = at91_gpio->next; in gpio_irq_handler()
1712 pio = at91_gpio->regbase; in gpio_irq_handler()
1713 gpio_chip = &at91_gpio->chip; in gpio_irq_handler()
1718 generic_handle_domain_irq(gpio_chip->irq.domain, n); in gpio_irq_handler()
1721 /* now it may re-trigger */ in gpio_irq_handler()
1727 struct device *dev = &pdev->dev; in at91_gpio_of_irq_setup()
1730 struct irq_data *d = irq_get_irq_data(at91_gpio->pioc_virq); in at91_gpio_of_irq_setup()
1737 return -ENOMEM; in at91_gpio_of_irq_setup()
1739 at91_gpio->pioc_hwirq = irqd_to_hwirq(d); in at91_gpio_of_irq_setup()
1741 gpio_irqchip->name = "GPIO"; in at91_gpio_of_irq_setup()
1742 gpio_irqchip->irq_request_resources = gpio_irq_request_resources; in at91_gpio_of_irq_setup()
1743 gpio_irqchip->irq_release_resources = gpio_irq_release_resources; in at91_gpio_of_irq_setup()
1744 gpio_irqchip->irq_ack = gpio_irq_ack; in at91_gpio_of_irq_setup()
1745 gpio_irqchip->irq_disable = gpio_irq_mask; in at91_gpio_of_irq_setup()
1746 gpio_irqchip->irq_mask = gpio_irq_mask; in at91_gpio_of_irq_setup()
1747 gpio_irqchip->irq_unmask = gpio_irq_unmask; in at91_gpio_of_irq_setup()
1748 gpio_irqchip->irq_set_wake = pm_ptr(gpio_irq_set_wake); in at91_gpio_of_irq_setup()
1749 gpio_irqchip->irq_set_type = at91_gpio->ops->irq_type; in at91_gpio_of_irq_setup()
1750 gpio_irqchip->flags = IRQCHIP_IMMUTABLE; in at91_gpio_of_irq_setup()
1752 /* Disable irqs of this PIO controller */ in at91_gpio_of_irq_setup()
1753 writel_relaxed(~0, at91_gpio->regbase + PIO_IDR); in at91_gpio_of_irq_setup()
1760 girq = &at91_gpio->chip.irq; in at91_gpio_of_irq_setup()
1762 girq->default_type = IRQ_TYPE_NONE; in at91_gpio_of_irq_setup()
1763 girq->handler = handle_edge_irq; in at91_gpio_of_irq_setup()
1770 gpiochip_prev = irq_get_handler_data(at91_gpio->pioc_virq); in at91_gpio_of_irq_setup()
1772 girq->parent_handler = gpio_irq_handler; in at91_gpio_of_irq_setup()
1773 girq->num_parents = 1; in at91_gpio_of_irq_setup()
1774 girq->parents = devm_kcalloc(dev, girq->num_parents, in at91_gpio_of_irq_setup()
1775 sizeof(*girq->parents), in at91_gpio_of_irq_setup()
1777 if (!girq->parents) in at91_gpio_of_irq_setup()
1778 return -ENOMEM; in at91_gpio_of_irq_setup()
1779 girq->parents[0] = at91_gpio->pioc_virq; in at91_gpio_of_irq_setup()
1786 if (prev->next) { in at91_gpio_of_irq_setup()
1787 prev = prev->next; in at91_gpio_of_irq_setup()
1789 prev->next = at91_gpio; in at91_gpio_of_irq_setup()
1794 return -EINVAL; in at91_gpio_of_irq_setup()
1813 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1814 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1815 { .compatible = "microchip,sam9x60-gpio", .data = &sam9x60_ops },
1821 struct device *dev = &pdev->dev; in at91_gpio_probe()
1822 struct device_node *np = dev->of_node; in at91_gpio_probe()
1834 return dev_err_probe(dev, -EBUSY, "%d slot is occupied.\n", alias_idx); in at91_gpio_probe()
1842 return -ENOMEM; in at91_gpio_probe()
1844 at91_chip->regbase = devm_platform_ioremap_resource(pdev, 0); in at91_gpio_probe()
1845 if (IS_ERR(at91_chip->regbase)) in at91_gpio_probe()
1846 return PTR_ERR(at91_chip->regbase); in at91_gpio_probe()
1848 at91_chip->ops = of_device_get_match_data(dev); in at91_gpio_probe()
1849 at91_chip->pioc_virq = irq; in at91_gpio_probe()
1851 at91_chip->clock = devm_clk_get_enabled(dev, NULL); in at91_gpio_probe()
1852 if (IS_ERR(at91_chip->clock)) in at91_gpio_probe()
1853 return dev_err_probe(dev, PTR_ERR(at91_chip->clock), "failed to get clock, ignoring.\n"); in at91_gpio_probe()
1855 at91_chip->chip = at91_gpio_template; in at91_gpio_probe()
1856 at91_chip->id = alias_idx; in at91_gpio_probe()
1858 chip = &at91_chip->chip; in at91_gpio_probe()
1859 chip->label = dev_name(dev); in at91_gpio_probe()
1860 chip->parent = dev; in at91_gpio_probe()
1861 chip->owner = THIS_MODULE; in at91_gpio_probe()
1862 chip->base = alias_idx * MAX_NB_GPIO_PER_BANK; in at91_gpio_probe()
1864 if (!of_property_read_u32(np, "#gpio-lines", &ngpio)) { in at91_gpio_probe()
1866 dev_err(dev, "at91_gpio.%d, gpio-nb >= %d failback to %d\n", in at91_gpio_probe()
1869 chip->ngpio = ngpio; in at91_gpio_probe()
1872 names = devm_kasprintf_strarray(dev, "pio", chip->ngpio); in at91_gpio_probe()
1876 for (i = 0; i < chip->ngpio; i++) in at91_gpio_probe()
1877 strreplace(names[i], '-', alias_idx + 'A'); in at91_gpio_probe()
1879 chip->names = (const char *const *)names; in at91_gpio_probe()
1881 range = &at91_chip->range; in at91_gpio_probe()
1882 range->name = chip->label; in at91_gpio_probe()
1883 range->id = alias_idx; in at91_gpio_probe()
1884 range->pin_base = range->base = range->id * MAX_NB_GPIO_PER_BANK; in at91_gpio_probe()
1886 range->npins = chip->ngpio; in at91_gpio_probe()
1887 range->gc = chip; in at91_gpio_probe()
1901 dev_info(dev, "at address %p\n", at91_chip->regbase); in at91_gpio_probe()
1910 .name = "gpio-at91",
1919 .name = "pinctrl-at91",