381 	if (op->cmd.dtr)  in cqspi_calc_dummy()
481 	if (op->cmd.dtr) {  in cqspi_enable_dtr()
524 	if (op->cmd.dtr)  in cqspi_command_read()
609 	if (op->cmd.dtr)  in cqspi_command_write()
665 	if (op->cmd.dtr)  in cqspi_read_setup()
967 	if (op->cmd.dtr)  in cqspi_write_setup()
984 	 * command in DTR mode.  in cqspi_write_setup()
1271 	 * address (all 0s) with the read status register command in DTR mode.  in cqspi_write()
1273 	 * the flash when it is polling the write completion register in DTR  in cqspi_write()
1274 	 * mode. So, we can not use direct mode when in DTR mode for writing  in cqspi_write()
1277 	if (!op->cmd.dtr && cqspi->use_direct_mode &&  in cqspi_write()
1424 	 * op->dummy.dtr is required for converting nbytes into ncycles.  in cqspi_supports_mem_op()
1425 	 * Also, don't check the dtr field of the op phase having zero nbytes.  in cqspi_supports_mem_op()
1427 	all_true = op->cmd.dtr &&  in cqspi_supports_mem_op()
1428 		   (!op->addr.nbytes || op->addr.dtr) &&  in cqspi_supports_mem_op()
1429 		   (!op->dummy.nbytes || op->dummy.dtr) &&  in cqspi_supports_mem_op()
1430 		   (!op->data.nbytes || op->data.dtr);  in cqspi_supports_mem_op()
1432 	all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr &&  in cqspi_supports_mem_op()
1433 		    !op->data.dtr;  in cqspi_supports_mem_op()
1436 		/* Right now we only support 8-8-8 DTR mode. */  in cqspi_supports_mem_op()
1444 		/* Mixed DTR modes are not supported. */  in cqspi_supports_mem_op()
1602 	.dtr = true,