Lines Matching +full:11 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - Port/Switch config area registers
69 * struct tb_cap_extended_short - Switch extended short capability
84 * struct tb_cap_extended_long - Switch extended long capability
102 * struct tb_cap_any - Structure capable of hold every capability
134 u32 unknown3:11;
140 bool fl_sk:1; /* send pulse to transfer one bit */
159 u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */
160 u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */
202 #define ROUTER_CS_5_SLP BIT(0)
203 #define ROUTER_CS_5_WOP BIT(1)
204 #define ROUTER_CS_5_WOU BIT(2)
205 #define ROUTER_CS_5_WOD BIT(3)
206 #define ROUTER_CS_5_CNS BIT(23)
207 #define ROUTER_CS_5_PTO BIT(24)
208 #define ROUTER_CS_5_UTO BIT(25)
209 #define ROUTER_CS_5_HCO BIT(26)
210 #define ROUTER_CS_5_CV BIT(31)
212 #define ROUTER_CS_6_SLPR BIT(0)
213 #define ROUTER_CS_6_TNS BIT(1)
214 #define ROUTER_CS_6_WOPS BIT(2)
215 #define ROUTER_CS_6_WOUS BIT(3)
216 #define ROUTER_CS_6_HCI BIT(18)
217 #define ROUTER_CS_6_CR BIT(25)
225 #define ROUTER_CS_26_ONS BIT(30)
226 #define ROUTER_CS_26_OV BIT(31)
245 #define TMU_RTR_CS_0_TD BIT(27)
246 #define TMU_RTR_CS_0_UCAP BIT(30)
257 #define TMU_RTR_CS_15_DELAY_AVG_MASK GENMASK(11, 6)
287 u32 max_counters:11;
301 u32 max_in_hop_id:11;
302 u32 max_out_hop_id:11;
316 #define ADP_CS_4_LCK BIT(31)
320 #define ADP_CS_5_DHP BIT(31)
324 #define TMU_ADP_CS_3_UDM BIT(29)
326 #define TMU_ADP_CS_6_DTS BIT(1)
329 #define TMU_ADP_CS_8_EUDM BIT(15)
343 #define LANE_ADP_CS_0_CL0S_SUPPORT BIT(26)
344 #define LANE_ADP_CS_0_CL1_SUPPORT BIT(27)
345 #define LANE_ADP_CS_0_CL2_SUPPORT BIT(28)
353 #define LANE_ADP_CS_1_CL0S_ENABLE BIT(10)
354 #define LANE_ADP_CS_1_CL1_ENABLE BIT(11)
355 #define LANE_ADP_CS_1_CL2_ENABLE BIT(12)
356 #define LANE_ADP_CS_1_LD BIT(14)
357 #define LANE_ADP_CS_1_LB BIT(15)
365 #define LANE_ADP_CS_1_PMS BIT(30)
373 #define PORT_CS_1_WNR_WRITE BIT(24)
374 #define PORT_CS_1_NR BIT(25)
375 #define PORT_CS_1_RC BIT(26)
376 #define PORT_CS_1_PND BIT(31)
379 #define PORT_CS_18_BE BIT(8)
380 #define PORT_CS_18_TCM BIT(9)
381 #define PORT_CS_18_CPS BIT(10)
382 #define PORT_CS_18_WOCS BIT(16)
383 #define PORT_CS_18_WODS BIT(17)
384 #define PORT_CS_18_WOU4S BIT(18)
386 #define PORT_CS_19_PC BIT(3)
387 #define PORT_CS_19_PID BIT(4)
388 #define PORT_CS_19_WOC BIT(16)
389 #define PORT_CS_19_WOD BIT(17)
390 #define PORT_CS_19_WOU4 BIT(18)
396 #define ADP_DP_CS_0_AE BIT(30)
397 #define ADP_DP_CS_0_VE BIT(31)
399 #define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11)
400 #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11
403 #define ADP_DP_CS_2_HDP BIT(6)
406 #define ADP_DP_CS_2_CA BIT(10)
407 #define ADP_DP_CS_2_GR_MASK GENMASK(12, 11)
408 #define ADP_DP_CS_2_GR_SHIFT 11
416 #define ADP_DP_CS_2_CMMS BIT(20)
420 #define ADP_DP_CS_3_HDPC BIT(9)
429 #define DP_STATUS_CTRL_CMHS BIT(25)
430 #define DP_STATUS_CTRL_UF BIT(26)
435 #define ADP_DP_CS_8_DPME BIT(30)
436 #define ADP_DP_CS_8_DR BIT(31)
442 #define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8)
453 #define DP_COMMON_CAP_UHBR10 BIT(17)
454 #define DP_COMMON_CAP_UHBR20 BIT(18)
455 #define DP_COMMON_CAP_UHBR13_5 BIT(19)
456 #define DP_COMMON_CAP_LTTPR_NS BIT(27)
457 #define DP_COMMON_CAP_BW_MODE BIT(28)
458 #define DP_COMMON_CAP_DPRX_DONE BIT(31)
461 #define ADP_DP_CS_8_DPME BIT(30)
462 #define ADP_DP_CS_8_DR BIT(31)
466 #define ADP_PCIE_CS_0_PE BIT(31)
468 #define ADP_PCIE_CS_1_EE BIT(0)
472 #define ADP_USB3_CS_0_V BIT(30)
473 #define ADP_USB3_CS_0_PE BIT(31)
475 #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0)
478 #define ADP_USB3_CS_1_HCA BIT(31)
480 #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0)
483 #define ADP_USB3_CS_2_CMR BIT(31)
489 #define ADP_USB3_CS_4_ULV BIT(7)
497 u32 next_hop:11; /*
511 u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
525 #define TB_TIME_VSEC_3_CS_26_TD BIT(22)
533 #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 BIT(2)
534 #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3)
537 #define TB_PLUG_EVENTS_USB_DISABLE BIT(2)
538 #define TB_PLUG_EVENTS_CS_1_LANE_DISABLE BIT(3)
539 #define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE BIT(4)
540 #define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE BIT(5)
541 #define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE BIT(6)
548 #define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK BIT(21)
553 #define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK BIT(30)
554 #define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK BIT(31)
583 #define TB_LC_CS_42_USB_PLUGGED BIT(31)
586 #define TB_LC_PORT_ATTR_BE BIT(12)
589 #define TB_LC_SX_CTRL_WOC BIT(1)
590 #define TB_LC_SX_CTRL_WOD BIT(2)
591 #define TB_LC_SX_CTRL_WODPC BIT(3)
592 #define TB_LC_SX_CTRL_WODPD BIT(4)
593 #define TB_LC_SX_CTRL_WOU4 BIT(5)
594 #define TB_LC_SX_CTRL_WOP BIT(6)
595 #define TB_LC_SX_CTRL_L1C BIT(16)
596 #define TB_LC_SX_CTRL_L1D BIT(17)
597 #define TB_LC_SX_CTRL_L2C BIT(20)
598 #define TB_LC_SX_CTRL_L2D BIT(21)
599 #define TB_LC_SX_CTRL_SLI BIT(29)
600 #define TB_LC_SX_CTRL_UPSTREAM BIT(30)
601 #define TB_LC_SX_CTRL_SLP BIT(31)
603 #define TB_LC_LINK_ATTR_CPS BIT(18)
606 #define TB_LC_LINK_REQ_XHCI_CONNECT BIT(31)