Lines Matching +full:ufs +full:- +full:ddr
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
21 #include <ufs/ufshcd.h>
22 #include "ufshcd-pltfrm.h"
23 #include <ufs/unipro.h>
24 #include "ufs-qcom.h"
25 #include <ufs/ufshci.h>
26 #include <ufs/ufs_quirks.h>
108 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
109 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
114 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init()
115 struct device *dev = hba->dev; in ufs_qcom_ice_init()
119 if (ice == ERR_PTR(-EOPNOTSUPP)) { in ufs_qcom_ice_init()
127 host->ice = ice; in ufs_qcom_ice_init()
128 hba->caps |= UFSHCD_CAP_CRYPTO; in ufs_qcom_ice_init()
135 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_resume()
136 return qcom_ice_resume(host->ice); in ufs_qcom_ice_resume()
143 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_suspend()
144 return qcom_ice_suspend(host->ice); in ufs_qcom_ice_suspend()
156 cfg->config_enable & UFS_CRYPTO_CONFIGURATION_ENABLE; in ufs_qcom_ice_program_key()
158 /* Only AES-256-XTS has been tested so far. */ in ufs_qcom_ice_program_key()
159 cap = hba->crypto_cap_array[cfg->crypto_cap_idx]; in ufs_qcom_ice_program_key()
162 return -EOPNOTSUPP; in ufs_qcom_ice_program_key()
165 return qcom_ice_program_key(host->ice, in ufs_qcom_ice_program_key()
168 cfg->crypto_key, in ufs_qcom_ice_program_key()
169 cfg->data_unit_size, slot); in ufs_qcom_ice_program_key()
171 return qcom_ice_evict_key(host->ice, slot); in ufs_qcom_ice_program_key()
212 if (optional && err == -ENOENT) { in ufs_qcom_host_clk_get()
217 if (err != -EPROBE_DEFER) in ufs_qcom_host_clk_get()
237 if (!host->is_lane_clks_enabled) in ufs_qcom_disable_lane_clks()
240 clk_disable_unprepare(host->tx_l1_sync_clk); in ufs_qcom_disable_lane_clks()
241 clk_disable_unprepare(host->tx_l0_sync_clk); in ufs_qcom_disable_lane_clks()
242 clk_disable_unprepare(host->rx_l1_sync_clk); in ufs_qcom_disable_lane_clks()
243 clk_disable_unprepare(host->rx_l0_sync_clk); in ufs_qcom_disable_lane_clks()
245 host->is_lane_clks_enabled = false; in ufs_qcom_disable_lane_clks()
251 struct device *dev = host->hba->dev; in ufs_qcom_enable_lane_clks()
253 if (host->is_lane_clks_enabled) in ufs_qcom_enable_lane_clks()
257 host->rx_l0_sync_clk); in ufs_qcom_enable_lane_clks()
262 host->tx_l0_sync_clk); in ufs_qcom_enable_lane_clks()
267 host->rx_l1_sync_clk); in ufs_qcom_enable_lane_clks()
272 host->tx_l1_sync_clk); in ufs_qcom_enable_lane_clks()
276 host->is_lane_clks_enabled = true; in ufs_qcom_enable_lane_clks()
281 clk_disable_unprepare(host->rx_l1_sync_clk); in ufs_qcom_enable_lane_clks()
283 clk_disable_unprepare(host->tx_l0_sync_clk); in ufs_qcom_enable_lane_clks()
285 clk_disable_unprepare(host->rx_l0_sync_clk); in ufs_qcom_enable_lane_clks()
293 struct device *dev = host->hba->dev; in ufs_qcom_init_lane_clks()
299 &host->rx_l0_sync_clk, false); in ufs_qcom_init_lane_clks()
304 &host->tx_l0_sync_clk, false); in ufs_qcom_init_lane_clks()
309 if (host->hba->lanes_per_direction > 1) { in ufs_qcom_init_lane_clks()
311 &host->rx_l1_sync_clk, false); in ufs_qcom_init_lane_clks()
316 &host->tx_l1_sync_clk, true); in ufs_qcom_init_lane_clks()
351 dev_err(hba->dev, "%s: unable to get TX_FSM_STATE, err %d\n", in ufs_qcom_check_hibern8()
355 dev_err(hba->dev, "%s: invalid TX_FSM_STATE = %d\n", in ufs_qcom_check_hibern8()
364 ufshcd_rmwl(host->hba, QUNIPRO_SEL, in ufs_qcom_select_unipro_mode()
368 if (host->hw_ver.major >= 0x05) in ufs_qcom_select_unipro_mode()
369 ufshcd_rmwl(host->hba, QUNIPRO_G4_SEL, 0, REG_UFS_CFG0); in ufs_qcom_select_unipro_mode()
376 * ufs_qcom_host_reset - reset host controller and PHY
384 if (!host->core_reset) { in ufs_qcom_host_reset()
385 dev_warn(hba->dev, "%s: reset control not set\n", __func__); in ufs_qcom_host_reset()
389 reenable_intr = hba->is_irq_enabled; in ufs_qcom_host_reset()
390 disable_irq(hba->irq); in ufs_qcom_host_reset()
391 hba->is_irq_enabled = false; in ufs_qcom_host_reset()
393 ret = reset_control_assert(host->core_reset); in ufs_qcom_host_reset()
395 dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n", in ufs_qcom_host_reset()
402 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to in ufs_qcom_host_reset()
407 ret = reset_control_deassert(host->core_reset); in ufs_qcom_host_reset()
409 dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n", in ufs_qcom_host_reset()
415 enable_irq(hba->irq); in ufs_qcom_host_reset()
416 hba->is_irq_enabled = true; in ufs_qcom_host_reset()
426 if (host->hw_ver.major == 0x1) { in ufs_qcom_get_hs_gear()
428 * HS-G3 operations may not reliably work on legacy QCOM in ufs_qcom_get_hs_gear()
429 * UFS host controller hardware even though capability in ufs_qcom_get_hs_gear()
432 * Hence downgrade the maximum supported gear to HS-G2. in ufs_qcom_get_hs_gear()
435 } else if (host->hw_ver.major >= 0x4) { in ufs_qcom_get_hs_gear()
439 /* Default is HS-G3 */ in ufs_qcom_get_hs_gear()
446 struct phy *phy = host->generic_phy; in ufs_qcom_power_up_sequence()
449 /* Reset UFS Host Controller and PHY */ in ufs_qcom_power_up_sequence()
452 dev_warn(hba->dev, "%s: host reset returned %d\n", in ufs_qcom_power_up_sequence()
455 /* phy initialization - calibrate the phy */ in ufs_qcom_power_up_sequence()
458 dev_err(hba->dev, "%s: phy init failed, ret = %d\n", in ufs_qcom_power_up_sequence()
463 phy_set_mode_ext(phy, PHY_MODE_UFS_HS_B, host->hs_gear); in ufs_qcom_power_up_sequence()
465 /* power on phy - start serdes and phy's power and clocks */ in ufs_qcom_power_up_sequence()
468 dev_err(hba->dev, "%s: phy power on failed, ret = %d\n", in ufs_qcom_power_up_sequence()
485 * Internal hardware sub-modules within the UTP controller control the CGCs.
486 * Hardware CGCs disable the clock to inactivate UTP sub-modules not involved
488 * this function enables them (after every UFS link startup) to save some power
518 /* check if UFS PHY moved from DISABLED to HIBERN8 */ in ufs_qcom_hce_enable_notify()
524 dev_err(hba->dev, "%s: invalid status %d\n", __func__, status); in ufs_qcom_hce_enable_notify()
525 err = -EINVAL; in ufs_qcom_hce_enable_notify()
532 * Return: zero for success and non-zero in case of a failure.
574 dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear); in ufs_qcom_cfg_timers()
575 return -EINVAL; in ufs_qcom_cfg_timers()
578 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_cfg_timers()
579 if (!strcmp(clki->name, "core_clk")) in ufs_qcom_cfg_timers()
580 core_clk_rate = clk_get_rate(clki->clk); in ufs_qcom_cfg_timers()
609 dev_err(hba->dev, in ufs_qcom_cfg_timers()
613 return -EINVAL; in ufs_qcom_cfg_timers()
615 tx_clk_cycles_per_us = hs_fr_table_rA[gear-1][1]; in ufs_qcom_cfg_timers()
618 dev_err(hba->dev, in ufs_qcom_cfg_timers()
622 return -EINVAL; in ufs_qcom_cfg_timers()
624 tx_clk_cycles_per_us = hs_fr_table_rB[gear-1][1]; in ufs_qcom_cfg_timers()
626 dev_err(hba->dev, "%s: invalid rate = %d\n", in ufs_qcom_cfg_timers()
628 return -EINVAL; in ufs_qcom_cfg_timers()
634 dev_err(hba->dev, in ufs_qcom_cfg_timers()
638 return -EINVAL; in ufs_qcom_cfg_timers()
640 tx_clk_cycles_per_us = pwm_fr_table[gear-1][1]; in ufs_qcom_cfg_timers()
644 dev_err(hba->dev, "%s: invalid mode = %d\n", __func__, hs); in ufs_qcom_cfg_timers()
645 return -EINVAL; in ufs_qcom_cfg_timers()
660 if (update_link_startup_timer && host->hw_ver.major != 0x5) { in ufs_qcom_cfg_timers()
683 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_link_startup_notify()
685 return -EINVAL; in ufs_qcom_link_startup_notify()
697 * Some UFS devices (and may be host) have issues if LCC is in ufs_qcom_link_startup_notify()
719 if (!host->device_reset) in ufs_qcom_device_reset_ctrl()
722 gpiod_set_value_cansleep(host->device_reset, asserted); in ufs_qcom_device_reset_ctrl()
729 struct phy *phy = host->generic_phy; in ufs_qcom_suspend()
743 /* reset the connected UFS device during power down */ in ufs_qcom_suspend()
756 struct phy *phy = host->generic_phy; in ufs_qcom_resume()
762 dev_err(hba->dev, "%s: failed PHY power on: %d\n", in ufs_qcom_resume()
782 if (host->dev_ref_clk_ctrl_mmio && in ufs_qcom_dev_ref_clk_ctrl()
783 (enable ^ host->is_dev_ref_clk_enabled)) { in ufs_qcom_dev_ref_clk_ctrl()
784 u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
787 temp |= host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
789 temp &= ~host->dev_ref_clk_en_mask; in ufs_qcom_dev_ref_clk_ctrl()
800 gating_wait = host->hba->dev_info.clk_gating_wait_us; in ufs_qcom_dev_ref_clk_ctrl()
808 * HS-MODE to LS-MODE or HIBERN8 state. Give it in ufs_qcom_dev_ref_clk_ctrl()
816 writel_relaxed(temp, host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
822 readl(host->dev_ref_clk_ctrl_mmio); in ufs_qcom_dev_ref_clk_ctrl()
832 host->is_dev_ref_clk_enabled = enable; in ufs_qcom_dev_ref_clk_ctrl()
838 struct device *dev = host->hba->dev; in ufs_qcom_icc_set_bw()
841 ret = icc_set_bw(host->icc_ddr, 0, mem_bw); in ufs_qcom_icc_set_bw()
847 ret = icc_set_bw(host->icc_cpu, 0, cfg_bw); in ufs_qcom_icc_set_bw()
858 struct ufs_pa_layer_attr *p = &host->dev_req_params; in ufs_qcom_get_bw_table()
859 int gear = max_t(u32, p->gear_rx, p->gear_tx); in ufs_qcom_get_bw_table()
860 int lane = max_t(u32, p->lane_rx, p->lane_tx); in ufs_qcom_get_bw_table()
863 if (p->hs_rate == PA_HS_MODE_B) in ufs_qcom_get_bw_table()
892 return -EINVAL; in ufs_qcom_pwr_change_notify()
907 dev_err(hba->dev, "%s: failed to determine capabilities\n", in ufs_qcom_pwr_change_notify()
917 if (dev_req_params->gear_tx > host->hs_gear) in ufs_qcom_pwr_change_notify()
918 host->hs_gear = dev_req_params->gear_tx; in ufs_qcom_pwr_change_notify()
921 if (!ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
925 if (host->hw_ver.major >= 0x4) { in ufs_qcom_pwr_change_notify()
927 dev_req_params->gear_tx, in ufs_qcom_pwr_change_notify()
932 if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx, in ufs_qcom_pwr_change_notify()
933 dev_req_params->pwr_rx, in ufs_qcom_pwr_change_notify()
934 dev_req_params->hs_rate, false)) { in ufs_qcom_pwr_change_notify()
935 dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n", in ufs_qcom_pwr_change_notify()
942 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
946 memcpy(&host->dev_req_params, in ufs_qcom_pwr_change_notify()
952 if (ufshcd_is_hs_mode(&hba->pwr_info) && in ufs_qcom_pwr_change_notify()
957 ret = -EINVAL; in ufs_qcom_pwr_change_notify()
983 if (hba->dev_quirks & UFS_DEVICE_QUIRK_HOST_PA_SAVECONFIGTIME) in ufs_qcom_apply_dev_quirks()
986 if (hba->dev_info.wmanufacturerid == UFS_VENDOR_WDC) in ufs_qcom_apply_dev_quirks()
987 hba->dev_quirks |= UFS_DEVICE_QUIRK_HOST_PA_TACTIVATE; in ufs_qcom_apply_dev_quirks()
996 if (host->hw_ver.major == 0x1) in ufs_qcom_get_ufs_hci_version()
1003 * ufs_qcom_advertise_quirks - advertise the known QCOM UFS controller quirks
1006 * QCOM UFS host controller might have some non standard behaviours (quirks)
1008 * quirks to standard UFS host controller driver so standard takes them into
1015 if (host->hw_ver.major == 0x01) { in ufs_qcom_advertise_quirks()
1016 hba->quirks |= UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS in ufs_qcom_advertise_quirks()
1020 if (host->hw_ver.minor == 0x0001 && host->hw_ver.step == 0x0001) in ufs_qcom_advertise_quirks()
1021 hba->quirks |= UFSHCD_QUIRK_BROKEN_INTR_AGGR; in ufs_qcom_advertise_quirks()
1023 hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC; in ufs_qcom_advertise_quirks()
1026 if (host->hw_ver.major == 0x2) { in ufs_qcom_advertise_quirks()
1027 hba->quirks |= UFSHCD_QUIRK_BROKEN_UFS_HCI_VERSION; in ufs_qcom_advertise_quirks()
1031 hba->quirks |= (UFSHCD_QUIRK_DELAY_BEFORE_DME_CMDS in ufs_qcom_advertise_quirks()
1036 if (host->hw_ver.major > 0x3) in ufs_qcom_advertise_quirks()
1037 hba->quirks |= UFSHCD_QUIRK_REINIT_AFTER_MAX_GEAR_SWITCH; in ufs_qcom_advertise_quirks()
1044 hba->caps |= UFSHCD_CAP_CLK_GATING | UFSHCD_CAP_HIBERN8_WITH_CLK_GATING; in ufs_qcom_set_caps()
1045 hba->caps |= UFSHCD_CAP_CLK_SCALING | UFSHCD_CAP_WB_WITH_CLK_SCALING; in ufs_qcom_set_caps()
1046 hba->caps |= UFSHCD_CAP_AUTO_BKOPS_SUSPEND; in ufs_qcom_set_caps()
1047 hba->caps |= UFSHCD_CAP_WB_EN; in ufs_qcom_set_caps()
1048 hba->caps |= UFSHCD_CAP_AGGR_POWER_COLLAPSE; in ufs_qcom_set_caps()
1049 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; in ufs_qcom_set_caps()
1051 if (host->hw_ver.major >= 0x2) { in ufs_qcom_set_caps()
1052 host->caps = UFS_QCOM_CAP_QUNIPRO | in ufs_qcom_set_caps()
1058 * ufs_qcom_setup_clocks - enables/disable clocks
1063 * Return: 0 on success, non-zero on failure.
1092 if (ufshcd_is_hs_mode(&hba->pwr_info)) in ufs_qcom_setup_clocks()
1109 ufs_qcom_assert_reset(host->hba); in ufs_qcom_reset_assert()
1120 ufs_qcom_deassert_reset(host->hba); in ufs_qcom_reset_deassert()
1137 struct device *dev = host->hba->dev; in ufs_qcom_icc_init()
1140 host->icc_ddr = devm_of_icc_get(dev, "ufs-ddr"); in ufs_qcom_icc_init()
1141 if (IS_ERR(host->icc_ddr)) in ufs_qcom_icc_init()
1142 return dev_err_probe(dev, PTR_ERR(host->icc_ddr), in ufs_qcom_icc_init()
1145 host->icc_cpu = devm_of_icc_get(dev, "cpu-ufs"); in ufs_qcom_icc_init()
1146 if (IS_ERR(host->icc_cpu)) in ufs_qcom_icc_init()
1147 return dev_err_probe(dev, PTR_ERR(host->icc_cpu), in ufs_qcom_icc_init()
1151 * Set Maximum bandwidth vote before initializing the UFS controller and in ufs_qcom_icc_init()
1164 * ufs_qcom_init - bind phy with controller
1170 * Return: -EPROBE_DEFER if binding fails, returns negative error
1176 struct device *dev = hba->dev; in ufs_qcom_init()
1184 dev_err(dev, "%s: no memory for qcom ufs host\n", __func__); in ufs_qcom_init()
1185 return -ENOMEM; in ufs_qcom_init()
1189 host->hba = hba; in ufs_qcom_init()
1193 host->core_reset = devm_reset_control_get_optional(hba->dev, "rst"); in ufs_qcom_init()
1194 if (IS_ERR(host->core_reset)) { in ufs_qcom_init()
1195 err = dev_err_probe(dev, PTR_ERR(host->core_reset), in ufs_qcom_init()
1200 /* Fire up the reset controller. Failure here is non-fatal. */ in ufs_qcom_init()
1201 host->rcdev.of_node = dev->of_node; in ufs_qcom_init()
1202 host->rcdev.ops = &ufs_qcom_reset_ops; in ufs_qcom_init()
1203 host->rcdev.owner = dev->driver->owner; in ufs_qcom_init()
1204 host->rcdev.nr_resets = 1; in ufs_qcom_init()
1205 err = devm_reset_controller_register(dev, &host->rcdev); in ufs_qcom_init()
1210 host->generic_phy = devm_phy_get(dev, "ufsphy"); in ufs_qcom_init()
1211 if (IS_ERR(host->generic_phy)) { in ufs_qcom_init()
1212 err = dev_err_probe(dev, PTR_ERR(host->generic_phy), "Failed to get PHY\n"); in ufs_qcom_init()
1221 host->device_reset = devm_gpiod_get_optional(dev, "reset", in ufs_qcom_init()
1223 if (IS_ERR(host->device_reset)) { in ufs_qcom_init()
1224 err = PTR_ERR(host->device_reset); in ufs_qcom_init()
1225 if (err != -EPROBE_DEFER) in ufs_qcom_init()
1230 ufs_qcom_get_controller_revision(hba, &host->hw_ver.major, in ufs_qcom_init()
1231 &host->hw_ver.minor, &host->hw_ver.step); in ufs_qcom_init()
1235 * moved inside UFS controller register address space itself. in ufs_qcom_init()
1237 if (host->hw_ver.major >= 0x02) { in ufs_qcom_init()
1238 host->dev_ref_clk_ctrl_mmio = hba->mmio_base + REG_UFS_CFG1; in ufs_qcom_init()
1239 host->dev_ref_clk_en_mask = BIT(26); in ufs_qcom_init()
1245 host->dev_ref_clk_ctrl_mmio = in ufs_qcom_init()
1247 if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) in ufs_qcom_init()
1248 host->dev_ref_clk_ctrl_mmio = NULL; in ufs_qcom_init()
1249 host->dev_ref_clk_en_mask = BIT(5); in ufs_qcom_init()
1253 list_for_each_entry(clki, &hba->clk_list_head, list) { in ufs_qcom_init()
1254 if (!strcmp(clki->name, "core_clk_unipro")) in ufs_qcom_init()
1255 clki->keep_link_active = true; in ufs_qcom_init()
1271 if (hba->dev->id < MAX_UFS_QCOM_HOSTS) in ufs_qcom_init()
1272 ufs_qcom_hosts[hba->dev->id] = host; in ufs_qcom_init()
1277 /* Failure is non-fatal */ in ufs_qcom_init()
1285 host->hs_gear = UFS_HS_G2; in ufs_qcom_init()
1300 phy_power_off(host->generic_phy); in ufs_qcom_exit()
1301 phy_exit(host->generic_phy); in ufs_qcom_exit()
1311 return -EINVAL; in ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div()
1387 struct ufs_pa_layer_attr *dev_req_params = &host->dev_req_params; in ufs_qcom_clk_scale_notify()
1420 dev_req_params->gear_rx, in ufs_qcom_clk_scale_notify()
1421 dev_req_params->pwr_rx, in ufs_qcom_clk_scale_notify()
1422 dev_req_params->hs_rate, in ufs_qcom_clk_scale_notify()
1433 ufshcd_rmwl(host->hba, UFS_REG_TEST_BUS_EN, in ufs_qcom_enable_test_bus()
1435 ufshcd_rmwl(host->hba, TEST_BUS_EN, TEST_BUS_EN, REG_UFS_CFG1); in ufs_qcom_enable_test_bus()
1441 host->testbus.select_major = TSTBUS_UNIPRO; in ufs_qcom_get_default_testbus_cfg()
1442 host->testbus.select_minor = 37; in ufs_qcom_get_default_testbus_cfg()
1447 if (host->testbus.select_major >= TSTBUS_MAX) { in ufs_qcom_testbus_cfg_is_ok()
1448 dev_err(host->hba->dev, in ufs_qcom_testbus_cfg_is_ok()
1450 __func__, host->testbus.select_major); in ufs_qcom_testbus_cfg_is_ok()
1464 return -EINVAL; in ufs_qcom_testbus_config()
1467 return -EPERM; in ufs_qcom_testbus_config()
1469 switch (host->testbus.select_major) { in ufs_qcom_testbus_config()
1526 ufshcd_rmwl(host->hba, TEST_BUS_SEL, in ufs_qcom_testbus_config()
1527 (u32)host->testbus.select_major << 19, in ufs_qcom_testbus_config()
1529 ufshcd_rmwl(host->hba, mask, in ufs_qcom_testbus_config()
1530 (u32)host->testbus.select_minor << offset, in ufs_qcom_testbus_config()
1568 /* clear bit 17 - UTP_DBG_RAMS_EN */ in ufs_qcom_dump_dbg_regs()
1594 * ufs_qcom_device_reset() - toggle the (optional) device reset line
1595 * @hba: per-adapter instance
1604 if (!host->device_reset) in ufs_qcom_device_reset()
1605 return -EOPNOTSUPP; in ufs_qcom_device_reset()
1608 * The UFS device shall detect reset pulses of 1us, sleep for 10us to in ufs_qcom_device_reset()
1625 p->polling_ms = 60; in ufs_qcom_config_scaling_param()
1626 p->timer = DEVFREQ_TIMER_DELAYED; in ufs_qcom_config_scaling_param()
1627 d->upthreshold = 70; in ufs_qcom_config_scaling_param()
1628 d->downdifferential = 5; in ufs_qcom_config_scaling_param()
1642 phy_power_off(host->generic_phy); in ufs_qcom_reinit_notify()
1663 struct platform_device *pdev = to_platform_device(hba->dev); in ufs_qcom_mcq_config_resource()
1668 memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); in ufs_qcom_mcq_config_resource()
1671 res = &hba->res[i]; in ufs_qcom_mcq_config_resource()
1672 res->resource = platform_get_resource_byname(pdev, in ufs_qcom_mcq_config_resource()
1674 res->name); in ufs_qcom_mcq_config_resource()
1675 if (!res->resource) { in ufs_qcom_mcq_config_resource()
1676 dev_info(hba->dev, "Resource %s not provided\n", res->name); in ufs_qcom_mcq_config_resource()
1678 return -ENODEV; in ufs_qcom_mcq_config_resource()
1681 res_mem = res->resource; in ufs_qcom_mcq_config_resource()
1682 res->base = hba->mmio_base; in ufs_qcom_mcq_config_resource()
1686 res->base = devm_ioremap_resource(hba->dev, res->resource); in ufs_qcom_mcq_config_resource()
1687 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1688 dev_err(hba->dev, "Failed to map res %s, err=%d\n", in ufs_qcom_mcq_config_resource()
1689 res->name, (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1690 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1691 res->base = NULL; in ufs_qcom_mcq_config_resource()
1697 res = &hba->res[RES_MCQ]; in ufs_qcom_mcq_config_resource()
1699 if (res->base) in ufs_qcom_mcq_config_resource()
1703 res_mcq = devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); in ufs_qcom_mcq_config_resource()
1705 return -ENOMEM; in ufs_qcom_mcq_config_resource()
1707 res_mcq->start = res_mem->start + in ufs_qcom_mcq_config_resource()
1708 MCQ_SQATTR_OFFSET(hba->mcq_capabilities); in ufs_qcom_mcq_config_resource()
1709 res_mcq->end = res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; in ufs_qcom_mcq_config_resource()
1710 res_mcq->flags = res_mem->flags; in ufs_qcom_mcq_config_resource()
1711 res_mcq->name = "mcq"; in ufs_qcom_mcq_config_resource()
1715 dev_err(hba->dev, "Failed to insert MCQ resource, err=%d\n", in ufs_qcom_mcq_config_resource()
1720 res->base = devm_ioremap_resource(hba->dev, res_mcq); in ufs_qcom_mcq_config_resource()
1721 if (IS_ERR(res->base)) { in ufs_qcom_mcq_config_resource()
1722 dev_err(hba->dev, "MCQ registers mapping failed, err=%d\n", in ufs_qcom_mcq_config_resource()
1723 (int)PTR_ERR(res->base)); in ufs_qcom_mcq_config_resource()
1724 ret = PTR_ERR(res->base); in ufs_qcom_mcq_config_resource()
1729 hba->mcq_base = res->base; in ufs_qcom_mcq_config_resource()
1732 res->base = NULL; in ufs_qcom_mcq_config_resource()
1743 mem_res = &hba->res[RES_UFS]; in ufs_qcom_op_runtime_config()
1744 sqdao_res = &hba->res[RES_MCQ_SQD]; in ufs_qcom_op_runtime_config()
1746 if (!mem_res->base || !sqdao_res->base) in ufs_qcom_op_runtime_config()
1747 return -EINVAL; in ufs_qcom_op_runtime_config()
1750 opr = &hba->mcq_opr[i]; in ufs_qcom_op_runtime_config()
1751 opr->offset = sqdao_res->resource->start - in ufs_qcom_op_runtime_config()
1752 mem_res->resource->start + 0x40 * i; in ufs_qcom_op_runtime_config()
1753 opr->stride = 0x100; in ufs_qcom_op_runtime_config()
1754 opr->base = sqdao_res->base + 0x40 * i; in ufs_qcom_op_runtime_config()
1769 struct ufshcd_res_info *mcq_vs_res = &hba->res[RES_MCQ_VS]; in ufs_qcom_get_outstanding_cqs()
1771 if (!mcq_vs_res->base) in ufs_qcom_get_outstanding_cqs()
1772 return -EINVAL; in ufs_qcom_get_outstanding_cqs()
1774 *ocqs = readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); in ufs_qcom_get_outstanding_cqs()
1792 u32 id = desc->msi_index; in ufs_qcom_mcq_esi_handler()
1793 struct ufs_hw_queue *hwq = &hba->uhq[id]; in ufs_qcom_mcq_esi_handler()
1808 if (host->esi_enabled) in ufs_qcom_config_esi()
1815 nr_irqs = hba->nr_hw_queues - hba->nr_queues[HCTX_TYPE_POLL]; in ufs_qcom_config_esi()
1816 ret = platform_msi_domain_alloc_irqs(hba->dev, nr_irqs, in ufs_qcom_config_esi()
1819 dev_err(hba->dev, "Failed to request Platform MSI %d\n", ret); in ufs_qcom_config_esi()
1823 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1824 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1825 ret = devm_request_irq(hba->dev, desc->irq, in ufs_qcom_config_esi()
1827 IRQF_SHARED, "qcom-mcq-esi", desc); in ufs_qcom_config_esi()
1829 dev_err(hba->dev, "%s: Fail to request IRQ for %d, err = %d\n", in ufs_qcom_config_esi()
1830 __func__, desc->irq, ret); in ufs_qcom_config_esi()
1835 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1839 msi_lock_descs(hba->dev); in ufs_qcom_config_esi()
1840 msi_for_each_desc(desc, hba->dev, MSI_DESC_ALL) { in ufs_qcom_config_esi()
1843 devm_free_irq(hba->dev, desc->irq, hba); in ufs_qcom_config_esi()
1845 msi_unlock_descs(hba->dev); in ufs_qcom_config_esi()
1846 platform_msi_domain_free_irqs(hba->dev); in ufs_qcom_config_esi()
1848 if (host->hw_ver.major == 6 && host->hw_ver.minor == 0 && in ufs_qcom_config_esi()
1849 host->hw_ver.step == 0) { in ufs_qcom_config_esi()
1859 host->esi_enabled = true; in ufs_qcom_config_esi()
1865 * struct ufs_hba_qcom_vops - UFS QCOM specific variant operations
1896 * ufs_qcom_probe - probe routine of the driver
1899 * Return: zero for success and non-zero for failure.
1904 struct device *dev = &pdev->dev; in ufs_qcom_probe()
1915 * ufs_qcom_remove - set driver_data of the device to NULL
1924 pm_runtime_get_sync(&(pdev)->dev); in ufs_qcom_remove()
1926 platform_msi_domain_free_irqs(hba->dev); in ufs_qcom_remove()
1961 .name = "ufshcd-qcom",