Lines Matching +full:0 +full:x407
26 /* Registers for page 0 of TPS6594 */
27 #define TPS6594_REG_DEV_REV 0x01
29 #define TPS6594_REG_NVM_CODE_1 0x02
30 #define TPS6594_REG_NVM_CODE_2 0x03
32 #define TPS6594_REG_BUCKX_CTRL(buck_inst) (0x04 + ((buck_inst) << 1))
33 #define TPS6594_REG_BUCKX_CONF(buck_inst) (0x05 + ((buck_inst) << 1))
34 #define TPS6594_REG_BUCKX_VOUT_1(buck_inst) (0x0e + ((buck_inst) << 1))
35 #define TPS6594_REG_BUCKX_VOUT_2(buck_inst) (0x0f + ((buck_inst) << 1))
36 #define TPS6594_REG_BUCKX_PG_WINDOW(buck_inst) (0x18 + (buck_inst))
38 #define TPS6594_REG_LDOX_CTRL(ldo_inst) (0x1d + (ldo_inst))
39 #define TPS6594_REG_LDORTC_CTRL 0x22
40 #define TPS6594_REG_LDOX_VOUT(ldo_inst) (0x23 + (ldo_inst))
41 #define TPS6594_REG_LDOX_PG_WINDOW(ldo_inst) (0x27 + (ldo_inst))
43 #define TPS6594_REG_VCCA_VMON_CTRL 0x2b
44 #define TPS6594_REG_VCCA_PG_WINDOW 0x2c
45 #define TPS6594_REG_VMON1_PG_WINDOW 0x2d
46 #define TPS6594_REG_VMON1_PG_LEVEL 0x2e
47 #define TPS6594_REG_VMON2_PG_WINDOW 0x2f
48 #define TPS6594_REG_VMON2_PG_LEVEL 0x30
50 #define TPS6594_REG_GPIOX_CONF(gpio_inst) (0x31 + (gpio_inst))
51 #define TPS6594_REG_NPWRON_CONF 0x3c
52 #define TPS6594_REG_GPIO_OUT_1 0x3d
53 #define TPS6594_REG_GPIO_OUT_2 0x3e
54 #define TPS6594_REG_GPIO_IN_1 0x3f
55 #define TPS6594_REG_GPIO_IN_2 0x40
59 #define TPS6594_REG_GPIO_IN_1 0x3f
60 #define TPS6594_REG_GPIO_IN_2 0x40
62 #define TPS6594_REG_RAIL_SEL_1 0x41
63 #define TPS6594_REG_RAIL_SEL_2 0x42
64 #define TPS6594_REG_RAIL_SEL_3 0x43
66 #define TPS6594_REG_FSM_TRIG_SEL_1 0x44
67 #define TPS6594_REG_FSM_TRIG_SEL_2 0x45
68 #define TPS6594_REG_FSM_TRIG_MASK_1 0x46
69 #define TPS6594_REG_FSM_TRIG_MASK_2 0x47
70 #define TPS6594_REG_FSM_TRIG_MASK_3 0x48
72 #define TPS6594_REG_MASK_BUCK1_2 0x49
73 #define TPS6594_REG_MASK_BUCK3_4 0x4a
74 #define TPS6594_REG_MASK_BUCK5 0x4b
75 #define TPS6594_REG_MASK_LDO1_2 0x4c
76 #define TPS6594_REG_MASK_LDO3_4 0x4d
77 #define TPS6594_REG_MASK_VMON 0x4e
78 #define TPS6594_REG_MASK_GPIO1_8_FALL 0x4f
79 #define TPS6594_REG_MASK_GPIO1_8_RISE 0x50
80 #define TPS6594_REG_MASK_GPIO9_11 0x51
81 #define TPS6594_REG_MASK_STARTUP 0x52
82 #define TPS6594_REG_MASK_MISC 0x53
83 #define TPS6594_REG_MASK_MODERATE_ERR 0x54
84 #define TPS6594_REG_MASK_FSM_ERR 0x56
85 #define TPS6594_REG_MASK_COMM_ERR 0x57
86 #define TPS6594_REG_MASK_READBACK_ERR 0x58
87 #define TPS6594_REG_MASK_ESM 0x59
89 #define TPS6594_REG_INT_TOP 0x5a
90 #define TPS6594_REG_INT_BUCK 0x5b
91 #define TPS6594_REG_INT_BUCK1_2 0x5c
92 #define TPS6594_REG_INT_BUCK3_4 0x5d
93 #define TPS6594_REG_INT_BUCK5 0x5e
94 #define TPS6594_REG_INT_LDO_VMON 0x5f
95 #define TPS6594_REG_INT_LDO1_2 0x60
96 #define TPS6594_REG_INT_LDO3_4 0x61
97 #define TPS6594_REG_INT_VMON 0x62
98 #define TPS6594_REG_INT_GPIO 0x63
99 #define TPS6594_REG_INT_GPIO1_8 0x64
100 #define TPS6594_REG_INT_STARTUP 0x65
101 #define TPS6594_REG_INT_MISC 0x66
102 #define TPS6594_REG_INT_MODERATE_ERR 0x67
103 #define TPS6594_REG_INT_SEVERE_ERR 0x68
104 #define TPS6594_REG_INT_FSM_ERR 0x69
105 #define TPS6594_REG_INT_COMM_ERR 0x6a
106 #define TPS6594_REG_INT_READBACK_ERR 0x6b
107 #define TPS6594_REG_INT_ESM 0x6c
109 #define TPS6594_REG_STAT_BUCK1_2 0x6d
110 #define TPS6594_REG_STAT_BUCK3_4 0x6e
111 #define TPS6594_REG_STAT_BUCK5 0x6f
112 #define TPS6594_REG_STAT_LDO1_2 0x70
113 #define TPS6594_REG_STAT_LDO3_4 0x71
114 #define TPS6594_REG_STAT_VMON 0x72
115 #define TPS6594_REG_STAT_STARTUP 0x73
116 #define TPS6594_REG_STAT_MISC 0x74
117 #define TPS6594_REG_STAT_MODERATE_ERR 0x75
118 #define TPS6594_REG_STAT_SEVERE_ERR 0x76
119 #define TPS6594_REG_STAT_READBACK_ERR 0x77
121 #define TPS6594_REG_PGOOD_SEL_1 0x78
122 #define TPS6594_REG_PGOOD_SEL_2 0x79
123 #define TPS6594_REG_PGOOD_SEL_3 0x7a
124 #define TPS6594_REG_PGOOD_SEL_4 0x7b
126 #define TPS6594_REG_PLL_CTRL 0x7c
128 #define TPS6594_REG_CONFIG_1 0x7d
129 #define TPS6594_REG_CONFIG_2 0x7e
131 #define TPS6594_REG_ENABLE_DRV_REG 0x80
133 #define TPS6594_REG_MISC_CTRL 0x81
135 #define TPS6594_REG_ENABLE_DRV_STAT 0x82
137 #define TPS6594_REG_RECOV_CNT_REG_1 0x83
138 #define TPS6594_REG_RECOV_CNT_REG_2 0x84
140 #define TPS6594_REG_FSM_I2C_TRIGGERS 0x85
141 #define TPS6594_REG_FSM_NSLEEP_TRIGGERS 0x86
143 #define TPS6594_REG_BUCK_RESET_REG 0x87
145 #define TPS6594_REG_SPREAD_SPECTRUM_1 0x88
147 #define TPS6594_REG_FREQ_SEL 0x8a
149 #define TPS6594_REG_FSM_STEP_SIZE 0x8b
151 #define TPS6594_REG_LDO_RV_TIMEOUT_REG_1 0x8c
152 #define TPS6594_REG_LDO_RV_TIMEOUT_REG_2 0x8d
154 #define TPS6594_REG_USER_SPARE_REGS 0x8e
156 #define TPS6594_REG_ESM_MCU_START_REG 0x8f
157 #define TPS6594_REG_ESM_MCU_DELAY1_REG 0x90
158 #define TPS6594_REG_ESM_MCU_DELAY2_REG 0x91
159 #define TPS6594_REG_ESM_MCU_MODE_CFG 0x92
160 #define TPS6594_REG_ESM_MCU_HMAX_REG 0x93
161 #define TPS6594_REG_ESM_MCU_HMIN_REG 0x94
162 #define TPS6594_REG_ESM_MCU_LMAX_REG 0x95
163 #define TPS6594_REG_ESM_MCU_LMIN_REG 0x96
164 #define TPS6594_REG_ESM_MCU_ERR_CNT_REG 0x97
165 #define TPS6594_REG_ESM_SOC_START_REG 0x98
166 #define TPS6594_REG_ESM_SOC_DELAY1_REG 0x99
167 #define TPS6594_REG_ESM_SOC_DELAY2_REG 0x9a
168 #define TPS6594_REG_ESM_SOC_MODE_CFG 0x9b
169 #define TPS6594_REG_ESM_SOC_HMAX_REG 0x9c
170 #define TPS6594_REG_ESM_SOC_HMIN_REG 0x9d
171 #define TPS6594_REG_ESM_SOC_LMAX_REG 0x9e
172 #define TPS6594_REG_ESM_SOC_LMIN_REG 0x9f
173 #define TPS6594_REG_ESM_SOC_ERR_CNT_REG 0xa0
175 #define TPS6594_REG_REGISTER_LOCK 0xa1
177 #define TPS6594_REG_MANUFACTURING_VER 0xa6
179 #define TPS6594_REG_CUSTOMER_NVM_ID_REG 0xa7
181 #define TPS6594_REG_VMON_CONF_REG 0xa8
183 #define TPS6594_REG_SOFT_REBOOT_REG 0xab
185 #define TPS6594_REG_RTC_SECONDS 0xb5
186 #define TPS6594_REG_RTC_MINUTES 0xb6
187 #define TPS6594_REG_RTC_HOURS 0xb7
188 #define TPS6594_REG_RTC_DAYS 0xb8
189 #define TPS6594_REG_RTC_MONTHS 0xb9
190 #define TPS6594_REG_RTC_YEARS 0xba
191 #define TPS6594_REG_RTC_WEEKS 0xbb
193 #define TPS6594_REG_ALARM_SECONDS 0xbc
194 #define TPS6594_REG_ALARM_MINUTES 0xbd
195 #define TPS6594_REG_ALARM_HOURS 0xbe
196 #define TPS6594_REG_ALARM_DAYS 0xbf
197 #define TPS6594_REG_ALARM_MONTHS 0xc0
198 #define TPS6594_REG_ALARM_YEARS 0xc1
200 #define TPS6594_REG_RTC_CTRL_1 0xc2
201 #define TPS6594_REG_RTC_CTRL_2 0xc3
202 #define TPS6594_REG_RTC_STATUS 0xc4
203 #define TPS6594_REG_RTC_INTERRUPTS 0xc5
204 #define TPS6594_REG_RTC_COMP_LSB 0xc6
205 #define TPS6594_REG_RTC_COMP_MSB 0xc7
206 #define TPS6594_REG_RTC_RESET_STATUS 0xc8
208 #define TPS6594_REG_SCRATCH_PAD_REG_1 0xc9
209 #define TPS6594_REG_SCRATCH_PAD_REG_2 0xca
210 #define TPS6594_REG_SCRATCH_PAD_REG_3 0xcb
211 #define TPS6594_REG_SCRATCH_PAD_REG_4 0xcc
213 #define TPS6594_REG_PFSM_DELAY_REG_1 0xcd
214 #define TPS6594_REG_PFSM_DELAY_REG_2 0xce
215 #define TPS6594_REG_PFSM_DELAY_REG_3 0xcf
216 #define TPS6594_REG_PFSM_DELAY_REG_4 0xd0
219 #define TPS6594_REG_SERIAL_IF_CONFIG 0x11a
220 #define TPS6594_REG_I2C1_ID 0x122
221 #define TPS6594_REG_I2C2_ID 0x123
224 #define TPS6594_REG_WD_ANSWER_REG 0x401
225 #define TPS6594_REG_WD_QUESTION_ANSW_CNT 0x402
226 #define TPS6594_REG_WD_WIN1_CFG 0x403
227 #define TPS6594_REG_WD_WIN2_CFG 0x404
228 #define TPS6594_REG_WD_LONGWIN_CFG 0x405
229 #define TPS6594_REG_WD_MODE_REG 0x406
230 #define TPS6594_REG_WD_QA_CFG 0x407
231 #define TPS6594_REG_WD_ERR_STATUS 0x408
232 #define TPS6594_REG_WD_THR_CFG 0x409
233 #define TPS6594_REG_DWD_FAIL_CNT_REG 0x40a
236 #define TPS6594_BIT_BUCK_EN BIT(0)
245 #define TPS6594_MASK_BUCK_SLEW_RATE GENMASK(2, 0)
249 #define TPS6594_MASK_BUCK_OV_THR GENMASK(2, 0)
253 #define TPS6594_MASK_BUCKS_VSET GENMASK(7, 0)
256 #define TPS6594_BIT_LDO_EN BIT(0)
263 #define TPS6594_BIT_LDORTC_DIS BIT(0)
267 #define TPS6594_MASK_LDO4_VSET GENMASK(6, 0)
271 #define TPS6594_MASK_LDO_OV_THR GENMASK(2, 0)
275 #define TPS6594_BIT_VMON_EN BIT(0)
283 #define TPS6594_MASK_VCCA_OV_THR GENMASK(2, 0)
288 #define TPS6594_MASK_VMONX_OV_THR GENMASK(2, 0)
293 #define TPS6594_BIT_GPIO_DIR BIT(0)
301 #define TPS6594_BIT_NRSTOUT_OD BIT(0)
316 #define TPS6594_MASK_BUCK1_GRP_SEL GENMASK(1, 0)
322 #define TPS6594_MASK_BUCK5_GRP_SEL GENMASK(1, 0)
328 #define TPS6594_MASK_LDO4_GRP_SEL GENMASK(1, 0)
334 #define TPS6594_MASK_MCU_RAIL_TRIG GENMASK(1, 0)
340 #define TPS6594_MASK_MODERATE_ERR_TRIG GENMASK(1, 0)
357 #define TPS6594_BIT_VCCA_OV_MASK BIT(0)
371 #define TPS6594_BIT_NPWRON_START_MASK BIT(0)
377 #define TPS6594_BIT_BIST_PASS_MASK BIT(0)
390 #define TPS6594_BIT_IMM_SHUTDOWN_MASK BIT(0)
396 #define TPS6594_BIT_COMM_FRM_ERR_MASK BIT(0)
403 #define TPS6594_BIT_EN_DRV_READBACK_MASK BIT(0)
407 #define TPS6594_BIT_ESM_SOC_PIN_MASK BIT(0)
415 #define TPS6594_BIT_BUCK_INT BIT(0)
425 #define TPS6594_BIT_BUCK1_2_INT BIT(0)
436 #define TPS6594_BIT_LDO1_2_INT BIT(0)
447 #define TPS6594_BIT_VCCA_OV_INT BIT(0)
457 #define TPS6594_BIT_GPIO9_INT BIT(0)
466 #define TPS6594_BIT_NPWRON_START_INT BIT(0)
473 #define TPS6594_BIT_BIST_PASS_INT BIT(0)
478 #define TPS6594_BIT_TSD_ORD_INT BIT(0)
488 #define TPS6594_BIT_TSD_IMM_INT BIT(0)
493 #define TPS6594_BIT_IMM_SHUTDOWN_INT BIT(0)
503 #define TPS6594_BIT_COMM_FRM_ERR_INT BIT(0)
510 #define TPS6594_BIT_EN_DRV_READBACK_INT BIT(0)
514 #define TPS6594_BIT_ESM_SOC_PIN_INT BIT(0)
532 #define TPS6594_BIT_VCCA_OV_STAT BIT(0)
547 #define TPS6594_BIT_TSD_ORD_STAT BIT(0)
550 #define TPS6594_BIT_TSD_IMM_STAT BIT(0)
554 #define TPS6594_BIT_EN_DRV_READBACK_STAT BIT(0)
560 #define TPS6594_MASK_PGOOD_SEL_BUCK1 GENMASK(1, 0)
566 #define TPS6594_MASK_PGOOD_SEL_BUCK5 GENMASK(1, 0)
569 #define TPS6594_MASK_PGOOD_SEL_LDO1 GENMASK(1, 0)
575 #define TPS6594_BIT_PGOOD_SEL_VCCA BIT(0)
585 #define TPS6594_MASK_EXT_CLK_FREQ GENMASK(1, 0)
588 #define TPS6594_BIT_TWARN_LEVEL BIT(0)
597 #define TPS6594_BIT_BB_CHARGER_EN BIT(0)
603 #define TPS6594_BIT_ENABLE_DRV BIT(0)
606 #define TPS6594_BIT_NRSTOUT BIT(0)
615 #define TPS6594_BIT_EN_DRV_IN BIT(0)
622 #define TPS6594_MASK_RECOV_CNT GENMASK(3, 0)
625 #define TPS6594_MASK_RECOV_CNT_THR GENMASK(3, 0)
632 #define TPS6594_BIT_NSLEEP1B BIT(0)
639 #define TPS6594_MASK_SS_DEPTH GENMASK(1, 0)
646 #define TPS6594_MASK_PFSM_DELAY_STEP GENMASK(4, 0)
649 #define TPS6594_MASK_LDO1_RV_TIMEOUT GENMASK(3, 0)
653 #define TPS6594_MASK_LDO3_RV_TIMEOUT GENMASK(3, 0)
660 #define TPS6594_BIT_ESM_MCU_START BIT(0)
663 #define TPS6594_MASK_ESM_MCU_ERR_CNT_TH GENMASK(3, 0)
669 #define TPS6594_MASK_ESM_MCU_ERR_CNT GENMASK(4, 0)
672 #define TPS6594_BIT_ESM_SOC_START BIT(0)
675 #define TPS6594_MASK_ESM_SOC_ERR_CNT_TH GENMASK(3, 0)
681 #define TPS6594_MASK_ESM_SOC_ERR_CNT GENMASK(4, 0)
684 #define TPS6594_BIT_REGISTER_LOCK_STATUS BIT(0)
687 #define TPS6594_MASK_VMON1_SLEW_RATE GENMASK(2, 0)
691 #define TPS6594_BIT_SOFT_REBOOT BIT(0)
694 #define TPS6594_MASK_SECOND_0 GENMASK(3, 0)
698 #define TPS6594_MASK_MINUTE_0 GENMASK(3, 0)
702 #define TPS6594_MASK_HOUR_0 GENMASK(3, 0)
707 #define TPS6594_MASK_DAY_0 GENMASK(3, 0)
711 #define TPS6594_MASK_MONTH_0 GENMASK(3, 0)
715 #define TPS6594_MASK_YEAR_0 GENMASK(3, 0)
719 #define TPS6594_MASK_WEEK GENMASK(2, 0)
722 #define TPS6594_BIT_STOP_RTC BIT(0)
731 #define TPS6594_BIT_XTAL_EN BIT(0)
745 #define TPS6594_MASK_EVERY GENMASK(1, 0)
750 #define TPS6594_BIT_RESET_STATUS_RTC BIT(0)
753 #define TPS6594_BIT_I2C_SPI_SEL BIT(0)
759 #define TPS6594_MASK_WD_QUESTION GENMASK(3, 0)
763 #define TPS6594_BIT_WD_RETURN_LONGWIN BIT(0)
768 #define TPS6594_MASK_WD_QUESTION_SEED GENMASK(3, 0)
773 #define TPS6594_BIT_WD_LONGWIN_TIMEOUT_INT BIT(0)
783 #define TPS6594_MASK_WD_RST_TH GENMASK(2, 0)
789 #define TPS6594_MASK_WD_FAIL_CNT GENMASK(3, 0)
794 #define TPS6594_CRC8_POLYNOMIAL 0x07