1 /* SPDX-License-Identifier: GPL-2.0-or-later
33  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
39  * struct spi_statistics - statistics for spi transfers
40  * @syncp:         seqcount to protect members in this struct for per-cpu update
41  *                 on 32-bit systems
43  * @messages:      number of spi-messages handled
92 		u64_stats_update_begin(&__lstats->syncp);		\
93 		u64_stats_add(&__lstats->field, count);			\
94 		u64_stats_update_end(&__lstats->syncp);			\
103 		u64_stats_update_begin(&__lstats->syncp);		\
104 		u64_stats_inc(&__lstats->field);			\
105 		u64_stats_update_end(&__lstats->syncp);			\
110  * struct spi_delay - SPI delay information
128  * struct spi_device - Controller side proxy for an SPI slave device
136  * @mode: The spi mode defines how data is clocked out and in.
142  *	like eight or 12 bits are common.  In-memory wordsizes are
151  * @controller_data: Board-specific definitions for controller, such as
195 	 * only half-duplex, the wait state detection needs to be implemented
209 #define SPI_MODE_KERNEL_MASK	(~(BIT(29) - 1))
217 	struct spi_delay	word_delay; /* Inter-word delay */
229 	 *  - memory packing (12 bit samples into low bits, others zeroed)
230 	 *  - priority
231 	 *  - chipselect delays
232 	 *  - ...
248 	return (spi && get_device(&spi->dev)) ? spi : NULL;  in spi_dev_get()
254 		put_device(&spi->dev);  in spi_dev_put()
260 	return spi->controller_state;  in spi_get_ctldata()
265 	spi->controller_state = state;  in spi_set_ctldata()
272 	dev_set_drvdata(&spi->dev, data);  in spi_set_drvdata()
277 	return dev_get_drvdata(&spi->dev);  in spi_get_drvdata()
282 	return spi->chip_select;  in spi_get_chipselect()
287 	spi->chip_select = chipselect;  in spi_set_chipselect()
292 	return spi->cs_gpiod;  in spi_get_csgpiod()
297 	spi->cs_gpiod = csgpiod;  in spi_set_csgpiod()
301  * struct spi_driver - Host side "protocol" driver
341  * spi_unregister_driver - reverse effect of spi_register_driver
348 		driver_unregister(&sdrv->driver);  in spi_unregister_driver()
358  * module_spi_driver() - Helper macro for registering a SPI driver
370  * struct spi_controller - interface to SPI master or slave controller
373  * @bus_num: board-specific (and often SOC-specific) identifier for a
392  * @devm_allocated: whether the allocation of this struct is devres-managed
393  * @max_transfer_size: function that returns the max transfer size for
395  * @max_message_size: function that returns the max message size for
411  * @cleanup: frees controller-specific state
421  * @cur_msg: the currently in-flight message
422  * @cur_msg_completion: a completion for the current in-flight message
430  * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip
460  *                  - return 0 if the transfer is finished,
461  *                  - return 1 if the transfer is still in progress. When
492  * @dummy_rx: dummy receive buffer for full-duplex devices
493  * @dummy_tx: dummy transmit buffer for full-duplex devices
498  *	time snapshot in @spi_transfer->ptp_sts as close as possible to the
499  *	moment in time when @spi_transfer->ptp_sts_word_pre and
500  *	@spi_transfer->ptp_sts_word_post were transmitted.
502  *	close to the driver hand-over as possible.
528 	 * board-specific. Usually that simplifies to being SoC-specific.
530 	 * and one board's schematics might show it using SPI-2. Software
537 	 * might use board-specific GPIOs.
554 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
555 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)  argument
571 	/* Flag indicating if the allocation of this struct is devres-managed */
625 	 * + For now there's no remove-from-queue operation, or
709 	/* Optimized handlers for SPI memory-like operations. */
722 	/* DMA channels for use with core dmaengine helpers */
748 	return dev_get_drvdata(&ctlr->dev);  in spi_controller_get_devdata()
754 	dev_set_drvdata(&ctlr->dev, data);  in spi_controller_set_devdata()
759 	if (!ctlr || !get_device(&ctlr->dev))  in spi_controller_get()
767 		put_device(&ctlr->dev);  in spi_controller_put()
772 	return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->slave;  in spi_controller_is_slave()
777 	return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target;  in spi_controller_is_target()
886  * struct spi_res - SPI resource management structure
889  * @data:    extra data allocated for the specific use-case
891  * This is based on ideas from devres, but focused on life-cycle
900 /*---------------------------------------------------------------------------*/
920  * struct spi_transfer - a read/write buffer pair
921  * @tx_buf: data to be written (DMA-safe memory), or NULL
922  * @rx_buf: data to be read (DMA-safe memory), or NULL
944  * @effective_speed_hz: the effective SCK-speed that was used to
961  *	purposefully (instead of setting to spi_transfer->len - 1) to denote
962  *	that a transfer-level snapshot taken from within the driver may still
989  * In-memory data values are always in native CPU byte order, translated
990  * from the wire byte order (big-endian except with SPI_LSB_FIRST).  So
994  * When the word size of the SPI transfer is not a power-of-two multiple
995  * of eight bits, those in-memory words include extra bits.  In-memory
996  * words are always seen by protocol drivers as right-justified, so the
1010  * stay selected until the next transfer.  On multi-device SPI busses
1020  * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
1026  * Zero-initialize every field you don't set up explicitly, to
1035 	 * spi_message.is_dma_mapped reports a pre-existing mapping.
1055 #define	SPI_NBITS_SINGLE	0x01 /* 1-bit transfer */
1056 #define	SPI_NBITS_DUAL		0x02 /* 2-bit transfer */
1057 #define	SPI_NBITS_QUAD		0x04 /* 4-bit transfer */
1075  * struct spi_message - one multi-segment SPI transaction
1103  * Zero-initialize every field you don't set up explicitly, to
1123 	 * Some controller drivers (message-at-a-time queue processing)
1125 	 * others (with multi-message pipelines) could need a flag to
1153 	INIT_LIST_HEAD(&m->transfers);  in spi_message_init_no_memset()
1154 	INIT_LIST_HEAD(&m->resources);  in spi_message_init_no_memset()
1166 	list_add_tail(&t->transfer_list, &m->transfers);  in spi_message_add_tail()
1172 	list_del(&t->transfer_list);  in spi_transfer_del()
1178 	return spi_delay_exec(&t->delay, t);  in spi_transfer_delay_exec()
1182  * spi_message_init_with_transfers - Initialize spi_message and append transfers
1215 			spi_message_add_tail(&m->t[i], m);  in spi_message_alloc()
1233 	struct spi_controller *ctlr = spi->controller;  in spi_max_message_size()
1235 	if (!ctlr->max_message_size)  in spi_max_message_size()
1237 	return ctlr->max_message_size(spi);  in spi_max_message_size()
1243 	struct spi_controller *ctlr = spi->controller;  in spi_max_transfer_size()
1247 	if (ctlr->max_transfer_size)  in spi_max_transfer_size()
1248 		tr_max = ctlr->max_transfer_size(spi);  in spi_max_transfer_size()
1255  * spi_is_bpw_supported - Check if bits per word is supported
1266 	u32 bpw_mask = spi->master->bits_per_word_mask;  in spi_is_bpw_supported()
1275  * spi_controller_xfer_timeout - Compute a suitable timeout value
1288 	return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U);  in spi_controller_xfer_timeout()
1291 /*---------------------------------------------------------------------------*/
1300  * struct spi_replaced_transfers - structure describing the spi_transfer
1309  *                      are to get re-inserted
1311  * @inserted_transfers: array of spi_transfers of array-size @inserted,
1327 /*---------------------------------------------------------------------------*/
1340 /*---------------------------------------------------------------------------*/
1354  * spi_sync_transfer - synchronous SPI data transfer
1378  * spi_write - SPI synchronous write
1401  * spi_read - SPI synchronous read
1429  * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1451  * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1456  * The number is returned in wire-order, which is at least sometimes
1457  * big-endian.
1476  * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1482  * convert the read 16 bit data word from big-endian to native endianness.
1502 /*---------------------------------------------------------------------------*/
1514  * support for non-static configurations too; enough to handle adding
1515  * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1519  * struct spi_board_info - board-specific template for a SPI device
1522  *	data stored there is driver-specific.
1528  *	from the chip datasheet and board-specific signal quality issues.
1543  * be stored in tables of board-specific device descriptors, which are
1589 	 *  - quirks like clock rate mattering when not selected
1635 	return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);  in spi_transfer_is_last()