37 #define HBI_FIRMWARE_PAGE	0xFF
38 #define ZL38_MAX_RAW_XFER	0x100
40 #define REG_TDMA_CFG_CLK	0x0262
42 #define CFG_CLK_PCLK_MASK	(0x7ff << CFG_CLK_PCLK_SHIFT)
45 #define CFG_CLK_FSRATE_MASK	0x7
46 #define CFG_CLK_FSRATE_8KHZ	0x1
47 #define CFG_CLK_FSRATE_16KHZ	0x2
48 #define CFG_CLK_FSRATE_48KHZ	0x6
50 #define REG_CLK_CFG		0x0016
53 #define REG_CLK_STATUS		0x0014
54 #define CLK_STATUS_HWRST	BIT(0)
56 #define REG_PARAM_RESULT	0x0034
57 #define PARAM_RESULT_READY	0xD3D3
59 #define REG_PG255_BASE_HI	0x000C
60 #define REG_PG255_OFFS(addr)	((HBI_FIRMWARE_PAGE << 8) | (addr & 0xFF))
61 #define REG_FWR_EXEC		0x012C
63 #define REG_CMD			0x0032
64 #define REG_HW_REV		0x0020
65 #define REG_FW_PROD		0x0022
66 #define REG_FW_REV		0x0024
68 #define REG_SEMA_FLAGS		0x0006
69 #define SEMA_FLAGS_BOOT_CMD	BIT(0)
72 #define REG_HW_REV		0x0020
73 #define REG_FW_PROD		0x0022
74 #define REG_FW_REV		0x0024
75 #define REG_GPIO_DIR		0x02DC
76 #define REG_GPIO_DAT		0x02DA
78 #define BOOTCMD_LOAD_COMPLETE	0x000D
79 #define BOOTCMD_FW_GO		0x0008
141 	__be32 addr_base = cpu_to_be32(addr & ~0xFF);  in zl38_fw_send_data()
266 	return 0;  in zl38_set_fmt()
313 	return 0;  in zl38_hw_params()
324 	return 0;  in zl38_hw_free()
330 	{ 0x0210, 0x0005 },	/* DAC1   in <= I2S1-L */
331 	{ 0x0212, 0x0006 },	/* DAC2   in <= I2S1-R */
332 	{ 0x0214, 0x0001 },	/* I2S1-L in <= MIC1   */
333 	{ 0x0216, 0x0001 },	/* I2S1-R in <= MIC1   */
334 	{ 0x0224, 0x0000 },	/* AEC-S  in <= n/a    */
335 	{ 0x0226, 0x0000 },	/* AEC-R  in <= n/a    */
337 	{ 0x0202, 0x000F },	/* enable I2S1 + DAC   */
395 	regmap_update_bits(regmap, REG_GPIO_DAT, mask, val ? mask : 0);  in chip_gpio_set()
417 	return regmap_update_bits(regmap, REG_GPIO_DIR, mask, 0);  in chip_direction_input()
460 	fw_major = (fwrev >> 12) & 0xF;  in zl38_check_revision()
461 	fw_minor = (fwrev >>  8) & 0xF;  in zl38_check_revision()
462 	fw_micro = fwrev & 0xFF;  in zl38_check_revision()
463 	dev_info(dev, "hw rev 0x%x, fw product code %d, firmware rev %d.%d.%d",  in zl38_check_revision()
464 		 hwrev & 0x1F, fwprod, fw_major, fw_minor, fw_micro);  in zl38_check_revision()
472 	return 0;  in zl38_check_revision()
481 	size_t len = 0;  in zl38_bus_read()
489 	page = reg_buf8[0];  in zl38_bus_read()
492 		txbuf[len++] = 0xFE;  in zl38_bus_read()
493 		txbuf[len++] = page == HBI_FIRMWARE_PAGE ? 0xFF : page - 1;  in zl38_bus_read()
497 		txbuf[len++] = offs | 0x80;  in zl38_bus_read()
508 	size_t val_len, len = 0;  in zl38_bus_write()
516 	page = data8[0];  in zl38_bus_write()
519 		buf[len++] = 0xFE;  in zl38_bus_write()
520 		buf[len++] = page == HBI_FIRMWARE_PAGE ? 0xFF : page - 1;  in zl38_bus_write()
522 		buf[len++] = (val_len / 2 - 1) | 0x80;  in zl38_bus_write()
524 		buf[len++] = offs | 0x80;  in zl38_bus_write()
525 		buf[len++] = (val_len / 2 - 1) | 0x80;  in zl38_bus_write()
563 		gpiod_set_value_cansleep(reset_gpio, 0);  in zl38_spi_probe()
618 	{ "zl38060", 0 },