Lines Matching +full:0 +full:x11210000
47 index 0b3cd7a33..763d37e86 100644
118 @@ -0,0 +1,270 @@
148 + reg = <0x82000000 0x20000000>;
233 + spidev@0 {
235 + reg = <0>;
236 + pl022,interface = <0>;
237 + pl022,com-mode = <0>;
245 + spidev@0 {
247 + reg = <0>;
248 + pl022,interface = <0>;
249 + pl022,com-mode = <0>;
255 + pl022,interface = <0>;
256 + pl022,com-mode = <0>;
264 + spidev@0 {
266 + reg = <0>;
267 + pl022,interface = <0>;
268 + pl022,com-mode = <0>;
291 + reg = <0>;
299 + reg = <0>;
394 @@ -0,0 +1,906 @@
450 + #size-cells = <0>;
453 + cpu@0 {
457 + reg = <0>;
475 + reg = <0x12010000 0x1000>;
481 + #address-cells = <0>;
484 + reg = <0x10301000 0x1000>, <0x10302000 0x100>;
490 + interrupts = <1 13 0xf08>,
491 + <1 14 0xf08>;
504 + #clock-cells = <0>;
510 + #clock-cells = <0>;
516 + interrupts = <0 54 4>;
521 + reg = <0x10060000 0x1000>;
522 + interrupts = <0 28 4>;
526 + resets = <&clock 0x194 0>;
530 + devid = <0>;
538 + reg = <0x10060000 0x1000>;
539 + interrupts = <0 28 4>;
543 + resets = <&clock 0x194 0>;
547 + devid = <0>;
555 + reg = <0x12020000 0x1000>;
556 + reboot-offset = <0x4>;
569 + reg = <0x12000000 0x20>, /* clocksource */
570 + <0x12000020 0x20>, /* local timer for each cpu */
571 + <0x12001000 0x20>;
572 + interrupts = <0 1 4>, /* irq of local timer */
573 + <0 2 4>;
583 + interrupts = <0 3 4>;
584 + reg = <0x12002000 0x1000>;
592 + arm,primecell-periphid = <0x00141805>;
593 + reg = <0x12051000 0x1000>;
601 + reg = <0x120a0000 0x1000>;
602 + interrupts = <0 6 4>;
610 + reg = <0x120a1000 0x1000>;
611 + interrupts = <0 7 4>;
623 + reg = <0x120a2000 0x1000>;
624 + interrupts = <0 8 4>;
636 + reg = <0x120a3000 0x1000>;
637 + interrupts = <0 9 4>;
649 + reg = <0x120a4000 0x1000>;
650 + interrupts = <0 10 4>;
665 + reg = <0x120b0000 0x1000>;
668 + dmas = <&hiedmacv310_0 1 1>, <&hiedmacv310_0 0 0>;
676 + reg = <0x120b1000 0x1000>;
687 + reg = <0x120b2000 0x1000>;
698 + reg = <0x120b3000 0x1000>;
709 + reg = <0x120b4000 0x1000>;
719 + reg = <0x120b5000 0x1000>;
730 + reg = <0x120b6000 0x1000>;
741 + reg = <0x120b7000 0x1000>;
753 + arm,primecell-periphid = <0x00800022>;
754 + reg = <0x120c0000 0x1000>;
755 + interrupts = <0 68 4>;
759 + #size-cells = <0>;
769 + arm,primecell-periphid = <0x00800022>;
770 + reg = <0x120c1000 0x1000>, <0x12030000 0x4>;
771 + interrupts = <0 69 4>;
775 + #size-cells = <0>;
778 + hisi,spi_cs_mask_bit = <0x4>;//0100
788 + arm,primecell-periphid = <0x00800022>;
789 + reg = <0x120c2000 0x1000>;
790 + interrupts = <0 70 4>;
794 + #size-cells = <0>;
806 + interrupts = <0 10 4>;
807 + reg = <0x10300000 0x4000>;
813 + reg = <0x10011100 0x10>;
818 + resets = <&clock 0x16c 3>;
821 + #size-cells = <0>;
827 + reg = <0x10010000 0x1000>,<0x10011300 0x200>;
828 + interrupts = <0 32 4>;
830 + resets = <&clock 0x16c 0>;
836 + reg = <0x10000000 0x1000>, <0x14000000 0x10000>;
839 + max-dma-size = <0x2000>;
841 + #size-cells = <0>;
843 + hisfc:spi-nor@0 {
848 + #size-cells = <0>;
851 + hisnfc:spi-nand@0 {
856 + #size-cells = <0>;
860 + mmc0: himci.eMMC@0x10100000 {
862 + reg = <0x10100000 0x1000>;
863 + interrupts = <0 64 4>;
866 + resets = <&clock 0x148 0>;
872 + devid = <0>;
876 + mmc1: himci.SD@0x100f0000 {
878 + reg = <0x100f0000 0x1000>;
879 + interrupts = <0 30 4>;
882 + resets = <&clock 0x160 0>;
896 + mmc2: himci.SD@0x10020000 {
898 + reg = <0x10020000 0x1000>;
899 + interrupts = <0 31 4>;
902 + resets = <&clock 0x154 0>;
915 + reg = <0x10060000 0x1000>;
916 + interrupts = <0 28 4>;
919 + resets = <&clock 0xc8 4>;
927 + reg = <0x12010000 0x1000>;
928 + #phy-cells = <0>;
932 + xhci_0@0x100e0000 {
934 + reg = <0x100e0000 0x10000>;
935 + interrupts = <0 27 4>;
940 + hidwc3_0@0x100e0000 {
942 + reg = <0x100e0000 0x10000>;
943 + interrupts = <0 27 4>;
951 + reg = <0x120d0000 0x1000>;
952 + interrupts = <0 16 4>;
961 + reg = <0x120d1000 0x1000>;
962 + interrupts = <0 17 4>;
971 + reg = <0x120d2000 0x1000>;
972 + interrupts = <0 18 4>;
981 + reg = <0x120d3000 0x1000>;
982 + interrupts = <0 19 4>;
991 + reg = <0x120d4000 0x1000>;
992 + interrupts = <0 20 4>;
1001 + reg = <0x120d5000 0x1000>;
1002 + interrupts = <0 21 4>;
1011 + reg = <0x120d6000 0x1000>;
1012 + interrupts = <0 22 4>;
1021 + reg = <0x120d7000 0x1000>;
1022 + interrupts = <0 23 4>;
1031 + reg = <0x120d8000 0x1000>;
1032 + interrupts = <0 24 4>;
1041 + reg = <0x120d9000 0x1000>;
1042 + interrupts = <0 25 4>;
1051 + reg = <0x120da000 0x1000>;
1052 + interrupts = <0 26 4>;
1061 + reg = <0x120db000 0x1000>;
1062 + interrupts = <0 80 4>;
1069 + cipher: cipher@0x100c0000 {
1071 + reg = <0x100c0000 0x10000>;
1073 + interrupts = <0 71 4>, <0 72 4>, <0 71 4>, <0 72 4>;
1100 + reg = <0x12010000 0x10000>, <0x12020000 0x8000>,
1101 + <0x12060000 0x10000>, <0x12030000 0x8000>;
1107 + reg = <0x113a0000 0x10000>;
1109 + interrupts = <0 57 4>;
1115 + reg = <0x11270000 0x10000>;
1117 + interrupts = <0 63 4>;
1123 + reg = <0x11300000 0xa0000>, <0x11000000 0x40000>;
1125 + interrupts = <0 56 4>, <0 44 4>;
1131 + reg = <0x11020000 0x20000>;
1133 + interrupts = <0 56 4>;
1139 + reg = <0x11040000 0x10000>;
1141 + interrupts = <0 43 4>;
1147 + reg = <0x11240000 0x10000>;
1149 + interrupts = <0 38 4>;
1155 + reg = <0x11440000 0x40000>;
1157 + interrupts = <0 58 4>;
1163 + reg = <0x11440000 0x40000>, <0x12020000 0x8000>;
1165 + interrupts = <0 59 4>, <0 51 4>;
1171 + reg = <0x11210000 0x10000>;
1173 + interrupts = <0 35 4>;
1183 + reg = <0x11110000 0x10000>, <0x11100000 0x10000>;
1185 + interrupts = <0 42 4>, <0 41 4>;
1191 + reg = <0x11200000 0x10000>;
1193 + interrupts = <0 34 4>;
1199 + reg = <0x11260000 0x10000>;
1201 + interrupts = <0 45 4>;
1207 + reg = <0x11500000 0x10000>, <0x11220000 0x10000>;
1209 + interrupts = <0 40 4>, <0 36 4>;
1219 + reg = <0x10030000 0x10000>;
1221 + interrupts = <0 67 4>;
1227 + reg = <0x11400000 0x30000>;
1233 + reg = <0x113b0000 0x10000>,<0x113c0000 0x10000>,<0x12010000 0x10000>;
1235 + interrupts = <0 55 4>;
1241 + reg = <0x11100000 0x10000>,<0x11110000 0x10000>;
1243 + interrupts = <0 41 4>,<0 42 4>;
1249 + reg = <0x11230000 0x10000>;
1251 + interrupts = <0 37 4>;
1257 + reg = <0x120e0000 0x1000>;
1258 + interrupts = <0 65 4>;
1259 + resets = <&clock 0x1bc 2>;
1265 + reg = <0x120f0000 0x1000>;
1266 + interrupts = <0 75 4>;
1271 + reg = <0x12080000 0x1000>;
1272 + interrupts = <0 5 4>;
1277 + reg = <0x12050000 0x1000>;
1281 + reg = <0x12070000 0x20>;
1283 + resets = <&clock 0x1bc 6>;
1287 + reg = <0x12070020 0x20>;
1289 + resets = <&clock 0x1bc 6>;
1294 …0x11240000 0x10000>,<0x11040000 0x10000>,<0x10030000 0x10000>,<0x113b0000 0x10000>,<0x113c0000 0x1…
1296 …terrupts = <0 67 4>,<0 26 4>,<0 56 4>, <0 44 4>,<0 43 4>,<0 38 4>,<0 58 4>,<0 40 4>,<0 36 4>,<0 37…
1306 @@ -0,0 +1,18 @@
1323 + memory { device_type = "memory"; reg = <0 0>; };
1330 @@ -0,0 +1,3070 @@
1337 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
1341 +CONFIG_CLANG_VERSION=0
1596 +CONFIG_HI_ZRELADDR=0x80008000
1597 +CONFIG_HI_PARAMS_PHYS=0x00000100
1598 +CONFIG_HI_INITRD_PHYS=0x00800000
1715 +CONFIG_PAGE_OFFSET=0xC0000000
1719 +CONFIG_ARCH_NR_GPIO=0
1720 +CONFIG_HZ_FIXED=0
1752 +CONFIG_ZBOOT_ROM_TEXT=0
1753 +CONFIG_ZBOOT_ROM_BSS=0
1883 +CONFIG_BASE_SMALL=0
2114 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
4297 +CONFIG_PANIC_ON_OOPS_VALUE=0
4298 +CONFIG_PANIC_TIMEOUT=0
4406 @@ -0,0 +1,3135 @@
4413 +# Compiler: arm-himix400-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
4417 +CONFIG_CLANG_VERSION=0
4699 +CONFIG_HI_ZRELADDR=0x80008000
4700 +CONFIG_HI_PARAMS_PHYS=0x00000100
4701 +CONFIG_HI_INITRD_PHYS=0x00800000
4818 +CONFIG_PAGE_OFFSET=0xC0000000
4822 +CONFIG_ARCH_NR_GPIO=0
4823 +CONFIG_HZ_FIXED=0
4855 +CONFIG_ZBOOT_ROM_TEXT=0
4856 +CONFIG_ZBOOT_ROM_BSS=0
4987 +CONFIG_BASE_SMALL=0
5220 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
7460 +CONFIG_PANIC_ON_OOPS_VALUE=0
7461 +CONFIG_PANIC_TIMEOUT=0
7547 @@ -0,0 +1,3189 @@
7554 +# Compiler: arm-himix410-linux-gcc (HC&C V1R3C00SPC200B041_20200707) 7.3.0
7558 +CONFIG_CLANG_VERSION=0
7813 +CONFIG_HI_ZRELADDR=0x80008000
7814 +CONFIG_HI_PARAMS_PHYS=0x00000100
7815 +CONFIG_HI_INITRD_PHYS=0x00800000
7932 +CONFIG_PAGE_OFFSET=0xC0000000
7936 +CONFIG_ARCH_NR_GPIO=0
7937 +CONFIG_HZ_FIXED=0
7969 +CONFIG_ZBOOT_ROM_TEXT=0
7970 +CONFIG_ZBOOT_ROM_BSS=0
8100 +CONFIG_BASE_SMALL=0
8331 +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0
10238 +CONFIG_JFFS2_FS_DEBUG=0
10633 +CONFIG_PANIC_ON_OOPS_VALUE=0
10634 +CONFIG_PANIC_TIMEOUT=0
10802 + return 0;
10819 @@ -0,0 +1,269 @@
11046 + default "0x32008000" if ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3568V100
11047 + default "0x82008000" if ARCH_HI3516CV500 || ARCH_HI3516DV300 || ARCH_HI3556V200 || ARCH_HI3559V20…
11048 + default "0x42008000" if ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI3516DV…
11051 + default "0x40008000" if ARCH_HI3521DV200
11052 + default "0x40008000" if ARCH_HI3520DV500
11053 + default "0x80008000" if ARCH_HI3516CV500
11054 + default "0x80008000" if ARCH_HI3516DV300
11055 + default "0x80008000" if ARCH_HI3556V200
11056 + default "0x80008000" if ARCH_HI3559V200
11057 + default "0x80008000" if ARCH_HI3562V100
11058 + default "0x80008000" if ARCH_HI3566V100
11059 + default "0x80008000" if ARCH_HI3516A
11060 + default "0x80008000" if ARCH_HI3518EV20X
11061 + default "0x80008000" if ARCH_HI3536DV100
11062 + default "0x80008000" if ARCH_HI3521A
11063 + default "0x40008000" if ARCH_HI3531A
11064 + default "0x40008000" if ARCH_HI3516EV200 || ARCH_HI3516EV300 || ARCH_HI3518EV300 || ARCH_HI…
11065 + default "0x22008000" if ARCH_HI3556AV100 || ARCH_HI3519AV100 || ARCH_HI3568V100
11069 + default "0x00000100"
11073 + default "0x00800000"
11094 @@ -0,0 +1,34 @@
11134 @@ -0,0 +1,7 @@
11147 @@ -0,0 +1,26 @@
11152 + * phy: 0x20000000 ~ 0x20700000
11153 + * vir: 0xFE100000 ~ 0xFE800000
11155 +#define HI3516DV300_IOCH2_PHYS 0x20000000
11156 +#define IO_OFFSET_HIGH 0xDE100000
11158 +#define HI3516DV300_IOCH2_SIZE 0x700000
11160 +/* phy: 0x10000000 ~ 0x100E0000
11161 + * vir: 0xFE000000 ~ 0xFE0E0000
11163 +#define HI3516DV300_IOCH1_PHYS 0x10000000
11164 +#define IO_OFFSET_LOW 0xEE000000
11166 +#define HI3516DV300_IOCH1_SIZE 0xE0000
11179 @@ -0,0 +1,4 @@
11189 @@ -0,0 +1,52 @@
11247 @@ -0,0 +1,52 @@
11305 @@ -0,0 +1,9 @@
11320 @@ -0,0 +1,68 @@
11346 +#define REG_CPU_SRST_CRG 0x78
11362 + crg_base = of_iomap(np, 0);
11394 @@ -0,0 +1,62 @@
11411 +#define HI35XX_BOOT_ADDRESS 0x00000000
11415 + unsigned long base = 0;
11441 + writel_relaxed(0xe51ff004, virt); /* ldr pc, [rc, #-4] */
11454 + return 0;
11462 @@ -0,0 +1,340 @@
11486 + round_up((0x80000 + sizeof(struct fault_log_info)), SIZE_1K)
11518 + size_t stack_len = 0;
11519 + size_t com_len = 0;
11528 + memset(pbuf, 0, buf_size);
11529 + memset(tmp_buf, 0, sizeof(tmp_buf));
11530 + nr_entries = stack_trace_save(entries, ARRAY_SIZE(entries), 0);
11533 + for (i = 0; i < nr_entries; i++) {
11535 + tmp_buf[sizeof(tmp_buf) - 1] = '\0';
11541 + if (strncmp(tmp_buf, "panic", strlen("panic")) == 0)
11544 + (void)memset(tmp_buf, 0, sizeof(tmp_buf));
11551 + *(pbuf + buf_size - 1) = '\0';
11566 + memset(path, 0, sizeof(path));
11573 + (size_t)pinfo->len), 0);
11575 + memset(kernel_log, 0, KERNEL_LOG_MAX_SIZE);
11580 + if (ret == 0)
11598 + if (down_trylock(&kmsg_sem) != 0) {
11618 + save_kmsg_from_buffer(log_dir, KERNEL_LOG_NAME, 0);
11639 + unsigned int i = 0;
11644 + if (storage_lastword->get_log((void *)kernel_log, log_size) < 0) {
11652 + for (i = 0; i < strlen((*info).event); i++)
11655 + if (strncmp((*info).module, "PSTORE", strlen("PSTORE")) == 0)
11659 + return 0;
11689 + memset(error_desc, 0, sizeof(error_desc));
11698 + bbox_notify_error(EVENT_POWEROFF, MODULE_SYSTEM, error_desc, 0);
11715 + memset(error_desc, 0, sizeof(error_desc));
11732 + if (bbox_register_module_ops(&ops) != 0) {
11737 + bbox_notify_error("EVENT_TEST", "TEST", "Test bbox_notify_error", 0);
11754 + if (bbox_register_module_ops(&ops) != 0) {
11771 + memset(dumper, 0, sizeof(*dumper));
11775 + if (ret != 0) {
11785 + return 0;
11808 @@ -0,0 +1,339 @@
11832 + round_up((0x80000 + sizeof(struct fault_log_info)), SIZE_1K)
11864 + size_t stack_len = 0;
11865 + size_t com_len = 0;
11874 + memset(pbuf, 0, buf_size);
11875 + memset(tmp_buf, 0, sizeof(tmp_buf));
11876 + nr_entries = stack_trace_save(entries, ARRAY_SIZE(entries), 0);
11879 + for (i = 0; i < nr_entries; i++) {
11881 + tmp_buf[sizeof(tmp_buf) - 1] = '\0';
11887 + if (strncmp(tmp_buf, "panic", strlen("panic")) == 0)
11890 + (void)memset(tmp_buf, 0, sizeof(tmp_buf));
11897 + *(pbuf + buf_size - 1) = '\0';
11912 + memset(path, 0, sizeof(path));
11919 + (size_t)pinfo->len), 0);
11921 + memset(kernel_log, 0, KERNEL_LOG_MAX_SIZE);
11926 + if (ret == 0)
11944 + if (down_trylock(&kmsg_sem) != 0) {
11964 + save_kmsg_from_buffer(log_dir, KERNEL_LOG_NAME, 0);
11989 + if (storage_lastword->get_log((void *)kernel_log, log_size) < 0) {
11999 + return 0;
12029 + memset(error_desc, 0, sizeof(error_desc));
12038 + bbox_notify_error(EVENT_POWEROFF, MODULE_SYSTEM, error_desc, 0);
12055 + memset(error_desc, 0, sizeof(error_desc));
12072 + if (bbox_register_module_ops(&ops) != 0) {
12077 + bbox_notify_error("EVENT_TEST", "TEST", "Test bbox_notify_error", 0);
12094 + if (bbox_register_module_ops(&ops) != 0) {
12106 + if (storage_lastword->storage_log(kernel_log, KERNEL_LOG_MAX_SIZE) < 0) {
12116 + memset(dumper, 0, sizeof(*dumper));
12120 + if (ret != 0) {
12130 + return 0;
12298 return 0;
12307 + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
12309 + return 0;
12401 @@ -0,0 +1,44 @@
12414 + default "0x10390000" if (ARCH_HI3531DV200 || ARCH_HI3535AV100)
12415 + default "0x10390000" if (ARCH_HI3521DV200 || ARCH_HI3520DV500)
12422 + range 0 1
12431 + range 0 1
12477 +#define PCI_AHCI 0
12533 @@ -0,0 +1,174 @@
12564 + for (ix = 0; ix < size; ix += 0x04, addr++) {
12565 + if (!(ix & 0x0F))
12586 + for (ix = 0; ix <= 0x28; ix += 0x04) {
12587 + if (!(ix & 0x0F))
12592 + regbase = CONFIG_HISI_SATA_IOBASE + 0x0100;
12593 + pr_debug("AHCI PORT 0 Register dump:");
12594 + for (ix = 0; ix <= 0x7F; ix += 0x04) {
12595 + if (!(ix & 0x0F))
12626 + pr_debug("flags:0x%08lX, protocol:0x%02X, command:0x%02X, device:0x%02X, ctl:0x%02X\n",
12628 + pr_debug("feature:0x%08X, nsect:0x%02X, lbal:0x%02X, lbam:0x%02X, lbah:0x%02X\n",
12630 + pr_debug("hob_feature:0x%08X, hob_nsect:0x%02X, hob_lbal:0x%02X, hob_lbam:0x%02X, hob_lbah:0x%02X…
12645 + for (i = 0; i < 16; i++) {
12660 + tmp = readl(port_base + 0x58);
12661 + pr_debug("txdmac_curr_st:0x%2x\n", (tmp >> 24) & 0xf);
12662 + tmp = readl(port_base + 0x64);
12663 + pr_debug("rxdmac_curr_st:0x%2x\n", (tmp >> 24) & 0xf);
12664 + tmp = readl(port_base + 0x70);
12665 + pr_debug("dmac tx fifo:count-0x%x-empty-%x-ful-%x\n",
12666 + (tmp >> 0) & 0xff,
12667 + (tmp >> 16) & 0x1, (tmp >> 17) & 0x1);
12668 + pr_debug("dmac rx fifo:count-0x%x-empty-%x-ful-%x\n",
12669 + (tmp >> 8) & 0xff,
12670 + (tmp >> 18) & 0x1, (tmp >> 19) & 0x1);
12674 + tmp = readl(port_base + 0x50);
12675 + pr_debug("pxxx_curr_st:0x%2x ndrx_curr_st:0x%2x\n",
12676 + (tmp >> 24) & 0xf,
12677 + (tmp >> 16) & 0xff);
12678 + pr_debug("cfis_curr_st:0x%2x piox_curr_st:0x%2x\n",
12679 + (tmp >> 12) & 0xf,
12680 + (tmp >> 8) & 0xf);
12681 + pr_debug("pmxx_curr_st:0x%2x errx_curr_st:0x%2x\n",
12682 + (tmp >> 4) & 0xf,
12683 + (tmp >> 0) & 0xf);
12687 + tmp = readl(port_base + 0x54);
12688 + pr_debug("link_curr_st:0x%2x\n", (tmp >> 24) & 0x1f);
12689 + pr_debug("link tx fifo:count-0x%x-empty-%x-ful-%x\n",
12690 + (tmp >> 0) & 0x1f,
12691 + (tmp >> 5) & 0x1, (tmp >> 6) & 0x1);
12692 + pr_debug("link rx fifo:count-0x%x-empty-%x-ful-%x\n",
12693 + (tmp >> 8) & 0x1f,
12694 + (tmp >> 13) & 0x1, (tmp >> 14) & 0x1);
12695 + pr_debug("link df fifo:count-0x%x-empty-%x-ful-%x\n\n",
12696 + (tmp >> 16) & 0x1f,
12697 + (tmp >> 21) & 0x1, (tmp >> 22) & 0x1);
12700 + tmp = readl(port_base + 0x0);
12702 + __hisi_ahci_st_md(phys_to_virt(tmp + 0x100));
12703 + __hisi_ahci_st_md(phys_to_virt(tmp + 0x200));
12704 + __hisi_ahci_st_md(phys_to_virt(tmp + 0x300));
12713 @@ -0,0 +1,58 @@
12751 +} while (0)
12755 + pr_debug("HI_AHCI(REG) %s:%d: readl(0x%08X) = 0x%08X\n", \
12758 + } while (0)
12761 + pr_debug("HI_AHCI(REG) %s:%d: writel(0x%08X) = 0x%08X\n", \
12764 + } while (0)
12784 @@ -42,6 +43,33 @@ MODULE_PARM_DESC(skip_host_reset, "skip global host reset (0=don't skip, 1=skip)
12786 MODULE_PARM_DESC(ignore_sss, "Ignore staggered spinup flag (0=don't ignore, 1=ignore)");
12851 + fbs_ctrl[port_num].fbs_enable_flag = 0;
12852 + fbs_ctrl[port_num].fbs_disable_flag = 0;
12853 + fbs_ctrl[port_num].fbs_cmd_issue_flag = 0;
12891 + cmd_timeout_count = 0;
12910 + ap->nr_active_links = 0;
12912 + fbs_ctrl[port_num].fbs_enable_flag = 0;
12913 + fbs_ctrl[ap->port_no].fbs_cmd_issue_flag = 0;
12917 + cmd_timeout_count = 0;
12932 + fbs_ctrl[port_num].fbs_enable_flag = 0;
12933 + fbs_ctrl[port_num].fbs_disable_flag = 0;
13024 + fbs_ctrl[port_num].fbs_disable_flag = 0;
13052 + fbs_ctrl[ap->port_no].fbs_enable_flag = 0;
13053 + fbs_ctrl[ap->port_no].fbs_disable_flag = 0;
13054 + fbs_ctrl[ap->port_no].fbs_cmd_issue_flag = 0;
13057 + timer_setup(&fbs_ctrl[ap->port_no].poll_timer, ahci_poll_timerout, 0);
13072 for (unit = 0, cd = pcd; unit < PCD_UNITS; unit++, cd++) {
13327 @@ -0,0 +1,271 @@
13356 + { HI3516DV300_FIXED_3M, "3m", NULL, 0, 3000000, },
13357 + { HI3516DV300_FIXED_6M, "6m", NULL, 0, 6000000, },
13358 + { HI3516DV300_FIXED_12M, "12m", NULL, 0, 12000000, },
13359 + { HI3516DV300_FIXED_24M, "24m", NULL, 0, 24000000, },
13360 + { HI3516DV300_FIXED_25M, "25m", NULL, 0, 25000000, },
13361 + { HI3516DV300_FIXED_50M, "50m", NULL, 0, 50000000, },
13362 + { HI3516DV300_FIXED_54M, "54m", NULL, 0, 54000000, },
13363 + { HI3516DV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
13364 + { HI3516DV300_FIXED_100M, "100m", NULL, 0, 100000000, },
13365 + { HI3516DV300_FIXED_125M, "125m", NULL, 0, 125000000, },
13366 + { HI3516DV300_FIXED_150M, "150m", NULL, 0, 150000000, },
13367 + { HI3516DV300_FIXED_163M, "163m", NULL, 0, 163000000, },
13368 + { HI3516DV300_FIXED_200M, "200m", NULL, 0, 200000000, },
13369 + { HI3516DV300_FIXED_250M, "250m", NULL, 0, 250000000, },
13370 + { HI3516DV300_FIXED_257M, "257m", NULL, 0, 257000000, },
13371 + { HI3516DV300_FIXED_300M, "300m", NULL, 0, 300000000, },
13372 + { HI3516DV300_FIXED_324M, "324m", NULL, 0, 324000000, },
13373 + { HI3516DV300_FIXED_342M, "342m", NULL, 0, 342000000, },
13374 + { HI3516DV300_FIXED_342M, "375m", NULL, 0, 375000000, },
13375 + { HI3516DV300_FIXED_396M, "396m", NULL, 0, 396000000, },
13376 + { HI3516DV300_FIXED_400M, "400m", NULL, 0, 400000000, },
13377 + { HI3516DV300_FIXED_448M, "448m", NULL, 0, 448000000, },
13378 + { HI3516DV300_FIXED_500M, "500m", NULL, 0, 500000000, },
13379 + { HI3516DV300_FIXED_540M, "540m", NULL, 0, 540000000, },
13380 + { HI3516DV300_FIXED_600M, "600m", NULL, 0, 600000000, },
13381 + { HI3516DV300_FIXED_750M, "750m", NULL, 0, 750000000, },
13382 + { HI3516DV300_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
13383 + { HI3516DV300_FIXED_1500M, "1500m", NULL, 0, 1500000000UL, },
13396 +static u32 sysaxi_mux_table[] = {0, 1, 2};
13397 +static u32 sysapb_mux_table[] = {0, 1};
13398 +static u32 uart_mux_table[] = {0, 1};
13399 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
13400 +static u32 eth_mux_table[] = {0, 1};
13402 +static u32 pwm_mux_table[] = {0, 1, 2, 3};
13408 + CLK_SET_RATE_PARENT, 0x80, 6, 2, 0, sysaxi_mux_table,
13413 + CLK_SET_RATE_PARENT, 0x80, 10, 1, 0, sysapb_mux_table,
13417 + CLK_SET_RATE_PARENT, 0x144, 2, 3, 0, fmc_mux_table,
13421 + CLK_SET_RATE_PARENT, 0x148, 2, 2, 0, mmc_mux_table,
13425 + CLK_SET_RATE_PARENT, 0x160, 2, 2, 0, mmc_mux_table,
13429 + CLK_SET_RATE_PARENT, 0x154, 2, 2, 0, mmc_mux_table,
13434 + CLK_SET_RATE_PARENT, 0x1bc, 18, 1, 0, uart_mux_table,
13439 + CLK_SET_RATE_PARENT, 0x1bc, 19, 1, 0, uart_mux_table,
13444 + CLK_SET_RATE_PARENT, 0x1bc, 20, 1, 0, uart_mux_table,
13449 + CLK_SET_RATE_PARENT, 0x1bc, 21, 1, 0, uart_mux_table,
13454 + CLK_SET_RATE_PARENT, 0x1bc, 22, 1, 0, uart_mux_table,
13459 + CLK_SET_RATE_PARENT, 0x1bc, 8, 2, 0, pwm_mux_table,
13464 + CLK_SET_RATE_PARENT, 0x16c, 7, 1, 0, eth_mux_table,
13479 + CLK_SET_RATE_PARENT, 0x144, 1, 0,
13483 + CLK_SET_RATE_PARENT, 0x148, 1, 0,
13487 + CLK_SET_RATE_PARENT, 0x160, 1, 0,
13491 + CLK_SET_RATE_PARENT, 0x154, 1, 0,
13495 + CLK_SET_RATE_PARENT, 0x1b8, 0, 0,
13499 + CLK_SET_RATE_PARENT, 0x1b8, 1, 0,
13503 + CLK_SET_RATE_PARENT, 0x1b8, 2, 0,
13507 + CLK_SET_RATE_PARENT, 0x1b8, 3, 0,
13511 + CLK_SET_RATE_PARENT, 0x1b8, 4, 0,
13515 + CLK_SET_RATE_PARENT, 0x1b8, 11, 0,
13519 + CLK_SET_RATE_PARENT, 0x1b8, 12, 0,
13523 + CLK_SET_RATE_PARENT, 0x1b8, 13, 0,
13527 + CLK_SET_RATE_PARENT, 0x1b8, 14, 0,
13531 + CLK_SET_RATE_PARENT, 0x1b8, 15, 0,
13535 + CLK_SET_RATE_PARENT, 0x1b8, 16, 0,
13539 + CLK_SET_RATE_PARENT, 0x1b8, 17, 0,
13543 + CLK_SET_RATE_PARENT, 0x1b8, 18, 0,
13547 + CLK_SET_RATE_PARENT, 0x1bc, 12, 0,
13551 + CLK_SET_RATE_PARENT, 0x1bc, 13, 0,
13555 + CLK_SET_RATE_PARENT, 0x1bc, 14, 0,
13559 + CLK_SET_RATE_PARENT, 0x16c, 1, 0,
13563 + CLK_SET_RATE_PARENT, 0x194, 1, 0,
13567 + CLK_SET_RATE_PARENT, 0x194, 2, 0,
13571 + CLK_SET_RATE_PARENT, 0x1bc, 7, 0,
13604 @@ -0,0 +1,559 @@
13669 + HI3519AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
13670 + 0x4, 0, 12, 12, 6
13678 + { HI3519AV100_FIXED_2376M, "2376m", NULL, 0, 2376000000UL, },
13679 + { HI3519AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
13680 + { HI3519AV100_FIXED_594M, "594m", NULL, 0, 594000000, },
13681 + { HI3519AV100_FIXED_297M, "297m", NULL, 0, 297000000, },
13682 + { HI3519AV100_FIXED_148P5M, "148p5m", NULL, 0, 148500000, },
13683 + { HI3519AV100_FIXED_74P25M, "74p25m", NULL, 0, 74250000, },
13684 + { HI3519AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
13685 + { HI3519AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
13686 + { HI3519AV100_FIXED_340M, "340m", NULL, 0, 340000000, },
13687 + { HI3519AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
13688 + { HI3519AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
13689 + { HI3519AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
13690 + { HI3519AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
13691 + { HI3519AV100_FIXED_27M, "27m", NULL, 0, 1188000000, },
13692 + { HI3519AV100_FIXED_37P125M, "37p125m", NULL, 0, 37125000, },
13693 + { HI3519AV100_FIXED_3000M, "3000m", NULL, 0, 3000000000UL, },
13694 + { HI3519AV100_FIXED_1500M, "1500m", NULL, 0, 1500000000, },
13695 + { HI3519AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
13696 + { HI3519AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
13697 + { HI3519AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
13698 + { HI3519AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
13699 + { HI3519AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
13700 + { HI3519AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
13701 + { HI3519AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
13702 + { HI3519AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
13703 + { HI3519AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
13704 + { HI3519AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
13705 + { HI3519AV100_FIXED_214M, "214m", NULL, 0, 214000000, },
13706 + { HI3519AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
13707 + { HI3519AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
13708 + { HI3519AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
13709 + { HI3519AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
13710 + { HI3519AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
13711 + { HI3519AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
13712 + { HI3519AV100_FIXED_100K, "100k", NULL, 0, 100000, },
13713 + { HI3519AV100_FIXED_400K, "400k", NULL, 0, 400000, },
13714 + { HI3519AV100_FIXED_49P5M, "49p5m", NULL, 0, 49500000, },
13715 + { HI3519AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
13716 + { HI3519AV100_FIXED_187P5M, "187p5m", NULL, 0, 187500000, },
13717 + { HI3519AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
13724 +static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6};
13729 +static u32 mmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
13734 +static u32 sysapb_mux_table[] = {0, 1};
13739 +static u32 sysbus_mux_table[] = {0, 1};
13742 +static u32 uart_mux_table[] = {0, 1, 2};
13747 +static u32 a53_1_clksel_mux_table[] = {0, 1, 2, 3};
13752 + CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
13757 + CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
13762 + CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
13767 + CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
13772 + CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
13777 + CLK_SET_RATE_PARENT, 0xe8, 0, 1, 1, sysbus_mux_table
13782 + CLK_SET_RATE_PARENT, 0x1a4, 0, 2, 1, uart_mux_table
13787 + CLK_SET_RATE_PARENT, 0x1a4, 2, 2, 1, uart_mux_table
13792 + CLK_SET_RATE_PARENT, 0x1a4, 4, 2, 1, uart_mux_table
13797 + CLK_SET_RATE_PARENT, 0x1a4, 6, 2, 1, uart_mux_table
13802 + CLK_SET_RATE_PARENT, 0x1a4, 8, 2, 1, uart_mux_table
13807 + CLK_SET_RATE_PARENT, 0x1a4, 10, 2, 1, uart_mux_table
13812 + CLK_SET_RATE_PARENT, 0x1a4, 12, 2, 1, uart_mux_table
13817 + CLK_SET_RATE_PARENT, 0x1a4, 14, 2, 1, uart_mux_table
13822 + CLK_SET_RATE_PARENT, 0x1a4, 28, 2, 1, uart_mux_table
13827 + CLK_SET_RATE_PARENT, 0xe4, 10, 2, 3, a53_1_clksel_mux_table
13840 + CLK_SET_RATE_PARENT, 0x170, 1, 0,
13844 + CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
13848 + CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
13852 + CLK_SET_RATE_PARENT, 0x214, 28, 0,
13856 + CLK_SET_RATE_PARENT, 0x198, 16, 0,
13860 + CLK_SET_RATE_PARENT, 0x198, 17, 0,
13864 + CLK_SET_RATE_PARENT, 0x198, 18, 0,
13868 + CLK_SET_RATE_PARENT, 0x198, 19, 0,
13872 + CLK_SET_RATE_PARENT, 0x198, 20, 0,
13876 + CLK_SET_RATE_PARENT, 0x198, 21, 0,
13880 + CLK_SET_RATE_PARENT, 0x198, 22, 0,
13884 + CLK_SET_RATE_PARENT, 0x198, 23, 0,
13888 + CLK_SET_RATE_PARENT, 0x198, 29, 0,
13892 + CLK_SET_RATE_PARENT, 0x0174, 1, 0,
13896 + CLK_SET_RATE_PARENT, 0x0174, 5, 0,
13901 + CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
13905 + CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
13909 + CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
13913 + CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
13917 + CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
13921 + CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
13925 + CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
13929 + CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
13933 + CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
13937 + CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
13941 + CLK_SET_RATE_PARENT, 0x0198, 24, 0,
13945 + CLK_SET_RATE_PARENT, 0x0198, 25, 0,
13949 + CLK_SET_RATE_PARENT, 0x0198, 26, 0,
13953 + CLK_SET_RATE_PARENT, 0x0198, 27, 0,
13957 + CLK_SET_RATE_PARENT, 0x0198, 28, 0,
13961 + CLK_SET_RATE_PARENT, 0x16c, 6, 0,
13965 + CLK_SET_RATE_PARENT, 0x16c, 5, 0,
13969 + CLK_SET_RATE_PARENT, 0x16c, 9, 0,
13973 + CLK_SET_RATE_PARENT, 0x16c, 8, 0,
13977 + CLK_SET_RATE_PARENT, 0x14c, 5, 0,
13989 + *frac_val = 0;
14010 + postdiv1_val = postdiv2_val = 0;
14033 + return 0;
14061 + rate = 0;
14064 + return 0;
14095 + for (i = 0; i < nums; i++) {
14108 + init.num_parents = (clks[i].parent_name ? 1 : 0);
14223 + rstc->membase = of_iomap(np, 0);
14311 #define arch_timer_check_ool_workaround(t,a) do { } while(0)
14323 @@ -0,0 +1,356 @@
14359 +#define TIMER_LOAD 0x00 /* ACVR rw */
14360 +#define TIMER_VALUE 0x04 /* ACVR ro */
14361 +#define TIMER_CTRL 0x08 /* ACVR rw */
14362 +#define TIMER_CTRL_ONESHOT (1 << 0) /* CVR */
14364 +#define TIMER_CTRL_DIV1 (0 << 2) /* ACVR */
14371 +#define TIMER_INTCLR 0x0c /* ACVR wo */
14372 +#define TIMER_RIS 0x10 /* CVR ro */
14373 +#define TIMER_MIS 0x14 /* CVR ro */
14374 +#define TIMER_BGLOAD 0x18 /* CVR rw */
14376 +#define CPU_TASKS_FROZEN 0x0010
14406 + writel(0, base + TIMER_CTRL);
14407 + writel(0xffffffff, base + TIMER_LOAD);
14408 + writel(0xffffffff, base + TIMER_VALUE);
14451 + writel(0, hiclkevt->base + TIMER_CTRL);
14453 + return 0;
14473 + return 0;
14492 + return 0;
14512 + writel(0, hiclkevt->base + TIMER_CTRL);
14518 + clockevents_config_and_register(clkevt, hiclkevt->rate, 0xf,
14519 + 0x7fffffff);
14521 + return 0;
14609 + clk1 = of_clk_get(node, 0);
14639 + for (ix = 0; ix < nr_cpus; ix++) {
14644 + while (--ix >= 0)
14653 + base = of_iomap(node, 0);
14655 + pr_err("can't iomap timer %d\n", 0);
14667 + return 0;
14672 + for (ix = 0; ix < nr_irqs; ix++)
14732 @@ -0,0 +1,1443 @@
14867 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "lli num = 0%d\n", num);
14868 + for (i = 0; i < num; i++) {
14869 + printk("lli%d:lli_L: 0x%llx\n", i, plli[i].next_lli & 0xffffffff);
14870 + printk("lli%d:lli_H: 0x%llx\n", i, (plli[i].next_lli >> BITS_PER_HALF_WORD) & 0xffffffff);
14871 + printk("lli%d:count: 0x%x\n", i, plli[i].count);
14872 + printk("lli%d:src_addr_L: 0x%llx\n", i, plli[i].src_addr & 0xffffffff);
14873 + printk("lli%d:src_addr_H: 0x%llx\n", i, (plli[i].src_addr >> BITS_PER_HALF_WORD) & 0xffffffff);
14874 + printk("lli%d:dst_addr_L: 0x%llx\n", i, plli[i].dest_addr & 0xffffffff);
14875 + printk("lli%d:dst_addr_H: 0x%llx\n", i, (plli[i].dest_addr >> BITS_PER_HALF_WORD) & 0xffffffff);
14876 + printk("lli%d:CONFIG: 0x%x\n", i, plli[i].config);
14919 + unsigned int reg = 0;
14920 + unsigned int offset = 0;
14932 + request_num = dma_spec->args[0];
14941 + reg = 0xc0;
14944 + offset = hiedmac->misc_ctrl_base + (request_num & (~0x3));
14947 + reg &= ~(0x3f << ((request_num & 0x3) << 3));
14948 + reg |= signal << ((request_num & 0x3) << 3);
14953 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "offset = 0x%x, reg = 0x%x\n", offset, reg);
14981 + hiedmac->irq = platform_get_irq(platdev, 0);
14982 + if (unlikely(hiedmac->irq < 0))
14989 + res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
14998 + return 0;
15009 + hiedmac->misc_regmap = 0;
15038 + return 0;
15079 + phychan->id)) & 0xffffffff) << BITS_PER_HALF_WORD);
15082 + if (next_lli != 0) {
15087 + for (i = 0; i < index; i++)
15143 + for (i = 0; i < hiedmac->channels; i++) {
15169 + if (plli->next_lli != 0x0)
15170 + hiedmacv310_writel((plli->next_lli & 0xffffffff) | HIEDMAC_LLI_ENABLE,
15173 + hiedmacv310_writel((plli->next_lli & 0xffffffff),
15176 + hiedmacv310_writel(((plli->next_lli >> 32) & 0xffffffff),
15179 + hiedmacv310_writel(plli->src_addr & 0xffffffff,
15181 + hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff,
15183 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
15185 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
15202 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, " HIEDMAC_Cx_CONFIG = 0x%x\n", val);
15250 + return 0;
15264 + for (timeout = 2000; timeout > 0; timeout--) {
15265 + if (!((0x1 << phychan->id) & hiedmacv310_readl(hiedmac->base + HIEDMAC_CH_STAT)))
15270 + if (timeout == 0)
15283 + return 0;
15288 + return 0;
15310 + return 0;
15317 + return 0;
15330 + return 0;
15344 + return 0;
15360 + return ~0;
15376 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "addr_width = 0x%x\n", addr_width);
15378 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "width = 0x%x\n", width);
15381 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, "tsf_desc->ccfg = 0x%x\n", config);
15382 + hiedmacv310_trace(HIEDMACV310_CONFIG_TRACE_LEVEL, "burst = 0x%x\n", burst);
15385 + if (signal >= 0) {
15399 + unsigned int burst = 0;
15400 + unsigned int addr_width = 0;
15401 + unsigned int maxburst = 0;
15421 + else if (maxburst == 0)
15428 + hiedmacv310_trace(HIEDMACV310_REG_TRACE_LEVEL, "tsf_desc->ccfg = 0x%x\n", tsf_desc->ccfg);
15444 + memset(&plli[num], 0x0, sizeof(*plli));
15452 + if (num > 0) {
15457 + return 0;
15477 + if (len == 0) {
15478 + hiedmacv310_error("Transfer length is 0. \n");
15493 + return 0;
15501 + dma_addr_t src = 0;
15502 + dma_addr_t dst = 0;
15554 + size_t count_in_sg = 0;
15564 + return 0;
15581 + while (dsg->len != 0) {
15596 + return 0;
15604 + unsigned int lli_count = 0;
15620 + last_plli->next_lli = 0;
15623 + return 0;
15634 + dma_addr_t slave_addr = 0;
15677 + u32 config = 0;
15698 + /* max burst width is 16 ,but reg value set 0xf */
15729 + dma_addr_t slave_addr = 0;
15777 + val = 0x1 << phychan->id;
15829 + return 0;
15834 + channel_tc_status = (channel_tc_status >> chan_id) & 0x01;
15839 + channel_tc_status = (channel_tc_status >> chan_id) & 0x01;
15842 + channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
15845 + if ((channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) & (1 << chan_id)) {
15846 + hiedmacv310_error("Error in hiedmac %d!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n",
15847 + chan_id, channel_err_status[0],
15876 + u32 mask = 0;
15881 + hiedmacv310_error("channel_status = 0x%x\n", channel_status);
15885 + for (i = 0; i < hiedmac->channels; i++) {
15886 + temp = (channel_status >> i) & 0x1;
15915 + for (i = 0; i < channels; i++) {
15933 + return 0;
15990 + for (i = 0; i < hiedmac->channels; i++) {
16011 + return 0;
16079 + trasfer_size, EDMACV300_POOL_ALIGN, 0);
16115 + ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
16132 + return 0;
16145 + int err = 0;
16181 @@ -0,0 +1,153 @@
16208 +#define HIEDMACV310_TRACE_LEVEL 0
16219 +} while (0)
16229 +} while (0)
16235 +} while (0)
16248 +} while (0)
16251 +#define MAX_TRANSFER_BYTES 0xffff
16254 +#define HIEDMAC_INT_STAT 0x0
16255 +#define HIEDMAC_INT_TC1 0x4
16256 +#define HIEDMAC_INT_TC2 0x8
16257 +#define HIEDMAC_INT_ERR1 0xc
16258 +#define HIEDMAC_INT_ERR2 0x10
16259 +#define HIEDMAC_INT_ERR3 0x14
16261 +#define HIEDMAC_INT_TC1_MASK 0x18
16262 +#define HIEDMAC_INT_TC2_MASK 0x1c
16263 +#define HIEDMAC_INT_ERR1_MASK 0x20
16264 +#define HIEDMAC_INT_ERR2_MASK 0x24
16265 +#define HIEDMAC_INT_ERR3_MASK 0x28
16267 +#define HIEDMAC_INT_TC1_RAW 0x600
16268 +#define HIEDMAC_INT_TC2_RAW 0x608
16269 +#define HIEDMAC_INT_ERR1_RAW 0x610
16270 +#define HIEDMAC_INT_ERR2_RAW 0x618
16271 +#define HIEDMAC_INT_ERR3_RAW 0x620
16273 +#define hiedmac_cx_curr_cnt0(cn) (0x404 + (cn) * 0x20)
16274 +#define hiedmac_cx_curr_src_addr_l(cn) (0x408 + (cn) * 0x20)
16275 +#define hiedmac_cx_curr_src_addr_h(cn) (0x40c + (cn) * 0x20)
16276 +#define hiedmac_cx_curr_dest_addr_l(cn) (0x410 + (cn) * 0x20)
16277 +#define hiedmac_cx_curr_dest_addr_h(cn) (0x414 + (cn) * 0x20)
16279 +#define HIEDMAC_CH_PRI 0x688
16280 +#define HIEDMAC_CH_STAT 0x690
16281 +#define HIEDMAC_DMA_CTRL 0x698
16283 +#define hiedmac_cx_base(cn) (0x800 + (cn) * 0x40)
16284 +#define hiedmac_cx_lli_l(cn) (0x800 + (cn) * 0x40)
16285 +#define hiedmac_cx_lli_h(cn) (0x804 + (cn) * 0x40)
16286 +#define hiedmac_cx_cnt0(cn) (0x81c + (cn) * 0x40)
16287 +#define hiedmac_cx_src_addr_l(cn) (0x820 + (cn) * 0x40)
16288 +#define hiedmac_cx_src_addr_h(cn) (0x824 + (cn) * 0x40)
16289 +#define hiedmac_cx_dest_addr_l(cn) (0x828 + (cn) * 0x40)
16290 +#define hiedmac_cx_dest_addr_h(cn) (0x82c + (cn) * 0x40)
16291 +#define hiedmac_cx_config(cn) (0x830 + (cn) * 0x40)
16293 +#define HIEDMAC_ALL_CHAN_CLR 0xff
16294 +#define HIEDMAC_INT_ENABLE_ALL_CHAN 0xff
16302 +#define HIEDMAC_WIDTH_8BIT 0b0
16303 +#define HIEDMAC_WIDTH_16BIT 0b1
16304 +#define HIEDMAC_WIDTH_32BIT 0b10
16305 +#define HIEDMAC_WIDTH_64BIT 0b11
16317 +#define HIEDMAC_LLI_ALIGN 0x40
16318 +#define HIEDMAC_LLI_DISABLE 0x0
16319 +#define HIEDMAC_LLI_ENABLE 0x2
16321 +#define HIEDMAC_CXCONFIG_SIGNAL_SHIFT 0x4
16322 +#define HIEDMAC_CXCONFIG_MEM_TYPE 0x0
16323 +#define HIEDMAC_CXCONFIG_DEV_MEM_TYPE 0x1
16324 +#define HIEDMAC_CXCONFIG_TSF_TYPE_SHIFT 0x2
16325 +#define HIEDMAC_CXCONFIG_LLI_START 0x1
16327 +#define HIEDMAC_CXCONFIG_ITC_EN 0x1
16328 +#define HIEDMAC_CXCONFIG_ITC_EN_SHIFT 0x1
16330 +#define CCFG_EN 0x1
16356 + if (gpio_idx < 0)
16361 + if (pl061->gc.base < 0)
16393 @@ -0,0 +1,8 @@
16407 @@ -0,0 +1,27 @@
16440 @@ -0,0 +1,91 @@
16453 + OUTPUT_USER = 0, /* User timing */
16537 @@ -0,0 +1,777 @@
16572 + unsigned int status; /* 0: closed, 1: opened */
16583 + unsigned int status; /* 0: closed, 1: opened */
16637 + cap->layer_cap[DRM_HAL_GFX_G0].formats[0] = DRM_HAL_FMT_ARGB8888;
16640 + cap->layer_cap[DRM_HAL_GFX_G1].available = 0;
16642 + cap->layer_cap[DRM_HAL_GFX_G2].available = 0;
16649 + cap->layer_cap[DRM_HAL_GFX_G3].formats[0] = DRM_HAL_FMT_ARGB8888;
16658 + int matched = 0;
16677 + for (i = 0; i < DRM_HAL_GFX_MAX; i++) {
16678 + if (cap.layer_cap[i].available != 0 &&
16688 + return 0;
16694 + hi_vo_csc csc = {0};
16702 + if (ret != 0) {
16709 + if (ret != 0) {
16713 + return 0;
16718 + int ret = 0;
16721 + enum drm_connector_status mipi_status = 0;
16722 + enum drm_connector_status hdmi_status = 0;
16753 + return 0;
16757 + if (ret != 0) {
16762 + if (ret != 0) {
16767 + if (ret != 0) {
16772 + return 0;
16793 + if (hi_plane->status == 0) {
16794 + return 0;
16798 + if (ret != 0) {
16803 + if (ret != 0) {
16806 + hi_plane->status = 0;
16807 + return 0;
16857 + hi_plane->root_hi_crtc->status == 0) {
16862 + gem = drm_gem_fb_get_obj(fb, 0);
16870 + hal_rect.x = 0;
16871 + hal_rect.y = 0;
16875 + if (ret != 0) {
16882 + if (ret != 0) {
16887 + ret = gfx_dev->set_attr(hi_plane->id, DRM_HAL_GFX_ATTR_STRIDE, &fb->pitches[0]);
16888 + if (ret != 0) {
16894 + if (ret != 0) {
16900 + if (ret != 0) {
16915 + return 0;
16955 + case 0:
16964 + return 0;
16981 + return 0;
16987 + if (ret != 0) {
16993 + if (ret != 0) {
17001 + return 0;
17020 + if (hi_crtc->status == 0) {
17022 + return 0;
17026 + if (ret != 0) {
17031 + for (i = 0; i < HI_DRM_MAX_PRIMARY_NUM; i++) {
17042 + if (ret != 0) {
17045 + hi_crtc->status = 0;
17075 + if (ret != 0) {
17079 + return 0;
17087 + hi_vo_user_intfsync_info intf_sync_attr = {0};
17105 + ret = disp_dev->attach_user_intf_sync(hi_crtc->id, &intf_sync_attr, 0);
17106 + if (ret != 0) {
17110 + return 0;
17124 + if (ret != 0) {
17128 + return 0;
17142 + if (ret != 0) {
17146 + return 0;
17160 + if (ret != 0) {
17164 + return 0;
17171 + struct drm_hal_gfx_capability cap = {0};
17179 + if (cap.layer_cap[layer].available == 0) {
17183 + for (i = 0; i < HI_DRM_MAX_CRTC_NUM; i++) {
17197 + if (type == DRM_HAL_GFX_CB_INTR_100 && hi_crtc->adp_crtc_cb != NULL && hi_crtc->status != 0) {
17200 + return 0;
17218 + return 0;
17225 + if (ret != 0) {
17230 + return 0;
17246 + {DRM_HAL_TIMING_FMT_1080P_60, {148500, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0}},
17247 + {DRM_HAL_TIMING_FMT_1080P_50, {148500, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0}},
17248 + {DRM_HAL_TIMING_FMT_1080P_59_94, {148352, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0…
17249 + {DRM_HAL_TIMING_FMT_1080P_30, {74250, 1920, 2008, 2052, 2200, 0, 1080, 1084, 1089, 1125, 0}},
17250 + {DRM_HAL_TIMING_FMT_1080P_25, {74250, 1920, 2448, 2492, 2640, 0, 1080, 1084, 1089, 1125, 0}},
17251 + {DRM_HAL_TIMING_FMT_1080P_24, {74250, 1920, 2558, 2602, 2750, 0, 1080, 1084, 1089, 1125, 0}},
17252 + {DRM_HAL_TIMING_FMT_1080I_60, {74250, 1920, 2008, 2052, 2200, 0, 540, 542, 547, 562, 0}},
17253 + {DRM_HAL_TIMING_FMT_1080I_50, {74250, 1920, 2448, 2492, 2640, 0, 540, 542, 547, 562, 0}},
17254 + {DRM_HAL_TIMING_FMT_720P_60, {74250, 1280, 1390, 1430, 1650, 0, 720, 725, 730, 750, 0}},
17255 + {DRM_HAL_TIMING_FMT_720P_50, {74250, 1280, 1720, 1760, 1980, 0, 720, 725, 730, 750, 0}},
17256 + {DRM_HAL_TIMING_FMT_576P_50, {27000, 720, 732, 796, 864, 0, 576, 581, 586, 625, 0}},
17257 + {DRM_HAL_TIMING_FMT_480P_60, {27000, 720, 736, 798, 858, 0, 480, 489, 495, 525, 0}},
17258 + {DRM_HAL_TIMING_FMT_PAL, {13500, 720, 732, 795, 864, 0, 288, 290, 293, 312, 0}},
17259 + {DRM_HAL_TIMING_FMT_NTSC, {13500, 720, 739, 801, 858, 0, 240, 244, 247, 262, 0}},
17260 + {DRM_HAL_TIMING_FMT_VESA_800X600_60, {40000, 800, 840, 968, 1056, 0, 600, 601, 605, 628, 0}},
17261 + {DRM_HAL_TIMING_FMT_VESA_1024X768_60, {48400, 1024, 1048, 1184, 1344, 0, 768, 771, 777, 806, 0…
17262 + {DRM_HAL_TIMING_FMT_VESA_1280X800_60, {83500, 1280, 1352, 1480, 1680, 0, 800, 803, 809, 831, 0…
17263 …_HAL_TIMING_FMT_VESA_1280X1024_60, {108000, 1280, 1328, 1440, 1688, 0, 1024, 1025, 1028, 1066, 0}},
17264 + {DRM_HAL_TIMING_FMT_VESA_1366X768_60, {85500, 1366, 1436, 1579, 1792, 0, 768, 771, 774, 798, 0…
17265 … {DRM_HAL_TIMING_FMT_VESA_1440X900_60, {106500, 1440, 1488, 1520, 1600, 0, 900, 903, 909, 926, 0}},
17266 …_HAL_TIMING_FMT_VESA_1600X1200_60, {162000, 1600, 1664, 1856, 2160, 0, 1200, 1201, 1204, 1250, 0}},
17267 …_HAL_TIMING_FMT_VESA_1680X1050_60, {146250, 1680, 1784, 1960, 2240, 0, 1050, 1053, 1059, 1089, 0}},
17268 …_HAL_TIMING_FMT_VESA_1920X1200_60, {193250, 1920, 1968, 2000, 2080, 0, 1200, 1203, 1209, 1235, 0}},
17269 … {DRM_HAL_TIMING_FMT_2560X1440_60, {238750, 2560, 2608, 2640, 2720, 0, 1440, 1442, 1447, 1481, 0}},
17270 … {DRM_HAL_TIMING_FMT_2560X1600_60, {268500, 2560, 2608, 2640, 2720, 0, 1600, 1603, 1609, 1646, 0}},
17271 …{DRM_HAL_TIMING_FMT_3840X2160P_24, {297000, 3840, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0}},
17272 …{DRM_HAL_TIMING_FMT_3840X2160P_25, {297000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0}},
17273 …{DRM_HAL_TIMING_FMT_3840X2160P_30, {297000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0}},
17274 …{DRM_HAL_TIMING_FMT_3840X2160P_50, {594000, 3840, 4896, 4984, 5280, 0, 2160, 2168, 2178, 2250, 0}},
17275 …{DRM_HAL_TIMING_FMT_3840X2160P_60, {594000, 3840, 4016, 4104, 4400, 0, 2160, 2168, 2178, 2250, 0}},
17276 …{DRM_HAL_TIMING_FMT_4096X2160P_24, {297000, 4096, 5116, 5204, 5500, 0, 2160, 2168, 2178, 2250, 0}},
17277 …{DRM_HAL_TIMING_FMT_4096X2160P_25, {297000, 4096, 5064, 5152, 5280, 0, 2160, 2168, 2178, 2250, 0}},
17278 …{DRM_HAL_TIMING_FMT_4096X2160P_30, {297000, 4096, 4184, 4272, 4400, 0, 2160, 2168, 2178, 2250, 0}},
17279 …{DRM_HAL_TIMING_FMT_4096X2160P_50, {594000, 4096, 5064, 5152, 5280, 0, 2160, 2168, 2178, 2250, 0}},
17280 …{DRM_HAL_TIMING_FMT_4096X2160P_60, {594000, 4096, 4184, 4272, 4400, 0, 2160, 2168, 2178, 2250, 0}},
17281 + {DRM_HAL_TIMING_FMT_USER, {155493, 480, 528, 560, 620, 0, 960, 963, 968, 974, 0}},
17288 + for (i = 0; i < sizeof(g_adp_crtc_timing_map) / sizeof(struct adp_crtc_timing_map); i++) {
17320 @@ -0,0 +1,69 @@
17395 @@ -0,0 +1,345 @@
17433 + unsigned int open; /* 0: close, 1: open */
17434 + unsigned int enable; /* 0: disable, 1: enable */
17473 + return 0;
17477 + if (ret != 0) {
17482 + return 0;
17494 + if (hdmitx->open == 0) {
17495 + return 0;
17499 + if (ret != 0) {
17503 + hdmitx->open = 0;
17504 + return 0;
17517 + return 0;
17521 + if (ret != 0) {
17526 + return 0;
17538 + if (hdmitx->enable == 0) {
17539 + return 0;
17543 + if (ret != 0) {
17547 + hdmitx->enable = 0;
17548 + return 0;
17563 + if (ret != 0) {
17568 + if (ret <= 0) {
17571 + return 0;
17586 + if (ret != 0) {
17591 + if (ret != 0) {
17618 + if (ret != 0) {
17623 + if (ret != 0) {
17626 + return 0;
17640 + if (ret != 0) {
17645 + if (ret != 0) {
17648 + return 0;
17655 + struct drm_hal_hdmitx_attr hdmi_attr = {0};
17666 + if (ret != 0) {
17671 + return 0;
17676 + if (ret != 0) {
17682 + if (ret != 0) {
17687 + if (ret != 0) {
17704 + if (ret != 0) {
17707 + return 0;
17719 + g_hi_hdmitx->hdmitx[0].drm_hdmi_id = drm_hdmi_id;
17720 + g_hi_hdmitx->hdmitx[0].hi_hdmi_id = DRM_HAL_HDMITX_0;
17721 + *conn = &g_hi_hdmitx->hdmitx[0].conn;
17722 + *encoder = &g_hi_hdmitx->hdmitx[0].encoder;
17723 + return 0;
17733 + return 0;
17746 @@ -0,0 +1,28 @@
17780 @@ -0,0 +1,300 @@
17822 + unsigned int enable; /* 0: disable, 1: enable */
17844 + .flags = 0, /* 0 alg data */
17865 + if (ret != 0) {
17898 + return 0;
17902 + if (ret != 0) {
17907 + if (ret != 0) {
17913 + if (ret != 0) {
17917 + return 0;
17930 + return 0;
17934 + if (ret != 0) {
17940 + return 0;
17953 + if (hi_mipitx->enable == 0) {
17954 + return 0;
17958 + if (ret != 0) {
17963 + hi_mipitx->enable = 0;
17964 + return 0;
17978 + return 0;
17993 + return 0;
18006 + return 0;
18008 + if (brightness < 0 || brightness >255) {
18009 + HI_DRM_INFO("brightness value out of range[0~255]!");
18010 + return 0;
18013 + if (ret != 0) {
18017 + return 0;
18024 + hi_mipitx->private.tv_brightness_property = drm_property_create_range(dev, 0, "brightness", 0,…
18030 + return 0;
18056 + return 0;
18068 + return 0;
18086 @@ -0,0 +1,32 @@
18124 @@ -0,0 +1,389 @@
18163 + if (ret != 0) {
18174 + if (ret != 0) {
18180 + return 0;
18200 + if (ret != 0) {
18222 + if (ret != 0) {
18228 + return 0;
18236 + if (ret != 0) {
18249 + if (ret != 0) {
18267 + if (drm_crtc_vblank_get(crtc) == 0) {
18308 + if (ret != 0) {
18339 + return 0;
18348 + if (ret != 0) {
18356 + return 0;
18377 + if (ret != 0) {
18404 + if (ret != 0) {
18409 + /* get the primary 0 plane on this crtc */
18410 + ret = hi_adp_plane_get_by_index(crtc, &primary, DRM_PLANE_TYPE_PRIMARY, 0);
18411 + if (ret != 0) {
18417 + if (ret != 0) {
18423 + if (ret != 0) {
18439 + if (ret != 0) {
18455 + if (ret != 0) {
18462 + for (i = 0; i < cap.crtc_num; i++) {
18466 + return 0;
18476 + for (i = 0; i < cap.crtc_num; i++) {
18495 + for (i = 0; i < cap.crtc_num; i++) {
18497 + if (ret != 0) {
18503 + for (j = 0; j < HI_DRM_MAX_PRIMARY_NUM; j++) {
18505 + if (ret != 0) {
18519 @@ -0,0 +1,17 @@
18542 @@ -0,0 +1,385 @@
18577 +#define DRIVER_MINOR 0
18616 + uint32_t handle = 0;
18624 + HI_DRM_ERR("gem object not finde fd %d, handle 0x%x", arg->fd, handle);
18636 + return 0;
18653 + return 0;
18656 + HI_DRM_ERR("drm_check_dumb_phy_addr, addr_start-addr_end [0x%llx-0x%llx]\n", addr_start, addr_…
18670 + if (ret != 0) {
18677 + return 0;
18679 + (void)memset(node, 0, sizeof(struct hi_drm_phys));
18684 + HI_DRM_ERR("gem object not finde handle 0x%x", args->handle);
18700 + return 0;
18785 + dev->mode_config.min_width = 0;
18786 + dev->mode_config.min_height = 0;
18799 + if (ret != 0) {
18804 + if (ret != 0) {
18809 + if (ret != 0) {
18814 + if (ret != 0) {
18822 + return 0;
18870 + if (ret != 0) {
18875 + ret = drm_dev_register(drm_dev, 0);
18876 + if (ret != 0) {
18883 + return 0;
18906 + return 0;
18933 @@ -0,0 +1,29 @@
18956 +} while (0)
18968 @@ -0,0 +1,43 @@
19004 + return 0;
19018 @@ -0,0 +1,27 @@
19051 @@ -0,0 +1,233 @@
19093 + if (ret != 0) {
19100 + if (ret != 0) {
19152 + return 0;
19160 + if (ret != 0) {
19172 + if (ret != 0) {
19206 + if (ret != 0) {
19224 + if (ret != 0) {
19250 + if (ret != 0) {
19256 + if (ret != 0) {
19270 + if (ret != 0) {
19275 + return 0;
19290 @@ -0,0 +1,16 @@
19312 @@ -0,0 +1,189 @@
19375 + return 0;
19391 + if (ret != 0) {
19403 + if (ret != 0) {
19428 + if (ret != 0) {
19446 + if (ret != 0) {
19462 + if (ret != 0) {
19469 + if (ret != 0) {
19484 + if (ret != 0) {
19490 + return 0;
19507 @@ -0,0 +1,17 @@
19530 @@ -0,0 +1,31 @@
19545 +#define DRM_HISILICON_GEM_FD_TO_PHYADDR 0x1
19567 @@ -0,0 +1,26 @@
19599 @@ -0,0 +1,2 @@
19607 @@ -0,0 +1,41 @@
19637 +#define VDMA_DATA_CMD 0x6
19654 @@ -0,0 +1,534 @@
19711 + && ((uintptr_t)ptr > 0))
19713 +int vdma_flag = 0;
19742 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
19743 + if (((dma_intr_status >> i) & 0x1) == 1) {
19796 + return 0;
19799 + for (i = 0; i < CHANNEL_NUM; i++) {
19805 + if (((tmp & 0x01) == 0x00) && (channel_intr == 0x00)) {
19824 + return 0;
19857 + reg[channel] &= 0xfffffc00;
19885 + return 0;
19889 + return 0;
19899 + unsigned int tmp_reg = 0;
19902 + return 0;
19907 + /* set rd dust address is ram 0 */
19908 + dmac_writew(hi_reg_vdma_base_va + DMAC_RD_DUSTB_ADDR, 0x04c11000);
19910 + /* set wr dust address is ram 0x1000 */
19911 + dmac_writew(hi_reg_vdma_base_va + DMAC_WR_DUSTB_ADDR, 0x04c11000);
19923 + for (i = 0; i < CHANNEL_NUM; i++) {
19931 + return 0;
19944 + return 0;
19955 + return 0;
19993 + int ret = 0;
20003 + wake_channel_flag[ulchnn] = 0;
20012 + if (hi_vdma_channelstart(ulchnn, psource, pdest) != 0) {
20033 + if (((uintptr_t)dst & 0xff) || ((uintptr_t)src & 0xff)) {
20050 + if (ret < 0) {
20053 + return 0;
20069 + res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
20092 + dma->irq = platform_get_irq(platdev, 0);
20093 + if (unlikely(dma->irq < 0)) {
20107 + for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
20123 + for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
20127 + vdma_flag = 0;
20130 + return 0;
20141 + for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
20147 + vdma_flag = 0;
20149 + return 0;
20159 + for (i = 0; i < CONFIG_HI_VDMA_CHN_NUM; i++) {
20165 + return 0;
20194 @@ -0,0 +1,122 @@
20220 +#define DMAC_GLOBLE_CTRL 0x000
20221 +#define WFE_EN (0x1 << 23)
20222 +#define EVENT_BROADCAST_EN (0x1 << 21)
20223 +#define AUTO_CLK_GT_EN (0x1 << 17)
20224 +#define AUTO_PRI_EN (0x1 << 16)
20225 +#define WR_CMD_NUM_PER_ARB (0x4 << 12)
20226 +#define RD_CMD_NUM_PER_ARB (0x4 << 8)
20227 +#define WR_OTD_NUM (0xF << 4)
20228 +#define RD_OTD_NUM (0xF)
20230 +#define DMAC_PRI_THRESHOLD 0x004
20232 +#define DMAC_MMU_NMRR 0x008
20233 +#define DMAC_MMU_PRRR 0x00C
20235 +#define DMAC_RD_DUSTB_ADDR 0x010
20236 +#define DMAC_WR_DUSTB_ADDR 0x014
20238 +#define DMAC_CHANNEL_STATUS 0x01c
20239 +#define DMAC_WORK_DURATION 0x020
20240 +#define DMAC_INT_STATUS 0x02c
20242 +#define DMAC_CHANNEL_BASE 0x100
20243 +#define DMAC_CxSRCADDR(i) (DMAC_CHANNEL_BASE + 0x00 + 0x20 * i)
20244 +#define DMAC_CxDESTADDR(i) (DMAC_CHANNEL_BASE + 0x04 + 0x20 * i)
20245 +#define DMAC_CxLENGTH(i) (DMAC_CHANNEL_BASE + 0x08 + 0x20 * i)
20246 +#define DMAC_CxTTBR(i) (DMAC_CHANNEL_BASE + 0x0C + 0x20 * i)
20247 +#define DMAC_CxMISC(i) (DMAC_CHANNEL_BASE + 0x10 + 0x20 * i)
20248 +#define DMAC_CxINTR_RAW(i) (DMAC_CHANNEL_BASE + 0x14 + 0x20 * i)
20249 +#define CX_INT_STAT (0x1 << 4)
20250 +#define CX_INT_TC_RAW (0x1 << 3)
20251 +#define CX_INT_TE_RAW (0x1 << 2)
20252 +#define CX_INT_TM_RAW (0x1 << 1)
20253 +#define CX_INT_AP_RAW (0x1 << 0)
20255 +#define DMAC_INTR_ENABLE (0x1 << 8)
20258 +#define DMAC_CHANNEL_ENABLE (0x1 << 9)
20261 +#define AFE (0x1 << 6)
20264 +#define DEST_IS_KERNEL (0x1 << 2)
20265 +#define SRC_IS_KERNEL (0x1 << 1)
20268 +#define TTB_RGN (0x1 << 3) /* outer cache write back allocate */
20273 +#define TRE 0x001
20275 +#define PRRR 0xff0a81a8
20276 +#define NMRR 0x40e040e0
20278 +#define DMAC_SYNC_VAL 0x0
20292 +#define DMAC_SWIDTH_ERROR (DMAC_ERROR_BASE + 0xa)
20293 +#define DMAC_LLI_ADDRESS_INVALID (DMAC_ERROR_BASE + 0xb)
20294 +#define DMAC_TRANS_CONTROL_INVALID (DMAC_ERROR_BASE + 0xc)
20295 +#define DMAC_MEMORY_ALLOCATE_ERROR (DMAC_ERROR_BASE + 0xd)
20296 +#define DMAC_NOT_FINISHED (DMAC_ERROR_BASE + 0xe)
20298 +#define DMAC_TIMEOUT (DMAC_ERROR_BASE + 0xf)
20299 +#define DMAC_CHN_SUCCESS (DMAC_ERROR_BASE + 0x10)
20300 +#define DMAC_CHN_CONFIG_ERROR (DMAC_ERROR_BASE + 0x11)
20301 +#define DMAC_CHN_DATA_ERROR (DMAC_ERROR_BASE + 0x12)
20302 +#define DMAC_CHN_TIMEOUT (DMAC_ERROR_BASE + 0x13)
20303 +#define DMAC_CHN_ALLOCAT (DMAC_ERROR_BASE + 0x14)
20304 +#define DMAC_CHN_VACANCY (DMAC_ERROR_BASE + 0x15)
20310 +#define DMA_TRANS_OK 0x1
20311 +#define DMA_PAGE_FAULT 0x2
20312 +#define DMA_TRANS_FAULT 0x3
20322 @@ -0,0 +1,109 @@
20365 +} while (0)
20371 + long ret = 0;
20393 + return 0;
20398 + return 0;
20437 @@ -0,0 +1,21 @@
20464 @@ -0,0 +1,6 @@
20476 @@ -0,0 +1,1303 @@
20538 +#define RX 0
20540 +static int dmac_channel[CHANNEL_NUM] = {0, 1, 2, 3};
20549 +#define dma_err(fmt, ...) do {} while (0)
20574 +#define CLR_INT(i) ((*(unsigned int *)(dma_regbase+0x008)) = (1 << i))
20590 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
20591 + if ((((channel_status >> i) & 0x1) == 0x01)) {
20598 + if ((0x01 == ((channel_tc_status >> i) & 0x01)))
20600 + (0x01 << i));
20601 + else if ((0x01 == ((channel_err_status
20602 + >> i) & 0x01)))
20604 + (0x01 << i));
20610 + if ((0x01 == ((channel_tc_status >> i) & 0x01))) {
20612 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, (0x01 << i));
20613 + } else if ((0x01 == ((channel_err_status >> i) & 0x01))) {
20615 + dmac_writew(dma->regbase + DMAC_INTERRCLR, (0x01 << i));
20640 + unsigned int time = 0;
20644 + for (j = 0; j < 3; j++) {
20646 + channel_tc_status[j] = (channel_status >> i) & 0x01;
20648 + channel_err_status[j] = (channel_status >> i) & 0x01;
20651 + if ((channel_tc_status[0] == 0x1) &&
20652 + (channel_tc_status[1] == 0x1) &&
20653 + (channel_tc_status[2] == 0x1)) {
20655 + dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x01 << i));
20657 + } else if ((channel_err_status[0] == 0x1) &&
20658 + (channel_err_status[1] == 0x1) &&
20659 + (channel_err_status[2] == 0x1)) {
20662 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x01 << i));
20681 + int status = 0;
20718 + for (i = 0; i < CHANNEL_NUM; i++) {
20723 + g_channelinfo = g_channelinfo & 0x00ff;
20725 + for (i = 0; i < CHANNEL_NUM; i++) {
20728 + if (0x00 == (channelinfo & 0x01)) {
20731 + (0x01 << dmac_channel[i]));
20733 + (0x01 << dmac_channel[i]));
20760 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x01 << channel));
20761 + dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x01 << channel));
20766 + return 0;
20781 + return 0;
20815 + if (tempvalue == 0) {
20818 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
20819 + dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
20820 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
20830 + if (ret < 0) {
20834 + if (request_irq(dma->irq, dmac_isr, 0, "hi_dma", dma)) {
20840 + return 0;
20846 + * ppheadlli[0]: memory physics address
20862 + ppheadlli[0] = (unsigned int)(dma_phys);
20865 + return 0;
20877 + dma_phys = (dma_addr_t)(ppheadlli[0]);
20883 + ppheadlli[0] = 0;
20884 + ppheadlli[1] = 0;
20885 + return 0;
20914 + dmac_writew(dma_regbase + DMAC_CxLLI(uwchannel_num), 0);
20915 + tmp_trasnsfer = (uwnumtransfers >> 2) & 0xfff;
20916 + tmp_trasnsfer = tmp_trasnsfer | (DMAC_CxCONTROL_M2M & (~0xfff));
20920 + return 0;
20942 + return 0;
20952 + int ret = 0;
20954 + if (channel < 0) {
20997 + phy_address = (unsigned int)(ppheadlli[0]);
20998 + dma_debug("phy_address: 0x%X\n", phy_address);
21000 + dma_debug("address: 0x%X\n", address);
21001 + for (j = 0; j < lli_num; j++) {
21002 + dma_debug("psource[%d]: 0x%X\n", j, psource[j]);
21006 + dma_debug("pdest[%d]: 0x%X\n", j, pdest[j]);
21011 + /* if the last node, next_lli_addr = 0 */
21013 + dmac_writew(address, 0);
21016 + (((phy_address + 8) & (~0x03)) |
21025 + (~0xfff)) | (length[j]) |
21026 + 0x80000000));
21029 + (((DMAC_CxCONTROL_LLIM2M_ISP & (~0xfff)) |
21030 + (length[j])) & 0x7fffffff));
21038 + return 0;
21049 + unsigned int lli_num = 0;
21050 + unsigned int last_lli = 0;
21056 + if ((totaltransfersize % uwnumtransfers) != 0) {
21061 + phy_address = (unsigned int)(ppheadlli[0]);
21063 + for (j = 0; j < lli_num; j++) {
21073 + dmac_writew(address, 0);
21076 + (((phy_address + 8) & (~0x03)) |
21082 + if ((j == (lli_num - 1)) && (last_lli == 0))
21084 + (~0xfff)) |
21086 + 0x80000000));
21090 + (~0xfff)) |
21093 + 0x80000000));
21096 + (((DMAC_CxCONTROL_LLIM2M & (~0xfff)) |
21097 + (uwnumtransfers >> 2)) & 0x7fffffff));
21104 + return 0;
21125 + reg_value &= 0xFFFFFFFE;
21137 + reg_value &= 0xFFFFFFFE;
21142 + reg_value = reg_value & 0x00ff;
21143 + count = 0;
21144 + while (((reg_value >> channel) & 0x1) == 1) {
21146 + reg_value = reg_value & 0x00ff;
21153 + return 0;
21179 + memset(&plli, 0, sizeof(plli));
21187 + dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << uwchannel_num));
21188 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << uwchannel_num));
21189 + dmac_writew(dma_regbase + DMAC_SYNC, 0x0);
21204 + return 0;
21217 + unsigned int temp = 0;
21231 + memset(&plli, 0, sizeof(plli));
21239 + dmac_writew(dma_regbase + DMAC_INTTCCLEAR, (0x1 << uwchannel_num));
21240 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << uwchannel_num));
21241 + dmac_writew(dma_regbase + DMAC_SYNC, 0x0);
21255 + return 0;
21268 + unsigned int uwtrans_control = 0;
21270 + unsigned int uwdst_addr = 0;
21271 + unsigned int uwsrc_addr = 0;
21284 + (uwchannel_num > CHANNEL_NUM) || (uwchannel_num < 0)) {
21298 + if (tmp & (~0x0fff)) {
21303 + tmp = tmp & 0xfff;
21305 + (g_peripheral[uwperipheralid].transfer_ctrl & (~0xfff));
21307 + (0x1 << (unsigned int)uwchannel_num));
21308 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << (unsigned int)uwchannel_num));
21318 + return 0;
21330 + unsigned int uwtrans_control = 0;
21332 + unsigned int uwdst_addr = 0;
21333 + unsigned int uwsrc_addr = 0;
21346 + (uwchannel_num > 3) || (uwchannel_num < 0)) {
21360 + if (tmp & (~0x0fff)) {
21365 + tmp = tmp & 0xfff;
21367 + (g_peripheral[uwperipheralid].transfer_ctrl & (~0xfff));
21369 + (0x1 << (unsigned int)uwchannel_num));
21370 + dmac_writew(dma_regbase + DMAC_INTERRCLR, (0x1 << (unsigned int)uwchannel_num));
21380 + return 0;
21390 + unsigned int dma_size = 0;
21394 + dma_count = 0;
21401 + while ((left_size >> 2) >= 0xffc) {
21402 + dma_size = 0xffc;
21413 + if (dmac_channelstart(ulchnn) != 0) {
21429 + if (dmac_channelstart(ulchnn) != 0) {
21437 + return 0;
21447 + unsigned int dma_size = 0;
21451 + dma_count = 0;
21460 + while ((left_size >> uwwidth) >= 0xffc) {
21461 + dma_size = 0xffc;
21466 + uwperipheralid, (dma_size << uwwidth), 0) < 0) {
21470 + if (dmac_channelstart(ulchnn) != 0) {
21482 + pr_debug("memaddr=0x%x\n", (unsigned int)(memaddr +
21487 + uwperipheralid, left_size, 0) < 0) {
21491 + if (dmac_channelstart(ulchnn) != 0) {
21504 + unsigned int dma_size = 0;
21509 + dma_count = 0;
21518 + while ((left_size >> uwwidth) >= 0xffc) {
21519 + dma_size = 0xffc;
21524 + uwperipheralid, (dma_size << uwwidth), 0) < 0) {
21528 + if (dmac_channelstart(ulchnn) != 0) {
21540 + pr_debug("memaddr=0x%x\n", (unsigned int)(memaddr +
21545 + uwperipheralid, left_size, 0) < 0) {
21549 + if (dmac_channelstart(ulchnn) != 0) {
21586 + if (dmac_channelstart(chnn) != 0) {
21598 + int ret = 0;
21602 + if (uwperipheralid < 0) {
21623 + if (uwperipheralid < 0) {
21653 + res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
21674 + dma->irq = platform_get_irq(platdev, 0);
21675 + if (unlikely(dma->irq < 0)) {
21688 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
21703 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
21709 + return 0;
21720 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
21726 + return 0;
21739 + if (tempvalue == 0) {
21742 + dmac_writew(dma->regbase + DMAC_INTTCCLEAR, 0xFF);
21743 + dmac_writew(dma->regbase + DMAC_INTERRCLR, 0xFF);
21744 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
21751 + for (i = 0; i < DMAC_MAX_CHANNELS; i++) {
21755 + return 0;
21785 @@ -0,0 +1,90 @@
21815 +#define dma_debug(fmt, ...) do {} while (0);
21818 +#define DMAC_CONFIGURATIONx_HALT_DMA_ENABLE (0x01L<<18)
21819 +#define DMAC_CONFIGURATIONx_ACTIVE (0x01L<<17)
21821 +#define DMAC_CONFIGURATIONx_CHANNEL_DISABLE 0
21835 +#define DMAC_SWIDTH_ERROR (DMAC_ERROR_BASE+0xa)
21836 +#define DMAC_LLI_ADDRESS_INVALID (DMAC_ERROR_BASE+0xb)
21837 +#define DMAC_TRANS_CONTROL_INVALID (DMAC_ERROR_BASE+0xc)
21838 +#define DMAC_MEMORY_ALLOCATE_ERROR (DMAC_ERROR_BASE+0xd)
21839 +#define DMAC_NOT_FINISHED (DMAC_ERROR_BASE+0xe)
21841 +#define DMAC_TIMEOUT (DMAC_ERROR_BASE+0xf)
21842 +#define DMAC_CHN_SUCCESS (DMAC_ERROR_BASE+0x10)
21843 +#define DMAC_CHN_ERROR (DMAC_ERROR_BASE+0x11)
21844 +#define DMAC_CHN_TIMEOUT (DMAC_ERROR_BASE+0x12)
21845 +#define DMAC_CHN_ALLOCAT (DMAC_ERROR_BASE+0x13)
21846 +#define DMAC_CHN_VACANCY (DMAC_ERROR_BASE+0x14)
21848 +#define DMAC_CONFIGURATIONx_ACTIVE_NOT 0
21851 +#define DMAC_TRANS_SIZE 0xff0
21873 +/* #define PAGE_SIZE 0x1000 */
21881 @@ -0,0 +1,29 @@
21916 @@ -0,0 +1,4 @@
21926 @@ -0,0 +1,946 @@
21997 +unsigned long pllihead[2] = {0, 0};
22022 + for (i = 0; i < HIEDMAC_CHANNEL_NUM; i++) {
22049 + channel_status = (channel_status >> i) & 0x01;
22052 + channel_tc_status = (channel_tc_status >> i) & 0x01;
22060 + channel_tc_status = (channel_tc_status >> i) & 0x01;
22067 + channel_err_status[0] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR1);
22068 + channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
22070 + channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
22072 + channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
22074 + if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
22076 + channel_err_status[0] = hiedmacv310_readl(dma_regbase + HIEDMAC_INT_ERR1);
22102 + if (channel < 0 || channel > HIEDMAC_CHANNEL_NUM - 1) {
22103 + hiedmacv310_error("invalid channel,channel=%0d\n", channel);
22109 + return 0;
22118 + if ((channel >= 0) && (channel < HIEDMAC_CHANNEL_NUM))
22121 + return 0;
22140 + if ((channel >= 0) && (channel < HIEDMAC_CHANNEL_NUM))
22149 + int ret = 0;
22151 + if (channel < 0)
22206 + hiedmacv310_writel(memaddr & 0xffffffff,
22209 + hiedmacv310_writel((memaddr >> 32) & 0xffffffff,
22212 + hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n",
22215 + hiedmacv310_writel(g_peripheral[uwperipheralid].peri_addr & 0xffffffff,
22218 + hiedmacv310_writel((g_peripheral[uwperipheralid].peri_addr >> 32) & 0xffffffff,
22221 + hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n",
22224 + hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn));
22225 + hiedmacv310_trace(4, "HIEDMAC_Cx_LLI_L = 0x%x\n",
22229 + hiedmacv310_trace(4, "HIEDMAC_Cx_CNT0 = 0x%x\n",
22236 + hiedmacv310_trace(4, "HIEDMAC_Cx_CONFIG = 0x%x\n", temp);
22262 + hiedmacv310_writel(memaddr & 0xffffffff,
22265 + hiedmacv310_writel((memaddr >> 32) & 0xffffffff,
22268 + hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n",
22271 + hiedmacv310_writel(g_peripheral[uwperipheralid].peri_addr & 0xffffffff,
22274 + hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_SRC_ADDR_H(ulchnn));
22276 + hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n",
22279 + hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(ulchnn));
22280 + hiedmacv310_trace(4, "HIEDMAC_Cx_LLI_L = 0x%x\n",
22284 + hiedmacv310_trace(4, "HIEDMAC_Cx_CNT0 = 0x%x\n",
22291 + hiedmacv310_trace(4, "HIEDMAC_Cx_CONFIG = 0x%x\n", temp);
22299 + int ret = 0;
22303 + if (uwperipheralid < 0) {
22325 + if (uwperipheralid < 0) {
22349 + int lli_num = 0;
22354 + if (uwnumtransfers == 0)
22358 + if ((totaltransfersize % uwnumtransfers) != 0)
22363 + phy_address = ppheadlli[0];
22365 + hiedmacv310_trace(4, "phy_address: 0x%lx\n", phy_address);
22366 + hiedmacv310_trace(4, "address: 0x%p\n", plli);
22367 + for (j = 0; j < lli_num; j++) {
22368 + memset(plli, 0x0, sizeof(dmac_lli));
22370 + * at the last transfer, chain_en should be set to 0x0;
22371 + * others tansfer,chain_en should be set to 0x2;
22392 + return 0;
22405 + hiedmacv310_trace(4, "plli.src_addr: 0x%lx\n", plli->src_addr);
22406 + hiedmacv310_trace(4, "plli.dst_addr: 0x%lx\n", plli->dest_addr);
22407 + hiedmacv310_trace(4, "plli.next_lli: 0x%lx\n", plli->next_lli);
22408 + hiedmacv310_trace(4, "plli.count: 0x%d\n", plli->count);
22410 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
22413 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
22418 + hiedmacv310_writel(plli->src_addr & 0xffffffff,
22421 + hiedmacv310_writel((plli->src_addr >> 32) & 0xffffffff,
22424 + hiedmacv310_writel(plli->dest_addr & 0xffffffff,
22427 + hiedmacv310_writel((plli->dest_addr >> 32) & 0xffffffff,
22433 + return 0;
22445 + if (uwnumtransfers > HIEDMAC_TRANS_MAXSIZE || uwnumtransfers == 0) {
22449 + hiedmacv310_trace(4, "channel[%d],source=0x%lx,dest=0x%lx,length=%d\n",
22452 + hiedmacv310_writel(psource & 0xffffffff,
22454 + hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_L = 0x%x\n",
22457 + hiedmacv310_writel((psource >> 32) & 0xffffffff,
22459 + hiedmacv310_trace(4, "HIEDMAC_Cx_SRC_ADDR_H = 0x%x\n",
22462 + hiedmacv310_writel(pdest & 0xffffffff, dma_regbase + HIEDMAC_Cx_DEST_ADDR_L(i));
22463 + hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_L = 0x%x\n",
22466 + hiedmacv310_writel((pdest >> 32) & 0xffffffff,
22468 + hiedmacv310_trace(4, "HIEDMAC_Cx_DEST_ADDR_H = 0x%x\n",
22471 + hiedmacv310_writel(0, dma_regbase + HIEDMAC_Cx_LLI_L(i));
22478 + return 0;
22488 + unsigned int dma_size = 0;
22492 + dma_count = 0;
22494 + if (ulchnn < 0) {
22498 + hiedmacv310_trace(6, "using channel[%d],source=0x%lx,dest=0x%lx,length=%d\n",
22520 + return 0;
22535 + int ret = 0;
22539 + if (chnn < 0) {
22546 + if (pllihead[0] == 0) {
22547 + hiedmacv310_error("ppheadlli[0] is NULL.\n");
22573 + * ppheadlli[0]: memory physics address
22590 + ppheadlli[0] = (unsigned long)(dma_phys);
22597 + return 0;
22605 + int i = 0;
22606 + unsigned int count = 0;
22607 + unsigned int offset = 0;
22608 + unsigned ctrl = 0;
22610 + for (i = 0; i < EDMAC_MAX_PERIPHERALS; i++) {
22617 + offset = hiedmac->misc_ctrl_base + (count & (~0x3));
22619 + ctrl &= ~(0x3f << ((count & 0x3) << 3));
22620 + ctrl |= peripheral_info[i].peri_id << ((count & 0x3) << 3);
22628 + return 0;
22663 + res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
22676 + hiedmac->misc_regmap = 0;
22691 + hiedmac->irq = platform_get_irq(platdev, 0);
22692 + if (unlikely(hiedmac->irq < 0))
22712 + return 0;
22721 + unsigned int channel_tc_status = 0;
22722 + unsigned int channel_status = 0;
22723 + int i = 0;
22724 + unsigned int mask = 0;
22728 + hiedmacv310_error("channel_status = 0x%x\n", channel_status);
22732 + for (i = 0; i < hiedmac->channels; i++) {
22733 + channel_status = (channel_status >> i) & 0x1;
22736 + channel_tc_status = (channel_tc_status >> i) & 0x01;
22741 + channel_tc_status = (channel_tc_status >> i) & 0x01;
22745 + channel_err_status[0] = hiedmacv310_readl(hiedmac->base + HIEDMAC_INT_ERR1);
22746 + channel_err_status[0] = (channel_err_status[0] >> i) & 0x01;
22748 + channel_err_status[1] = (channel_err_status[1] >> i) & 0x01;
22750 + channel_err_status[2] = (channel_err_status[2] >> i) & 0x01;
22752 + if (channel_err_status[0] | channel_err_status[1] | channel_err_status[2]) {
22753 + hiedmacv310_error("Error in hiedmac %d finish!,ERR1 = 0x%x,ERR2 = 0x%x,ERR3 = 0x%x\n",
22754 + i, channel_err_status[0], channel_err_status[1], channel_err_status[2]);
22774 + int ret = 0;
22775 + int i = 0;
22814 + for (i = 0; i < HIEDMAC_CHANNEL_NUM; i++)
22821 + if (ret < 0)
22826 + ret = request_irq(hiedmac->irq, hiemdacv310_irq, 0, DRIVER_NAME, hiedmac);
22832 + return 0;
22842 + int err = 0;
22878 @@ -0,0 +1,184 @@
22919 +} while (0)
22929 +} while (0)
22935 +} while (0)
22939 +#define hiedmacv310_trace(level, msg...) do { } while (0)
22940 +#define hiedmacv310_assert(level, msg...) do { } while (0)
22941 +#define hiedmacv310_error(level, msg...) do { } while (0)
22949 +} while (0)
22952 +#define MAX_TRANSFER_BYTES 0xffff
22955 +#define HIEDMAC_INT_STAT (0x0)
22956 +#define HIEDMAC_INT_TC1 (0x4)
22957 +#define HIEDMAC_INT_TC2 (0x8)
22958 +#define HIEDMAC_INT_ERR1 (0xc)
22959 +#define HIEDMAC_INT_ERR2 (0x10)
22960 +#define HIEDMAC_INT_ERR3 (0x14)
22961 +#define HIEDMAC_INT_TC1_MASK (0x18)
22962 +#define HIEDMAC_INT_TC2_MASK (0x1c)
22963 +#define HIEDMAC_INT_ERR1_MASK (0x20)
22964 +#define HIEDMAC_INT_ERR2_MASK (0x24)
22965 +#define HIEDMAC_INT_ERR3_MASK (0x28)
22967 +#define HIEDMAC_INT_TC1_RAW (0x600)
22968 +#define HIEDMAC_INT_TC2_RAW (0x608)
22969 +#define HIEDMAC_INT_ERR1_RAW (0x610)
22970 +#define HIEDMAC_INT_ERR2_RAW (0x618)
22971 +#define HIEDMAC_INT_ERR3_RAW (0x620)
22973 +#define HIEDMAC_Cx_CURR_CNT0(cn) (0x404 + cn * 0x20)
22974 +#define HIEDMAC_Cx_CURR_SRC_ADDR_L(cn) (0x408 + cn * 0x20)
22975 +#define HIEDMAC_Cx_CURR_SRC_ADDR_H(cn) (0x40c + cn * 0x20)
22976 +#define HIEDMAC_Cx_CURR_DEST_ADDR_L(cn) (0x410 + cn * 0x20)
22977 +#define HIEDMAC_Cx_CURR_DEST_ADDR_H(cn) (0x414 + cn * 0x20)
22979 +#define HIEDMAC_CH_PRI (0x688)
22980 +#define HIEDMAC_CH_STAT (0x690)
22981 +#define HIEDMAC_DMA_CTRL (0x698)
22983 +#define HIEDMAC_Cx_BASE(cn) (0x800 + cn * 0x40)
22984 +#define HIEDMAC_Cx_LLI_L(cn) (0x800 + cn * 0x40)
22985 +#define HIEDMAC_Cx_LLI_H(cn) (0x804 + cn * 0x40)
22986 +#define HIEDMAC_Cx_CNT0(cn) (0x81c + cn * 0x40)
22987 +#define HIEDMAC_Cx_SRC_ADDR_L(cn) (0x820 + cn * 0x40)
22988 +#define HIEDMAC_Cx_SRC_ADDR_H(cn) (0x824 + cn * 0x40)
22989 +#define HIEDMAC_Cx_DEST_ADDR_L(cn) (0x828 + cn * 0x40)
22990 +#define HIEDMAC_Cx_DEST_ADDR_H(cn) (0x82c + cn * 0x40)
22991 +#define HIEDMAC_Cx_CONFIG(cn) (0x830 + cn * 0x40)
22993 +#define HIEDMAC_CxCONFIG_M2M 0xCFF33000
22994 +#define HIEDMAC_CxCONFIG_M2M_LLI 0xCFF00000
22995 +#define HIEDMAC_CxCONFIG_CHN_START 0x1
22996 +#define HIEDMAC_Cx_DISABLE 0x0
22998 +#define HIEDMAC_ALL_CHAN_CLR (0xff)
22999 +#define HIEDMAC_INT_ENABLE_ALL_CHAN (0xff)
23007 +#define HIEDMAC_WIDTH_8BIT (0x0)
23008 +#define HIEDMAC_WIDTH_16BIT (0x1)
23009 +#define HIEDMAC_WIDTH_32BIT (0x10)
23010 +#define HIEDMAC_WIDTH_64BIT (0x11)
23017 +#define HIEDMAC_LLI_ALIGN 0x40
23018 +#define HIEDMAC_LLI_DISABLE 0x0
23019 +#define HIEDMAC_LLI_ENABLE 0x2
23021 +#define HIEDMAC_CXCONFIG_SIGNAL_SHIFT (0x4)
23022 +#define HIEDMAC_CXCONFIG_MEM_TYPE (0x0)
23023 +#define HIEDMAC_CXCONFIG_DEV_MEM_TYPE (0x1)
23024 +#define HIEDMAC_CXCONFIG_TSF_TYPE_SHIFT (0x2)
23025 +#define HIEDMAC_CxCONFIG_LLI_START (0x1)
23027 +#define HIEDMAC_CXCONFIG_ITC_EN (0x1)
23028 +#define HIEDMAC_CXCONFIG_ITC_EN_SHIFT (0x1)
23030 +#define CCFG_EN 0x1
23040 +#define DMAC_HOST0 0
23056 +#define PERI_8BIT_MODE 0
23061 +#define HIEDMAC_LLI_PAGE_NUM 0x4 /* 4*4K*65535B/64≈16MB */
23068 @@ -0,0 +1,4 @@
23075 index 000000000..0ba50a756
23078 @@ -0,0 +1 @@
23085 @@ -0,0 +1,16 @@
23107 @@ -0,0 +1,2 @@
23115 @@ -0,0 +1,203 @@
23143 + u64 total = 0;
23145 + for (i = 0; i < num_zones; i++) {
23158 + for (i = 0; i < num_zones; i++) {
23170 + return 0;
23181 + return 0;
23184 + tmpline[sizeof(tmpline) - 1] = '\0';
23191 + for (i = 0; (argv[i] = strsep(&line, ",")) != NULL;)
23197 + return 0;
23200 + strlcpy(hisi_zone[num_zones].name, argv[0], NAME_LEN_MAX);
23207 + strlcpy(hisi_zone[num_zones].name, argv[0], NAME_LEN_MAX);
23220 + if (num_zones != 0) {
23224 + return 0;
23233 + for (i = 0; i < num_zones; i++) {
23245 + u32 i = 0;
23249 + for (i = 0; i < num_zones; i++)
23250 + if (strcmp(hisi_zone[i].name, name) == 0) {
23264 + u32 i = 0;
23269 + for (i = 0; i < num_zones; i++)
23270 + if (strcmp(hisi_zone[i].name, name) == 0) {
23286 + int ret = 0;
23288 + if (use_bootargs == 0) {
23293 + for (i = 0; i < num_zones; i++) {
23295 + hisi_zone[i].phys_start, 0, &cma, true);
23315 + return 0;
23359 + because DMA for 0xFFC one-time largest data transfers;
23378 @@ -0,0 +1,1451 @@
23420 +#define HIBVT_I2C_GLB 0x0
23421 +#define HIBVT_I2C_SCL_H 0x4
23422 +#define HIBVT_I2C_SCL_L 0x8
23423 +#define HIBVT_I2C_DATA1 0x10
23424 +#define HIBVT_I2C_TXF 0x20
23425 +#define HIBVT_I2C_RXF 0x24
23426 +#define HIBVT_I2C_CMD_BASE 0x30
23427 +#define HIBVT_I2C_LOOP1 0xb0
23428 +#define HIBVT_I2C_DST1 0xb4
23429 +#define HIBVT_I2C_LOOP2 0xb8
23430 +#define HIBVT_I2C_DST2 0xbc
23431 +#define HIBVT_I2C_TX_WATER 0xc8
23432 +#define HIBVT_I2C_RX_WATER 0xcc
23433 +#define HIBVT_I2C_CTRL1 0xd0
23434 +#define HIBVT_I2C_CTRL2 0xd4
23435 +#define HIBVT_I2C_STAT 0xd8
23436 +#define HIBVT_I2C_INTR_RAW 0xe0
23437 +#define HIBVT_I2C_INTR_EN 0xe4
23438 +#define HIBVT_I2C_INTR_STAT 0xe8
23443 +#define GLB_EN_MASK BIT(0)
23449 + * I2C Timing CMD Register -- HIBVT_I2C_CMD_BASE + n * 4 (n = 0, 1, 2, ... 31)
23451 +#define CMD_EXIT 0x0
23452 +#define CMD_TX_S 0x1
23453 +#define CMD_TX_D1_2 0x4
23454 +#define CMD_TX_D1_1 0x5
23455 +#define CMD_TX_FIFO 0x9
23456 +#define CMD_RX_FIFO 0x12
23457 +#define CMD_RX_ACK 0x13
23458 +#define CMD_IGN_ACK 0x15
23459 +#define CMD_TX_ACK 0x16
23460 +#define CMD_TX_NACK 0x17
23461 +#define CMD_JMP1 0x18
23462 +#define CMD_JMP2 0x19
23463 +#define CMD_UP_TXF 0x1d
23464 +#define CMD_TX_RS 0x1e
23465 +#define CMD_TX_P 0x1f
23470 +#define CTRL1_CMD_START_MASK BIT(0)
23471 +#define CTRL1_DMA_OP_MASK (0x3 << 8)
23472 +#define CTRL1_DMA_R (0x3 << 8)
23473 +#define CTRL1_DMA_W (0x2 << 8)
23485 +#define INTR_ABORT_MASK (BIT(0) | BIT(11))
23493 +#define INTR_ALL_MASK GENMASK(31, 0)
23500 +#define I2C_WAIT_TIMEOUT 0x400
23530 +#define FORCE_SDA_OEN_SHIFT (0)
23539 + hibvt_i2c_cfg_irq(i2c, 0);
23542 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) |
23543 + (0x1 << FORCE_SDA_OEN_SHIFT);
23546 + time_cnt = 0;
23548 + for (index = 0; index < 9; index++) {
23549 + val = (0x1 << GPIO_MODE_SHIFT) | 0x1;
23554 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) |
23555 + (0x1 << FORCE_SDA_OEN_SHIFT);
23568 + } while (!(val & (0x1 << CHECK_SDA_IN_SHIFT)));
23570 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) |
23571 + (0x1 << FORCE_SDA_OEN_SHIFT);
23574 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT);
23579 + val = (0x1 << GPIO_MODE_SHIFT) | (0x1 << FORCE_SCL_OEN_SHIFT) |
23580 + (0x1 << FORCE_SDA_OEN_SHIFT);
23584 + val = (0x1 << FORCE_SCL_OEN_SHIFT) | 0x1;
23635 + dev_dbg(i2c->dev, "hii2c reg: offset=0x%x, cmd=0x%x...\n",
23651 + addr = ((msg->addr & 0x300) << 1) | 0xf000;
23656 + addr |= msg->addr & 0xff;
23658 + addr = (msg->addr & 0x7f) << 1;
23680 + unsigned int time_cnt = 0;
23686 + return 0;
23693 + dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
23700 + unsigned int time_cnt = 0;
23706 + return 0;
23713 + dev_err(i2c->dev, "wait rx no empty timeout, RIS: 0x%x, SR: 0x%x\n",
23720 + unsigned int time_cnt = 0;
23726 + dev_err(i2c->dev, "wait idle abort!, RIS: 0x%x\n",
23732 + return 0;
23739 + dev_err(i2c->dev, "wait idle timeout, RIS: 0x%x, SR: 0x%x\n",
23786 + val |= ((0xa << GLB_SDA_HOLD_SHIFT) & GLB_SDA_HOLD_MASK);
23820 + int offset = 0;
23822 + if (i2c->msg_idx == 0)
23828 + if (i2c->msg_idx == 0) {
23879 + int offset = 0;
23882 + if (i2c->msg_idx == 0) {
23889 + if (i2c->msg_idx == 0) {
23916 + for(i = 0; i < reg_data_width - 1; i++){
23927 + if(((msg->len / reg_data_width) - 1) > 0){
23928 + writel(0, i2c->base + HIBVT_I2C_DST2);
23973 + int status = 0;
23978 + writel(0x1, i2c->base + HIBVT_I2C_TX_WATER);
24015 + int chan, val, status = 0;
24021 + writel(0x1, i2c->base + HIBVT_I2C_TX_WATER);
24048 + int status = 0;
24053 + writel(0x0, i2c->base + HIBVT_I2C_RX_WATER);
24100 + return 0;
24109 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
24170 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
24224 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
24234 + i2c->msg_buf_ptr = 0;
24271 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
24281 + i2c->msg_buf_ptr = 0;
24321 + dev_dbg(i2c->dev, "%s RIS: 0x%x\n", __func__, irq_status);
24329 + dev_err(i2c->dev, "irq handle abort, RIS: 0x%x\n",
24359 + i2c->status = 0;
24378 + dev_dbg(i2c->dev, "[%s,%d]msg->flags=0x%x, len=0x%x\n",
24382 + i2c->msg_buf_ptr = 0;
24403 + if (timeout == 0) {
24428 + if (!msgs || (num <= 0)) {
24429 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
24437 + i2c->msg_idx = 0;
24446 + } else if (i2c->irq >= 0) {
24448 + if (i2c->irq >= 0) {
24464 + if (!status || i2c->msg_idx > 0)
24481 + if (!msgs || (num <= 0)) {
24482 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
24488 + i2c->msg_idx = 0;
24505 + if (!status || i2c->msg_idx > 0)
24517 + if (!msgs || (num <= 0)) {
24518 + dev_err(i2c->dev, "msgs == NULL || num <= 0, Invalid argument!\n");
24524 + i2c->msg_idx = 0;
24542 + if (!status || i2c->msg_idx > 0) {
24582 + (count < 0)) {
24587 + if ((client->addr > 0x3ff) ||
24588 + (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) {
24614 + if ((client->addr > 0x3ff)
24615 + || (((client->flags & I2C_M_TEN) == 0) && (client->addr > 0x7f))) {
24624 + if ((!buf)||(count < 0)) {
24625 + printk(KERN_ERR "buf == NULL || count < 0, Invalid argument!\n");
24657 + if ((msgs[0].addr > 0x3ff) ||
24658 + (((msgs[0].flags & I2C_M_TEN) == 0) && (msgs[0].addr > 0x7f))) {
24659 + printk(KERN_ERR "msgs[0] dev address out of range\n");
24663 + if ((msgs[1].addr > 0x3ff) ||
24664 + (((msgs[1].flags & I2C_M_TEN) == 0) && (msgs[1].addr > 0x7f))) {
24706 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
24736 + i2c->irq = platform_get_irq(pdev, 0);
24762 + return 0;
24776 + return 0;
24788 + return 0;
24800 + return 0;
24864 + if(msg.len == 0 || reg_data_width > msg.len || msg.len % reg_data_width != 0){
24871 + return 0;
24896 + return 0;
24944 + for (idx = 0; idx < DIS_IRQ_CNT; idx++) {
24947 + dis_irq_handle[idx].handle(((irqstat >> 10) & 0x7),
24953 + return 0;
25016 +#define GIC_DIST_INIT_FLAG 0x47444946
25017 +#define GIC_DIST_INIT_FLAG_OFFSET 0x0130
25018 + /* 0x47444946('G''D''I''F') is abbreviation of GIC_DIST_INIT_FLAG. */
25021 + sysctrl_reg_base = of_iomap(np, 0);
25051 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
25063 packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
25105 @@ -0,0 +1,134 @@
25200 + ret = mfd_add_devices(dev, 0, hisi_fmc_devs,
25201 + ARRAY_SIZE(hisi_fmc_devs), NULL, 0, NULL);
25207 + return 0;
25219 + return 0;
25263 + mmc_cmd.arg = data.blocks & 0x0000FFFF;
25274 index b5f3f160c..0b0e367bc 100644
25293 host->ops->get_cd(host) == 0) {
25395 + err = mmc_send_io_op_cond(host, 0, &ocr);
25407 + return 0;
25546 cqhci_set_irqs(cq_host, 0);
25551 cqhci_writel(cq_host, 0, CQHCI_CTL);
25621 #define CQHCI_SSC1 0x40
25626 +#define SEND_QSR_INTERVAL 0x70001
25632 #define CQHCI_DAT_ADDR_LO(x) (((x) & 0xFFFFFFFF) << 32)
25633 #define CQHCI_DAT_ADDR_HI(x) (((x) & 0xFFFFFFFF) << 0)
25635 +#define SYNOPSYS_DMA_LIMIT 0x8000000
25642 #define CQHCI_QUIRK_SHORT_TXFR_DESC_SZ 0x1
25643 +#define CQHCI_QUIRK_TXFR_DESC_SZ_SPLIT 0x2
25652 @@ -0,0 +1,23 @@
25681 @@ -0,0 +1,2 @@
25689 @@ -0,0 +1,2580 @@
25795 +#define PWR_CTRL0_REG 0x12090000
25796 +#define GPIO_AT_PMC_ENABLE_BIT 0x80
25797 +#define REG_SLEEP_TIME_MS 0x30
25804 +unsigned int slot_index = 0;
25868 + reg_value &= ~(0x1 << port);
25870 + reg_value |= (0x1 << port);
25891 + * 0: card on
25902 + card_status = 0;
25909 + * 0: card read/write
25917 +static int tuning_reset_flag = 0;
25921 + int wait_retry_count = 0;
25923 + unsigned int reg_data = 0;
25932 + * start_cmd = 0 means MMC Host controller has loaded registers
25936 + if ((reg_data & START_CMD) == 0)
25937 + return 0;
25993 + cmd_reg.bits.cmd_index = 0;
25994 + cmd_reg.bits.data_transfer_expected = 0;
25996 + cmd_reg.bits.response_expect = 0;
25997 + cmd_reg.bits.send_auto_stop = 0;
25998 + cmd_reg.bits.wait_prvdata_complete = 0;
25999 + cmd_reg.bits.check_response_crc = 0;
26006 + if (himci_wait_cmd(host) != 0) {
26010 + return 0;
26037 + if (reg_value > 0xFF)
26038 + reg_value = 0xFF;
26049 + clk_cmd.bits.cmd_index = 0;
26050 + clk_cmd.bits.data_transfer_expected = 0;
26051 + clk_cmd.bits.response_expect = 0;
26053 + if (himci_wait_cmd(host) != 0)
26066 + unsigned int tmp_reg = 0;
26085 + himci_writel(0x4, host->base + MCI_CLKSRC);
26089 + tmp_reg = 0;
26100 + host->pending_events = 0;
26119 + tmp_reg = 0;
26123 + host->error_count = 0;
26124 + host->data_error_count = 0;
26131 + unsigned int detect_retry_count = 0;
26136 + for (i = 0; i < 5; i++) {
26140 + if ((status[0] == status[1])
26141 + && (status[0] == status[2])
26142 + && (status[0] == status[3])
26143 + && (status[0] == status[4]))
26152 + curr_status = status[0];
26164 + mmc_detect_change(host->mmc, 0);
26211 + unsigned int ret = 0;
26240 + himci_trace(2, "host->dma_paddr is 0x%08lx,host->dma_vaddr is 0x%08lx\n",
26246 + des_cnt = 0;
26248 + for (i = 0; i < host->dma_sg_num; i++) {
26251 + himci_trace(2, "sg[%d] sg_length is 0x%08X, " \
26252 + "sg_phyaddr is 0x%08X\n", \
26264 + if (sg_length >= 0x1000) {
26265 + des[des_cnt].idmac_des_buf_size = 0x1000;
26266 + sg_length -= 0x1000;
26267 + sg_phyaddr += 0x1000;
26271 + sg_length = 0;
26274 + himci_trace(2, "des[%d] vaddr is 0x%08X", i,
26276 + himci_trace(2, "des[%d].idmac_des_ctrl is 0x%08X",
26278 + himci_trace(2, "des[%d].idmac_des_buf_size is 0x%08X",
26280 + himci_trace(2, "des[%d].idmac_des_buf_addr 0x%08X",
26282 + himci_trace(2, "des[%d].idmac_des_next_addr is 0x%08X",
26289 + des[0].idmac_des_ctrl |= DMA_DES_FIRST_DES;
26291 + des[des_cnt - 1].idmac_des_next_addr = 0;
26308 + himci_trace(4, "arg_reg 0x%x, val 0x%x", MCI_CMDARG, cmd->arg);
26313 + cmd_regs.bits.transfer_mode = 0;
26318 + cmd_regs.bits.read_write = 0;
26320 + cmd_regs.bits.data_transfer_expected = 0;
26321 + cmd_regs.bits.transfer_mode = 0;
26322 + cmd_regs.bits.read_write = 0;
26325 + cmd_regs.bits.send_auto_stop = 0;
26334 + cmd_regs.bits.wait_prvdata_complete = 0;
26336 + cmd_regs.bits.stop_abort_cmd = 0;
26337 + cmd_regs.bits.wait_prvdata_complete = 0;
26339 + cmd_regs.bits.stop_abort_cmd = 0;
26345 + cmd_regs.bits.response_expect = 0;
26346 + cmd_regs.bits.response_length = 0;
26347 + cmd_regs.bits.check_response_crc = 0;
26352 + cmd_regs.bits.response_length = 0;
26363 + cmd_regs.bits.response_length = 0;
26364 + cmd_regs.bits.check_response_crc = 0;
26373 + himci_trace(3, "cmd->opcode = %d cmd->arg = 0x%X\n",
26381 + cmd_regs.bits.send_initialization = 0;
26386 + cmd_regs.bits.volt_switch = 0;
26391 + cmd_regs.bits.update_clk_reg_only = 0;
26395 + himci_trace(4, "cmd_reg 0x%x, val 0x%x\n", MCI_CMD, cmd_regs.cmd_arg);
26397 + if (himci_wait_cmd(host) != 0) {
26401 + return 0;
26434 + for (i = 0; i < 4; i++) {
26437 + MCI_RESP3 - i * 0x4);
26443 + MCI_RESP0 + i * 0x4);
26448 + himci_trace(3, "irq cmd status stat = 0x%x is timeout error!",
26452 + himci_trace(3, "irq cmd status stat = 0x%x is response error!",
26458 + if ((cmd->resp[0] & CMD_ERRORS) && !host->is_tuning) {
26461 + himci_trace(5, "The status of the card is abnormal, cmd->resp[0]: %x",
26462 + cmd->resp[0]);
26468 + if ((cmd->resp[0] & R1_READY_FOR_DATA) && (R1_CURRENT_STATE(cmd->resp[0]) ==
26472 + himci_trace(5, "The status of the card is abnormal, cmd->resp[0]: %x",
26473 + cmd->resp[0]);
26492 + himci_trace(3, "irq data status stat = 0x%x is timeout error!",
26497 + himci_trace(3, "irq data status stat = 0x%x is data error!",
26504 + data->bytes_xfered = 0;
26511 + unsigned int cmd_retry_count = 0;
26513 + unsigned int cmd_irq_reg = 0;
26533 + return 0;
26539 + return 0;
26545 + cmd_retry_count = 0;
26553 + unsigned int i = 0;
26554 + for (i = 0; i < 4; i++) {
26557 + i * 0x4);
26559 + pr_err("%d : 0x%x\n", i, cmd->resp[i]);
26576 + unsigned int cmd_retry_count = 0;
26578 + unsigned int cmd_irq_reg = 0;
26595 + return 0;
26601 + cmd_retry_count = 0;
26637 + if (((time <= 0)
26641 + himci_trace(5, "wait data request complete is timeout! 0x%08X",
26650 + return 0;
26656 + unsigned int card_retry_count = 0;
26658 + unsigned int card_status_reg = 0;
26669 + return 0;
26674 + card_retry_count = 0;
26695 + int byte_cnt = 0;
26696 + int fifo_count = 0;
26697 + int ret = 0;
26707 + host->irq_status = 0;
26750 + himci_writel(0, host->base + MCI_BYTCNT);
26751 + himci_writel(0, host->base + MCI_BLKSIZ);
26793 + unsigned int wait_retry_count = 0;
26801 + himci_trace(3, "data status = 0x%x is error!", stat);
26884 + himci_set_drv_cap(host, 0);
26885 + return 0;
26914 + return 0;
26927 + return 0;
26934 + * sequence by setting S18R to 0.
26955 + himci_error("voltage failed, retrying with S18R set to 0\n");
26959 + return 0;
26974 + struct mmc_command cmd = {0};
26979 + err = mmc_wait_for_cmd(host, &cmd, 0);
27004 + void __iomem *tmp_reg = 0;
27006 + if (host->devid == 0)
27007 + tmp_reg = crg_ctrl + 0x14c;
27009 + tmp_reg = crg_ctrl + 0x164;
27011 + tmp_reg = crg_ctrl + 0x158;
27017 + himci_writel(0x80001, tmp_reg);
27027 + void __iomem *tmp_reg = 0;
27029 + if (host->devid == 0)
27030 + tmp_reg = crg_ctrl + 0x14c;
27032 + tmp_reg = crg_ctrl + 0x164;
27034 + tmp_reg = crg_ctrl + 0x158;
27051 + struct mmc_command cmd = {0};
27066 + return 0;
27071 + int err = 0;
27085 + tuning_reset_flag = 0;
27087 + if (cmd_count == 0) {
27102 + u32 regval = 0;
27103 + void __iomem *reg_sap_dll_status = 0;
27105 + if (host->devid == 0)
27106 + reg_sap_dll_status = crg_ctrl + 0x150;
27108 + reg_sap_dll_status = crg_ctrl + 0x168;
27110 + reg_sap_dll_status = crg_ctrl + 0x15c;
27113 + return 0;
27117 + return (regval & 0xff);
27123 + void __iomem *reg_sap_dll_ctrl = 0;
27125 + if (host->devid == 0)
27126 + reg_sap_dll_ctrl = crg_ctrl + 0x14c;
27128 + reg_sap_dll_ctrl = crg_ctrl + 0x164;
27130 + reg_sap_dll_ctrl = crg_ctrl + 0x158;
27136 + regval &= ~(0xFF << 8);
27167 + u32 found = 0;
27170 + u32 startp_init = 0;
27171 + u32 endp_init = 0;
27172 + u32 phaseoffset = 0;
27173 + u32 totalphases = 0;
27175 + u8 mdly_tap_flag = 0;
27176 + int prev_err = 0, err = 0;
27218 + err = 0;
27245 + err = 0;
27250 + phaseoffset = 0;
27251 + for (index = 0; index < edge_f2p; index++) {
27272 + err = 0;
27284 + if (totalphases == 0) {
27301 + return 0;
27318 + host->pending_events = 0;
27334 + u32 found = 0, prefound = 0;
27336 + u32 edge_num = 0;
27341 + edge_p2f = 0;
27346 + for (index = 0; index < HIMCI_PHASE_SCALE; index++) {
27369 + if ((edge_p2f != 0) && (edge_f2p != phase_num))
27373 + found = 0;
27376 + if ((edge_p2f == 0) && (edge_f2p == phase_num)) {
27395 +#if 0
27400 + unsigned int found = 0;
27401 + unsigned int prev_found = 0;
27402 + unsigned int prev_point = 0;
27404 + unsigned int phase = 0;
27410 + for (index = 0; index < HIMCI_PHASE_SCALE; index++) {
27420 + himci_trace(3, "try phase:%02d, found:0x%x\n", index, found);
27425 + if (index != 0)
27433 + found = 0;
27440 + return 0;
27468 + return 0;
27475 + * 1.Set a phase shift of 0° on cclk_in_sample
27507 + host->is_tuning = 0;
27515 + unsigned int err = 0;
27516 + unsigned int found = 0; /* identify if we have found a valid phase */
27529 + himci_writel(0x1, host->base + MCI_CARDTHRCTL);
27531 + himci_trace(3, "start sd3.0 phase tuning...");
27537 + count = 0;
27566 + err = 0;
27570 + host->is_tuning = 0;
27586 + phase = (phase < 0) ? (HIMCI_PHASE_SCALE + phase) : phase;
27598 + return 0;
27626 + int ret = 0;
27684 + himci_set_drv_cap(host, 0);
27714 + return 0;
27772 + memset(c_info, 0, sizeof(struct card_info));
27789 + return 0;
27808 + u32 state = 0;
27809 + int handle = 0;
27810 + u32 mstate = 0;
27870 + if (host->devid == 0 || host->devid == 1)
27872 + return 0;
27882 + pwr_ctrl = ioremap(PWR_CTRL0_REG, 0x4);
27900 + int ret = 0, irq;
27930 + crg_ctrl = ioremap(0x12010000, 0x1000);
27937 + misc_ctrl_1 = ioremap(0x12030004, 0x4);
27945 + regval &= ~(0x1 << 2);
27950 + host_ioaddr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
27988 + host->port = 0;
27990 + host->port = 0;
28035 + timer_setup(&host->timer, himci_detect_card, 0);
28040 + irq = platform_get_irq(pdev, 0);
28041 + if (irq < 0) {
28047 + ret = request_irq(irq, hisd_irq, 0, DRIVER_NAME, host);
28054 + return 0;
28099 + return 0;
28112 + himci_writel(0, host->base + MCI_IDINTEN);
28113 + himci_writel(0, host->base + MCI_INTMASK);
28127 + int ret = 0;
28144 + int ret = 0;
28191 + if (slot >= HIMCI_SLOT_NUM || slot < 0) {
28275 @@ -0,0 +1,156 @@
28284 + 0 - all message
28294 +#define POWER_OFF 0
28296 +#define FORCE_DISABLE 0
28299 +#define CARD_PLUGED 0
28302 +#define DISABLE 0
28321 +} while (0)
28330 +} while (0)
28336 +} while (0)
28339 + himci_trace(1, "readl(0x%04X) = 0x%08X", (unsigned int)(uintptr_t)addr, reg); \
28343 + himci_trace(1, "writel(0x%04X) = 0x%08X", (unsigned int)(uintptr_t)addr, \
28345 +} while (0)
28359 +#define CARD_DISCONNECT 0
28384 +#define HIMCI_PEND_DTO_B (0)
28437 @@ -0,0 +1,160 @@
28457 +#define TUNING_START_PHASE 0
28460 +#define DRV_PHASE_DFLT (0x4<<23)
28461 +#define SMPL_PHASE_DFLT (0x0<<16)
28464 +#define REG_CTRL_EMMC_START (0x10ff0000 + 0x0)
28466 +#define REG_CTRL_SDIO0_START (0x10ff0000 + 0x24)
28468 +#define REG_CTRL_SDIO1_START (0x112f0000 + 0x8)
28473 +static unsigned int emmc_hs200_drv[] = {0x2b0, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
28474 +static unsigned int emmc_hs_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
28475 +static unsigned int emmc_ds_drv[] = {0x6b0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
28476 +static unsigned int emmc_ds_400k_drv[] = {0x6c0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
28478 +static unsigned int sdio0_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
28479 +static unsigned int sdio0_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
28480 +static unsigned int sdio0_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
28481 +static unsigned int sdio0_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
28482 +static unsigned int sdio0_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
28483 +static unsigned int sdio0_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
28485 +static unsigned int sdio1_sdr104_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
28486 +static unsigned int sdio1_sdr50_drv[] = {0x290, 0x1c0, 0x1c0, 0x1c0, 0x1c0, 0x1c0};
28487 +static unsigned int sdio1_sdr25_drv[] = {0x6b0, 0x5d0, 0x5d0, 0x5d0, 0x5d0, 0x5d0};
28488 +static unsigned int sdio1_sdr12_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
28489 +static unsigned int sdio1_hs_drv[] = {0x6d0, 0x5f0, 0x5f0, 0x5f0, 0x5f0, 0x5f0};
28490 +static unsigned int sdio1_ds_drv[] = {0x6b0, 0x5e0, 0x5e0, 0x5e0, 0x5e0, 0x5e0};
28501 + if (devid == 0) {
28541 + (size_t)0x1000);
28542 + for (i = start, j = 0; j < 6; i = i + 4, j++) {
28550 + reg = reg & (~(0x7f0));
28557 +#define DRV_PHASE_180 (0x4<<23)
28558 +#define DRV_PHASE_135 (0x3<<23)
28559 +#define DRV_PHASE_90 (0x2<<23)
28561 +#define SMP_PHASE_45 (0x1<<16)
28562 +#define SMP_PHASE_0 (0x0<<16)
28571 + if (devid == 0) {
28603 @@ -0,0 +1,246 @@
28641 + const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
28680 + unsigned int scale = 0;
28685 + if (0 < tmp) {
28711 + unsigned int clock_value = 0;
28726 + for (index_mci = 0; index_mci < HIMCI_SLOT_NUM; index_mci++) {
28778 + (0x00 == speed_class) ? "0" :
28779 + (0x01 == speed_class) ? "2" :
28780 + (0x02 == speed_class) ? "4" :
28781 + (0x03 == speed_class) ? "6" :
28782 + (0x04 == speed_class) ? "10" :
28785 + (0x00 == grade_speed_uhs) ?
28786 + "Less than 10MB/sec(0h)" :
28787 + (0x01 == grade_speed_uhs) ?
28818 + return 0;
28830 + proc_stats_entry = proc_create_single_data(MCI_STATS_PROC, 0,
28837 + return 0;
28848 + return 0;
28855 @@ -0,0 +1,36 @@
28897 @@ -0,0 +1,241 @@
28918 +#define HI_MCI_IO_SIZE 0x1000
28920 +#define MCI_CTRL 0x00
28921 +#define MCI_PWREN 0x04
28922 +#define MCI_CLKDIV 0x08
28923 +#define MCI_CLKSRC 0x0C
28924 +#define MCI_CLKENA 0x10
28925 +#define MCI_TIMEOUT 0x14
28926 +#define MCI_CTYPE 0x18
28927 +#define MCI_BLKSIZ 0x1c
28928 +#define MCI_BYTCNT 0x20
28929 +#define MCI_INTMASK 0x24
28930 +#define MCI_CMDARG 0x28
28931 +#define MCI_CMD 0x2C
28932 +#define MCI_RESP0 0x30
28933 +#define MCI_RESP1 0x34
28934 +#define MCI_RESP2 0x38
28935 +#define MCI_RESP3 0x3C
28936 +#define MCI_MINTSTS 0x40
28937 +#define MCI_RINTSTS 0x44
28938 +#define MCI_STATUS 0x48
28939 +#define MCI_FIFOTH 0x4C
28940 +#define MCI_CDETECT 0x50
28941 +#define MCI_WRTPRT 0x54
28942 +#define MCI_GPIO 0x58
28943 +#define MCI_TCBCNT 0x5C
28944 +#define MCI_TBBCNT 0x60
28945 +#define MCI_DEBNCE 0x64
28946 +#define MCI_USRID 0x68
28947 +#define MCI_VERID 0x6C
28948 +#define MCI_HCON 0x70
28949 +#define MCI_UHS_REG 0x74
28950 +#define MCI_RESET_N 0x78
28951 +#define MCI_BMOD 0x80
28952 +#define MCI_DBADDR 0x88
28953 +#define MCI_IDSTS 0x8C
28954 +#define MCI_IDINTEN 0x90
28955 +#define MCI_DSCADDR 0x94
28956 +#define MCI_BUFADDR 0x98
28957 +#define MCI_CARDTHRCTL 0x100
28958 +#define MCI_UHS_REG_EXT 0x108
28960 +#define MCI_TUNING_CTRL 0x118
28962 +/* MCI_IDSTS(0x8c) detals */
28963 +#define CMD_LOCK_ERR (0x1 << 29)
28964 +#define OWNBIT_ERR (0x1 << 28)
28965 +#define QUEUE_OVERFLOW (0x1 << 27)
28966 +#define RESP_CHECK_ERR (0x1 << 26)
28967 +#define PACKET_INT (0x1 << 25)
28968 +#define PACKET_TO_INT (0x1 << 24)
28969 +#define AUTO_STOP_ERR (0x1 << 23)
28970 +#define QUEUE_FULL (0x1 << 22)
28971 +#define QUEUE_EMPTY (0x1 << 21)
28974 +#define CES (0x1 << 5)
28975 +#define DU (0x1 << 4)
28976 +#define FBE (0x1 << 2)
28978 +/* MCI_BMOD(0x80) details */
28979 +#define BMOD_SWR (0x1 << 0)
28980 +#define BURST_INCR (0x1 << 1)
28981 +#define BMOD_DMA_EN (0x1 << 7)
28982 +#define BURST_8 (0x2 << 8)
28983 +#define BURST_16 (0x3 << 8)
28985 +#define DMA_BUFFER (0x2000)
28994 +/* MCI_CTRL(0x00) details */
28995 +#define CTRL_RESET (1 << 0)
29001 +/* MCI_CLKENA(0x10) details */
29002 +#define CCLK_ENABLE (0x1 << 0)
29003 +#define CCLK_LOW_POWER (0x1 << 16)
29005 +/* MCI_TIMEOUT(0x14) details: */
29007 +#define DATA_TIMEOUT (0xffffff << 8)
29008 +/* bit 7-0: response timeout param */
29009 +#define RESPONSE_TIMEOUT 0xff
29011 +/* MCI_CTYPE(0x18) details */
29012 +#define CARD_WIDTH_0 (0x1 << 16)
29013 +#define CARD_WIDTH_1 (0x1 << 0)
29015 +/* MCI_INTMASK(0x24) details:
29018 +#define ALL_INT_MASK 0x1ffff
29019 +#define DTO_INT_MASK (0x1 << 3)
29020 +#define SDIO_INT_MASK (0x1 << 16)
29022 +/* MCI_UHS_REG_EXT(0x108) details */
29025 +#define CLK_SMPL_PHS_MASK (0x7 << 16)
29029 +#define CLK_DRV_PHS_MASK (0x7 << 23)
29030 +#define DEFAULT_PHASE 0x1050000
29032 +/* MCI_CMD(0x2c) details:
29035 +#define START_CMD (0x1<<31)
29037 +/* MCI_INTSTS(0x44) details */
29040 +#define SDIO_INT_STATUS (0x1 << 16)
29043 +#define EBE_INT_STATUS (0x1 << 15)
29046 +#define ACD_INT_STATUS (0x1 << 14)
29049 +#define SBE_INT_STATUS (0x1 << 13)
29052 +#define HLE_INT_STATUS (0x1 << 12)
29055 +#define FRUN_INT_STATUS (0x1 << 11)
29058 +#define HTO_INT_STATUS (0x1 << 10)
29061 +#define VOLT_SWITCH_INT_STATUS (0x1 << 10)
29064 +#define DRTO_INT_STATUS (0x1 << 9)
29067 +#define RTO_INT_STATUS (0x1 << 8)
29070 +#define DCRC_INT_STATUS (0x1 << 7)
29073 +#define RCRC_INT_STATUS (0x1<<6)
29076 +#define RXDR_INT_STATUS (0x1<<5)
29079 +#define TXDR_INT_STATUS (0x1<<4)
29082 +#define DTO_INT_STATUS (0x1<<3)
29085 +#define CD_INT_STATUS (0x1<<2)
29088 +#define RE_INT_STATUS (0x1<<1)
29095 +/* MCI_RINTSTS(0x44) details:bit 16-1: clear
29099 +#define ALL_INT_CLR 0x1efff
29100 +#define ALL_SD_INT_CLR 0xefff
29102 +/* MCI_STATUS(0x48) details */
29103 +#define DATA_BUSY (0x1<<9)
29105 +/* MCI_FIFOTH(0x4c) details */
29106 +#define BURST_SIZE (0x6<<28)
29107 +#define RX_WMARK (0x7f<<16)
29108 +#define TX_WMARK (0x80)
29110 +/* MCI_CDETECT(0x50) details */
29111 +#define HIMCI_CARD0 (0x1<<0)
29113 +/* MCI_GPIO(0x58) details */
29114 +#define DTO_FIX_BYPASS (0x1<<23)
29115 +#define CMD_OUT_EN_FIX_BYPASS (0x1<<8)
29117 +/* MCI_UHS_REG(0x74) details */
29118 +#define HI_SDXC_CTRL_VDD_180 (0x1<<0)
29119 +#define HI_SDXC_CTRL_DDR_REG (0x1<<16)
29121 +/* MCI_RESET_N(0x78) details */
29122 +#define MMC_RST_N (0x1<<0)
29124 +/* MCI_CARDTHRCTL(0x100) details */
29128 +#define RW_THRESHOLD_SIZE (0x2000005)
29130 +#define RW_THRESHOLD_SIZE (0x2000001)
29133 +/* MCI_TUNING_CTRL(0x118) details */
29134 +#define HW_TUNING_EN (0x1 << 0)
29135 +#define EDGE_CTRL (0x1 << 1)
29136 +#define FOUND_EDGE (0x1 << 5)
29144 @@ -0,0 +1,301 @@
29199 + const u32 mask = ((size < BIT_WIDTH) ? 1 << size : 0) - 1;
29200 + const int off = 0x3 - ((start) / BIT_WIDTH);
29223 + unsigned int scale = 0;
29228 + if (tmp > 0) {
29254 + unsigned int clock_value = 0;
29270 + for (index_mci = 0; index_mci < MCI_SLOT_NUM; index_mci++) {
29322 + (speed_class == 0x00) ? "0" :
29323 + (speed_class == 0x01) ? "2" :
29324 + (speed_class == 0x02) ? "4" :
29325 + (speed_class == 0x03) ? "6" :
29326 + (speed_class == 0x04) ? "10" :
29329 + (grade_speed_uhs == 0x00) ?
29330 + "Less than 10MB/sec(0h)" :
29331 + (grade_speed_uhs == 0x01) ?
29366 + if (*pos == 0)
29384 + return 0;
29426 + 0, proc_mci_dir, &mci_stats_proc_ops);
29433 + return 0;
29444 + return 0;
29451 @@ -0,0 +1,50 @@
29507 @@ -0,0 +1,783 @@
29548 + if (of_property_read_u32(np, "bus-width", &bus_width) == 0) {
29562 + return 0;
29622 + if (timeout == 0) {
29647 + count = 0;
29679 + host->is_tuning = 0;
29691 + int win_max = 0;
29693 + for (i = 0; i < PHASE_SCALE; i++) {
29694 + if ((candidates & 0x3) == 0x2)
29697 + if ((candidates & 0x3) == 0x1) {
29740 + unsigned int candidates = 0;
29745 + for (sample = 0; sample < PHASE_SCALE; sample++) {
29753 + candidates |= (0x1 << sample);
29756 + pr_info("%s: tuning done! candidates 0x%X: ",
29769 + return 0;
29795 + unsigned int prev_found = 0;
29798 + unsigned int fall_updat_flag = 0;
29800 + int prev_err = 0;
29805 + start = 0;
29810 + for (index = 0; index <= end; index++) {
29885 + return 0;
29923 + sdhci_writel(host, 0x0, SDHCI_EMMC_HW_RESET);
29925 + sdhci_writel(host, 0x1, SDHCI_EMMC_HW_RESET);
29936 + if ((slot >= MCI_SLOT_NUM) || (slot <= 0)) {
29947 + mmc_detect_change(mmc, 0);
29948 + return 0;
29983 + int cmd_error = 0;
29984 + int data_error = 0;
29991 + return 0;
30067 + sdhci_hisi_controller_v4_enable(mmc_priv(mmc), 0);
30120 + cq_host->mmio = host->ioaddr + 0x180;
30143 + return 0;
30195 + return 0;
30213 + 0xffffffff);
30224 + return 0;
30233 + return 0;
30241 + return 0;
30296 @@ -0,0 +1,126 @@
30362 +#define SDHCI_CTRL_HOST_VER4_ENABLE 0x1000
30363 +#define SDHCI_CLOCK_PLL_EN 0x0008
30364 +#define SDHCI_CTRL_64BIT_ADDR 0x2000
30365 +#define SDHCI_CAN_DO_ADMA3 0x08000000
30368 +#define SDHCI_MSHC_CTRL 0x508
30369 +#define SDHCI_CMD_CONFLIT_CHECK 0x01
30371 +#define SDHCI_AXI_MBIIU_CTRL 0x510
30372 +#define SDHCI_GM_WR_OSRC_LMT_MASK (0x7 << 24)
30374 +#define SDHCI_GM_RD_OSRC_LMT_MASK (0x7 << 16)
30376 +#define SDHCI_UNDEFL_INCR_EN 0x1
30378 +#define SDHCI_EMMC_CTRL 0x52C
30379 +#define SDHCI_CARD_IS_EMMC 0x0001
30380 +#define SDHCI_ENH_STROBE_EN 0x0100
30382 +#define SDHCI_EMMC_HW_RESET 0x534
30384 +#define SDHCI_AT_CTRL 0x540
30385 +#define SDHCI_SAMPLE_EN 0x00000010
30387 +#define SDHCI_AT_STAT 0x544
30388 +#define SDHCI_PHASE_SEL_MASK 0x000000FF
30390 +#define SDHCI_MULTI_CYCLE 0x54C
30391 +#define SDHCI_FOUND_EDGE (0x1 << 11)
30392 +#define SDHCI_EDGE_DETECT_EN (0x1 << 8)
30393 +#define SDHCI_DOUT_EN_F_EDGE (0x1 << 6)
30394 +#define SDHCI_DATA_DLY_EN (0x1 << 3)
30395 +#define SDHCI_CMD_DLY_EN (0x1 << 2)
30451 host->clock = 0;
30498 + attr_addr[0] = cpu_to_le32(attr);
30499 + reg_addr[0] = cpu_to_le32(reg);
30507 + attr_addr[0] = cpu_to_le32(attr);
30511 + cmd_ddr[0] = cpu_to_le64(addr);
30514 + cmd_ddr[0] = cpu_to_le32(addr);
30525 + blksz = SDHCI_MAKE_BLKSZ(0, data->blksz);
30530 + sdhci_write_cmd_table(host->cmd_table + 0x8, blksz, ADMA3_CMD_VALID); // add 0x8
30531 + sdhci_write_cmd_table(host->cmd_table + 0x10, // add 0x10
30533 + sdhci_write_cmd_table(host->cmd_table + 0x18, // add 0x18
30535 + sdhci_adma_write_desc(host, host->cmd_table + 0x20, // add 0x20
30536 + host->adma_addr, 0x0, ADMA2_LINK_VALID);
30600 if (sg_cnt <= 0) {
30638 cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
30643 + if ((cmd->resp[0] & CMD_ERRORS) && !host->is_tuning)
30650 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
30694 + memset(c_info,0,sizeof(struct card_info));
30712 + return 0;
30765 - pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
30767 + /*pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n",
30789 DBG("IRQ status 0x%08x\n", intmask);
30913 if (curr > 0) {
30955 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
30956 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
30975 #define SDHCI_INT_CARD_INT 0x00000100
30976 #define SDHCI_INT_RETUNE 0x00001000
30977 #define SDHCI_INT_CQE 0x00004000
30978 +#define SDHCI_INT_CQE 0x00004000
30979 #define SDHCI_INT_ERROR 0x00008000
30980 #define SDHCI_INT_TIMEOUT 0x00010000
30981 #define SDHCI_INT_CRC 0x00020000
30985 #define SDHCI_AUTO_CMD_STATUS 0x3C
30986 +#define SDHCI_AUTO_CMD12_NOT_EXEC 0x0001
30987 #define SDHCI_AUTO_CMD_TIMEOUT 0x00000002
30988 #define SDHCI_AUTO_CMD_CRC 0x00000004
30989 #define SDHCI_AUTO_CMD_END_BIT 0x00000008
30990 #define SDHCI_AUTO_CMD_INDEX 0x00000010
30991 +#define SDHCI_AUTO_CMD12_NOT_ISSUED 0x0080
30993 #define SDHCI_HOST_CONTROL2 0x3E
30994 #define SDHCI_CTRL_UHS_MASK 0x0007
30996 #define SDHCI_CTRL_UHS_SDR50 0x0002
30997 #define SDHCI_CTRL_UHS_SDR104 0x0003
30998 #define SDHCI_CTRL_UHS_DDR50 0x0004
30999 -#define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
31000 +#define SDHCI_CTRL_HS400 0x0007 /* Non-standard */
31001 #define SDHCI_CTRL_VDD_180 0x0008
31002 #define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
31003 #define SDHCI_CTRL_DRV_TYPE_B 0x0000
31005 #define SDHCI_CTRL_DRV_TYPE_D 0x0030
31006 #define SDHCI_CTRL_EXEC_TUNING 0x0040
31007 #define SDHCI_CTRL_TUNED_CLK 0x0080
31008 +#define SDHCI_CTRL_HOST_VER4_ENABLE 0x1000
31009 +#define SDHCI_CTRL_ADDRESSING_64BIT 0x2000
31010 +#define SDHCI_CTRL_ASYNC_INT_ENABLE 0x4000
31011 #define SDHCI_CMD23_ENABLE 0x0800
31012 #define SDHCI_CTRL_V4_MODE 0x1000
31013 #define SDHCI_CTRL_64BIT_ADDR 0x2000
31015 #define SDHCI_CAN_VDD_180 0x04000000
31016 #define SDHCI_CAN_64BIT_V4 0x08000000
31017 #define SDHCI_CAN_64BIT 0x10000000
31018 +#define SDHCI_CAN_ASYNC_INT 0x20000000
31020 #define SDHCI_CAPABILITIES_1 0x44
31021 #define SDHCI_SUPPORT_SDR50 0x00000001
31024 #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0)
31026 +#define SDHCI_ADMA3_ID_ADDR_LOW 0x78
31027 +#define SDHCI_ADMA3_ID_ADDR_HI 0x7C
31029 #define SDHCI_SLOT_INT_STATUS 0xFC
31031 #define SDHCI_HOST_VERSION 0xFE
31036 +#define SDHCI_DMA_BOUNDARY_SIZE (0x1 << 27)
31054 #define ADMA2_TRAN_VALID 0x21
31055 #define ADMA2_NOP_END_VALID 0x3
31056 #define ADMA2_END 0x2
31057 +#define ADMA2_LINK_VALID 0x31
31058 +#define ADMA3_CMD_VALID 0x9
31059 +#define ADMA3_END 0x3b
31073 +#define CARD_DISCONNECT 0
31213 @@ -0,0 +1,17 @@
31236 @@ -0,0 +1,26 @@
31268 @@ -0,0 +1,1218 @@
31326 + unsigned long clkrate = 0;
31412 + *host->epm = 0x0000;
31417 + FMC_PR(WR_DBG, "|-Set DMA_SADDR_D[0x40]%#x\n", reg);
31494 + if ((host->addr_value[0] == host->cache_addr_value[0])
31497 + op, host->addr_value[1], host->addr_value[0]);
31577 + host->cache_addr_value[0] = host->addr_value[0];
31621 + | FMC_ADDRL_BLOCK_L_MASK(host->addr_value[0]);
31719 + host->addr_cycle = 0x0;
31773 + host->addr_cycle = 0;
31774 + host->addr_value[0] = 0;
31775 + host->addr_value[1] = 0;
31776 + host->cache_addr_value[0] = ~0;
31777 + host->cache_addr_value[1] = ~0;
31806 + unsigned char ret_val = 0;
31812 + host->cmd_op.l_cmd = 0;
31917 + if (err_num == 0xff) {
31934 + if (chipselect < 0) {
31966 + unsigned int addr_value = 0;
31967 + unsigned int addr_offset = 0;
31970 + host->addr_cycle = 0x0;
31971 + host->addr_value[0] = 0x0;
31972 + host->addr_value[1] = 0x0;
31982 + ((udat & 0xff) << addr_offset);
31988 + cmd = udat & 0xff;
31992 + host->offset = 0;
31997 + is_cache_invalid = 0;
31998 + if (host->addr_value[0] == host->pagesize) {
32009 + memset((u_char *)(host->iobase), 0,
32039 + host->offset = 0x0;
32040 + host->column = (host->addr_value[0] & 0xffff);
32045 + host->cache_addr_value[0] = ~0;
32046 + host->cache_addr_value[1] = ~0;
32079 + return 0;
32083 + * 'host->epm' only use the first oobfree[0] field, it looks very simple, But...
32096 + return 0;
32109 + return 0;
32128 + return 0;
32141 + return 0;
32159 + return 0;
32172 + return 0;
32187 + {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
32193 + {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
32194 + {0, 0, 0, 0, NULL},
32256 + struct mtd_oob_region hifmc_oobregion = {0, 0};
32276 + info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
32304 + return 0;
32317 + return 0;
32327 + unsigned int block_reg = 0;
32328 + unsigned int page_per_block = 0;
32333 + return 0;
32339 + return 0;
32397 + return 0;
32404 + /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
32411 + return 0;
32458 + return 0;
32464 + return 0;
32477 + for (cs = 0; cs < chip->numchips; cs++) {
32484 + return 0;
32492 @@ -0,0 +1,354 @@
32519 +#define INFINITE (0xFFFFFFFF)
32521 +#define SPI_IF_READ_STD (0x01)
32522 +#define SPI_IF_READ_FAST (0x02)
32523 +#define SPI_IF_READ_DUAL (0x04)
32524 +#define SPI_IF_READ_DUAL_ADDR (0x08)
32525 +#define SPI_IF_READ_QUAD (0x10)
32526 +#define SPI_IF_READ_QUAD_ADDR (0x20)
32528 +#define SPI_IF_WRITE_STD (0x01)
32529 +#define SPI_IF_WRITE_DUAL (0x02)
32530 +#define SPI_IF_WRITE_DUAL_ADDR (0x04)
32531 +#define SPI_IF_WRITE_QUAD (0x08)
32532 +#define SPI_IF_WRITE_QUAD_ADDR (0x10)
32534 +#define SPI_IF_ERASE_SECTOR_4K (0x01)
32535 +#define SPI_IF_ERASE_SECTOR_32K (0x02)
32536 +#define SPI_IF_ERASE_SECTOR_64K (0x04)
32537 +#define SPI_IF_ERASE_SECTOR_128K (0x08)
32538 +#define SPI_IF_ERASE_SECTOR_256K (0x10)
32551 +#define SPI_CMD_READ_STD 0x03 /* Standard read cache */
32552 +#define SPI_CMD_READ_FAST 0x0B /* Higher speed read cache */
32553 +#define SPI_CMD_READ_DUAL 0x3B /* 2 IO read cache only date */
32554 +#define SPI_CMD_READ_DUAL_ADDR 0xBB /* 2 IO read cache date&addr */
32555 +#define SPI_CMD_READ_QUAD 0x6B /* 4 IO read cache only date */
32556 +#define SPI_CMD_READ_QUAD_ADDR 0xEB /* 4 IO read cache date&addr */
32558 +#define SPI_CMD_WRITE_STD 0x02 /* Standard page program */
32559 +#define SPI_CMD_WRITE_DUAL 0xA2 /* 2 IO program only date */
32560 +#define SPI_CMD_WRITE_DUAL_ADDR 0xD2 /* 2 IO program date&addr */
32561 +#define SPI_CMD_WRITE_QUAD 0x32 /* 4 IO program only date */
32562 +#define SPI_CMD_WRITE_QUAD_ADDR 0x12 /* 4 IO program date&addr */
32564 +#define SPI_CMD_SE_4K 0x20 /* 4KB sector Erase */
32565 +#define SPI_CMD_SE_32K 0x52 /* 32KB sector Erase */
32566 +#define SPI_CMD_SE_64K 0xD8 /* 64KB sector Erase */
32567 +#define SPI_CMD_SE_128K 0xD8 /* 128KB sector Erase */
32568 +#define SPI_CMD_SE_256K 0xD8 /* 256KB sector Erase */
32662 +#define SPI_CMD_WREN 0x06 /* Write Enable */
32663 +#define SPI_CMD_WRDI 0x04 /* Write Disable */
32665 +#define SPI_CMD_RDID 0x9F /* Read Identification */
32667 +#define SPI_CMD_GET_FEATURES 0x0F /* Get Features */
32668 +#define SPI_CMD_SET_FEATURE 0x1F /* Set Feature */
32670 +#define SPI_CMD_PAGE_READ 0x13 /* Page Read to Cache */
32672 +#define SPI_CMD_RESET 0xff /* Reset the device */
32682 +#define HIFMC100_ECC_ERR_NUM0_BUF0 0xc0
32684 +#define GET_ECC_ERR_NUM(_i, _reg) (((_reg) >> ((_i) * 8)) & 0xff)
32688 +#define REG_CNT_BLOCK_NUM_MASK 0x3ff
32691 +#define REG_CNT_PAGE_NUM_MASK 0x3f
32696 +#define HIFMC100_ADDR_CYCLE_MASK 0x2
32697 +#define OP_STYPE_NONE 0x0
32698 +#define OP_STYPE_READ 0x01
32699 +#define OP_STYPE_WRITE 0x02
32700 +#define OP_STYPE_ERASE 0x04
32750 +#define BBP_LAST_PAGE 0x01
32751 +#define BBP_FIRST_PAGE 0x02
32814 +#define HIFMC_BAD_BLOCK_POS 0
32852 @@ -0,0 +1,247 @@
32899 + host->offset = 0;
32900 + memset((unsigned char *)(chip->IO_ADDR_R), 0, 0x10);
32904 + if (nand_maf_id == 0x00 || nand_maf_id == 0xff) {
32909 + return 0;
32914 + int result = 0;
32920 + for (cs = 0; chip_num && (cs < HIFMC_MAX_CHIP_NUM); cs++) {
32943 + result = 0;
32952 + int result = 0;
32973 + memset((char *)host, 0, len);
32988 + memset((char *)host->iobase, 0xff, fmc->dma_len);
33024 + result = mtd_device_register(mtd, NULL, 0);
33027 + return 0;
33049 + return 0;
33062 + return 0;
33073 + return 0;
33105 @@ -0,0 +1,313 @@
33169 + return 0;
33229 + return 0;
33233 + Read status[C0H]:[0]bit OIP, judge whether the device is busy or not
33261 + return 0;
33297 + return 0;
33342 + return 0;
33361 + return 0;
33365 + Send set features cmd to SPI Nand, feature[B0H]:[0]bit QE would be set
33424 @@ -0,0 +1,2457 @@
33502 +SET_WRITE_STD(0, 256, 24);
33503 +SET_WRITE_STD(0, 256, 75);
33504 +SET_WRITE_STD(0, 256, 80);
33505 +SET_WRITE_STD(0, 256, 100);
33506 +SET_WRITE_STD(0, 256, 104);
33507 +SET_WRITE_STD(0, 256, 133);
33509 +SET_WRITE_QUAD(0, 256, 80);
33510 +SET_WRITE_QUAD(0, 256, 100);
33511 +SET_WRITE_QUAD(0, 256, 104);
33512 +SET_WRITE_QUAD(0, 256, 108);
33513 +SET_WRITE_QUAD(0, 256, 120);
33514 +SET_WRITE_QUAD(0, 256, 133);
33516 +SET_ERASE_SECTOR_128K(0, _128K, 24);
33517 +SET_ERASE_SECTOR_128K(0, _128K, 75);
33518 +SET_ERASE_SECTOR_128K(0, _128K, 80);
33519 +SET_ERASE_SECTOR_128K(0, _128K, 104);
33520 +SET_ERASE_SECTOR_128K(0, _128K, 133);
33522 +SET_ERASE_SECTOR_256K(0, _256K, 24);
33523 +SET_ERASE_SECTOR_256K(0, _256K, 75);
33524 +SET_ERASE_SECTOR_256K(0, _256K, 80);
33525 +SET_ERASE_SECTOR_256K(0, _256K, 100);
33526 +SET_ERASE_SECTOR_256K(0, _256K, 104);
33527 +SET_ERASE_SECTOR_256K(0, _256K, 133);
33602 + .id = {0x2C, 0x14},
33616 + 0
33619 + &WRITE_STD(0, 256, 80),
33620 + &WRITE_QUAD(0, 256, 80),
33621 + 0
33624 + &ERASE_SECTOR_128K(0, _128K, 80),
33625 + 0
33633 + .id = {0x2C, 0x15},
33647 + 0
33650 + &WRITE_STD(0, 256, 80),
33651 + &WRITE_QUAD(0, 256, 80),
33652 + 0
33655 + &ERASE_SECTOR_128K(0, _128K, 80),
33656 + 0
33664 + .id = {0x2C, 0x24},
33678 + 0
33681 + &WRITE_STD(0, 256, 80),
33682 + &WRITE_QUAD(0, 256, 108),
33683 + 0
33686 + &ERASE_SECTOR_128K(0, _128K, 80),
33687 + 0
33695 + .id = {0x2C, 0x25},
33709 + 0
33712 + &WRITE_STD(0, 256, 80),
33713 + &WRITE_QUAD(0, 256, 80),
33714 + 0
33717 + &ERASE_SECTOR_128K(0, _128K, 80),
33718 + 0
33726 + .id = {0x2C, 0x36},
33740 + 0
33743 + &WRITE_STD(0, 256, 80),
33744 + &WRITE_QUAD(0, 256, 108),
33745 + 0
33748 + &ERASE_SECTOR_128K(0, _128K, 80),
33749 + 0
33757 + .id = {0xC8, 0x20},
33769 + 0
33772 + &WRITE_STD(0, 256, 24),
33773 + &WRITE_QUAD(0, 256, 104),
33774 + 0
33777 + &ERASE_SECTOR_128K(0, _128K, 24),
33778 + 0
33786 + .id = {0xC8, 0x21},
33798 + 0
33801 + &WRITE_STD(0, 256, 24),
33802 + &WRITE_QUAD(0, 256, 104),
33803 + 0
33806 + &ERASE_SECTOR_128K(0, _128K, 24),
33807 + 0
33815 + .id = {0xc8, 0x51},
33827 + 0
33830 + &WRITE_STD(0, 256, 133),
33831 + &WRITE_QUAD(0, 256, 133),
33832 + 0
33835 + &ERASE_SECTOR_128K(0, _128K, 133),
33836 + 0
33844 + .id = {0xC8, 0x01, 0X7F},
33856 + 0
33859 + &WRITE_STD(0, 256, 104),
33860 + &WRITE_QUAD(0, 256, 104),
33861 + 0
33864 + &ERASE_SECTOR_128K(0, _128K, 104),
33865 + 0
33873 + .id = {0xc8, 0xf1},
33887 + 0
33890 + &WRITE_STD(0, 256, 24),
33891 + &WRITE_QUAD(0, 256, 120),
33892 + 0
33895 + &ERASE_SECTOR_128K(0, _128K, 24),
33896 + 0
33904 + .id = {0xc8, 0x41},
33916 + 0
33919 + &WRITE_STD(0, 256, 24),
33920 + &WRITE_QUAD(0, 256, 104),
33921 + 0
33924 + &ERASE_SECTOR_128K(0, _128K, 104),
33925 + 0
33933 + .id = {0xc8, 0xd9},
33947 + 0
33950 + &WRITE_STD(0, 256, 104),
33951 + &WRITE_QUAD(0, 256, 120),
33952 + 0
33955 + &ERASE_SECTOR_128K(0, _128K, 104),
33956 + 0
33964 + .id = {0xc8, 0xc1},
33978 + 0
33981 + &WRITE_STD(0, 256, 24),
33982 + &WRITE_QUAD(0, 256, 120),
33983 + 0
33986 + &ERASE_SECTOR_128K(0, _128K, 24),
33987 + 0
33995 + .id = {0xc8, 0xd1},
34009 + 0
34012 + &WRITE_STD(0, 256, 24),
34013 + &WRITE_QUAD(0, 256, 120),
34014 + 0
34017 + &ERASE_SECTOR_128K(0, _128K, 24),
34018 + 0
34026 + .id = {0xc8, 0xf2},
34040 + 0
34043 + &WRITE_STD(0, 256, 24),
34044 + &WRITE_QUAD(0, 256, 120),
34045 + 0
34048 + &ERASE_SECTOR_128K(0, _128K, 24),
34049 + 0
34057 + .id = {0xc8, 0xd2},
34071 + 0
34074 + &WRITE_STD(0, 256, 24),
34075 + &WRITE_QUAD(0, 256, 120),
34076 + 0
34079 + &ERASE_SECTOR_128K(0, _128K, 24),
34080 + 0
34088 + .id = {0xc8, 0x52},
34102 + 0
34105 + &WRITE_STD(0, 256, 104),
34106 + &WRITE_QUAD(0, 256, 120),
34107 + 0
34110 + &ERASE_SECTOR_128K(0, _128K, 104),
34111 + 0
34119 + .id = {0xc8, 0x42},
34133 + 0
34136 + &WRITE_STD(0, 256, 104),
34137 + &WRITE_QUAD(0, 256, 104),
34138 + 0
34141 + &ERASE_SECTOR_128K(0, _128K, 104),
34142 + 0
34150 + .id = {0xc8, 0xf4},
34164 + 0
34167 + &WRITE_STD(0, 256, 24),
34168 + &WRITE_QUAD(0, 256, 120),
34169 + 0
34172 + &ERASE_SECTOR_128K(0, _128K, 24),
34173 + 0
34181 + .id = {0xc8, 0xd4},
34195 + 0
34198 + &WRITE_STD(0, 256, 24),
34199 + &WRITE_QUAD(0, 256, 120),
34200 + 0
34203 + &ERASE_SECTOR_256K(0, _256K, 24),
34204 + 0
34212 + .id = {0xc8, 0x55},
34226 + 0
34229 + &WRITE_STD(0, 256, 24), /* 24MHz */
34230 + &WRITE_QUAD(0, 256, 104), /* 104MHz */
34231 + 0
34234 + &ERASE_SECTOR_128K(0, _128K, 104), /* 104MHz */
34235 + 0
34243 + .id = {0xc8, 0xc1},
34257 + 0
34260 + &WRITE_STD(0, 256, 24),
34261 + &WRITE_QUAD(0, 256, 104),
34262 + 0
34265 + &ERASE_SECTOR_128K(0, _128K, 24),
34266 + 0
34274 + .id = {0xc8, 0xc2},
34288 + 0
34291 + &WRITE_STD(0, 256, 24),
34292 + &WRITE_QUAD(0, 256, 104),
34293 + 0
34296 + &ERASE_SECTOR_128K(0, _128K, 24),
34297 + 0
34304 + .id = {0xc8, 0x45},
34318 + 0
34321 + &WRITE_STD(0, 256, 80),
34322 + &WRITE_QUAD(0, 256, 80),
34323 + 0
34326 + &ERASE_SECTOR_128K(0, _128K, 80),
34327 + 0
34334 + .id = {0xc8, 0xe4},
34348 + 0
34351 + &WRITE_STD(0, 256, 24),
34352 + &WRITE_QUAD(0, 256, 104),
34353 + 0
34356 + &ERASE_SECTOR_256K(0, _256K, 24),
34357 + 0
34365 + .id = {0xef, 0xbf, 0x22},
34379 + 0
34382 + &WRITE_STD(0, 256, 104),
34383 + &WRITE_QUAD(0, 256, 104),
34384 + 0
34387 + &ERASE_SECTOR_128K(0, _128K, 104),
34388 + 0
34396 + .id = {0xc8, 0xc4},
34410 + 0
34413 + &WRITE_STD(0, 256, 24),
34414 + &WRITE_QUAD(0, 256, 120),
34415 + 0
34418 + &ERASE_SECTOR_256K(0, _256K, 24),
34419 + 0
34427 + .id = {0xef, 0xaa, 0x21},
34441 + 0
34444 + &WRITE_STD(0, 256, 24),
34445 + &WRITE_QUAD(0, 256, 104),
34446 + 0
34449 + &ERASE_SECTOR_128K(0, _128K, 24),
34450 + 0
34458 + .id = {0xef, 0xba, 0x21},
34472 + 0
34475 + &WRITE_STD(0, 256, 24),
34476 + &WRITE_QUAD(0, 256, 80),
34477 + 0
34480 + &ERASE_SECTOR_128K(0, _128K, 24),
34481 + 0
34489 + .id = {0x9b, 0x12},
34500 + 0
34503 + &WRITE_STD(0, 256, 24),
34504 + &WRITE_QUAD(0, 256, 104),
34505 + 0
34508 + &ERASE_SECTOR_128K(0, _128K, 24),
34509 + 0
34517 + .id = {0xc2, 0x12},
34528 + 0
34531 + &WRITE_STD(0, 256, 24),
34532 + &WRITE_QUAD(0, 256, 104),
34533 + 0
34536 + &ERASE_SECTOR_128K(0, _128K, 24),
34537 + 0
34545 + .id = {0xc2, 0x90},
34556 + 0
34559 + &WRITE_STD(0, 256, 24),
34560 + &WRITE_QUAD(0, 256, 104),
34561 + 0
34564 + &ERASE_SECTOR_128K(0, _128K, 104),
34565 + 0
34573 + .id = {0xc2, 0x22},
34584 + 0
34587 + &WRITE_STD(0, 256, 24),
34588 + &WRITE_QUAD(0, 256, 104),
34589 + 0
34592 + &ERASE_SECTOR_128K(0, _128K, 24),
34593 + 0
34601 + .id = {0xc2, 0x20},
34612 + 0
34615 + &WRITE_STD(0, 256, 24),
34616 + &WRITE_QUAD(0, 256, 104),
34617 + 0
34620 + &ERASE_SECTOR_128K(0, _128K, 24),
34621 + 0
34629 + .id = {0xc2, 0xa0},
34640 + 0
34643 + &WRITE_STD(0, 256, 24),
34644 + &WRITE_QUAD(0, 256, 104),
34645 + 0
34648 + &ERASE_SECTOR_128K(0, _128K, 104),
34649 + 0
34657 + .id = {0xa1, 0xe1},
34671 + 0
34674 + &WRITE_STD(0, 256, 24),
34675 + &WRITE_QUAD(0, 256, 108),
34676 + 0
34679 + &ERASE_SECTOR_128K(0, _128K, 24),
34680 + 0
34688 + .id = {0xa1, 0xe2},
34702 + 0
34705 + &WRITE_STD(0, 256, 24),
34706 + &WRITE_QUAD(0, 256, 108),
34707 + 0
34710 + &ERASE_SECTOR_128K(0, _128K, 24),
34711 + 0
34719 + .id = {0xc1, 0x51},
34733 + 0
34736 + &WRITE_STD(0, 256, 24),
34737 + &WRITE_QUAD(0, 256, 80),
34738 + 0
34741 + &ERASE_SECTOR_128K(0, _128K, 24),
34742 + 0
34750 + .id = {0xc1, 0x52},
34764 + 0
34767 + &WRITE_STD(0, 256, 24),
34768 + &WRITE_QUAD(0, 256, 80),
34769 + 0
34772 + &ERASE_SECTOR_128K(0, _128K, 24),
34773 + 0
34781 + .id = {0x98, 0xc2},
34793 + 0
34796 + &WRITE_STD(0, 256, 104),
34797 + 0
34800 + &ERASE_SECTOR_128K(0, _128K, 104),
34801 + 0
34808 + .id = {0x98, 0xe2, 0x40},
34820 + 0
34823 + &WRITE_STD(0, 256, 133),
34824 + &WRITE_QUAD(0, 256, 133),
34825 + 0
34828 + &ERASE_SECTOR_128K(0, _128K, 133),
34829 + 0
34836 + .id = {0x98, 0xb2},
34848 + 0
34851 + &WRITE_STD(0, 256, 104),
34852 + 0
34855 + &ERASE_SECTOR_128K(0, _128K, 104),
34856 + 0
34864 + .id = {0x98, 0xD2, 0x40},
34876 + 0
34879 + &WRITE_STD(0, 256, 133),
34880 + &WRITE_QUAD(0, 256, 133),
34881 + 0
34884 + &ERASE_SECTOR_128K(0, _128K, 133),
34885 + 0
34893 + .id = {0x98, 0xcb},
34905 + 0
34908 + &WRITE_STD(0, 256, 104),
34909 + 0
34912 + &ERASE_SECTOR_128K(0, _128K, 104),
34913 + 0
34921 + .id = {0x98, 0xeb, 0x40},
34933 + 0
34936 + &WRITE_STD(0, 256, 133),
34937 + &WRITE_QUAD(0, 256, 133),
34938 + 0
34941 + &ERASE_SECTOR_128K(0, _128K, 133),
34942 + 0
34950 + .id = {0x98, 0xbb},
34962 + 0
34965 + &WRITE_STD(0, 256, 75),
34966 + 0
34969 + &ERASE_SECTOR_128K(0, _128K, 75),
34970 + 0
34978 + .id = {0x98, 0xdb, 0x40},
34990 + 0
34993 + &WRITE_STD(0, 256, 133),
34994 + &WRITE_QUAD(0, 256, 133),
34995 + 0
34998 + &ERASE_SECTOR_128K(0, _128K, 133),
34999 + 0
35007 + .id = {0x98, 0xcd},
35019 + 0
35022 + &WRITE_STD(0, 256, 104),
35023 + 0
35026 + &ERASE_SECTOR_256K(0, _256K, 104),
35027 + 0
35035 + .id = {0x98, 0xed, 0x51},
35047 + 0
35050 + &WRITE_STD(0, 256, 133),
35051 + &WRITE_QUAD(0, 256, 133),
35052 + 0
35055 + &ERASE_SECTOR_256K(0, _256K, 133),
35056 + 0
35064 + .id = {0x98, 0xbd},
35076 + 0
35079 + &WRITE_STD(0, 256, 75),
35080 + 0
35083 + &ERASE_SECTOR_256K(0, _256K, 75),
35084 + 0
35092 + .id = {0x98, 0xdd, 0x51},
35104 + 0
35107 + &WRITE_STD(0, 256, 133), /* 133MHz */
35108 + &WRITE_QUAD(0, 256, 133), /* 133MHz */
35109 + 0
35112 + &ERASE_SECTOR_256K(0, _256K, 133), /* 133MHz */
35113 + 0
35121 + .id = {0x98, 0xd4, 0x51},
35133 + 0
35136 + &WRITE_STD(0, 256, 133), /* 133MHz */
35137 + &WRITE_QUAD(0, 256, 133), /* 133MHz */
35138 + 0
35141 + &ERASE_SECTOR_256K(0, _256K, 133), /* 133MHz */
35142 + 0
35150 + .id = {0xc9, 0x51},
35164 + 0
35167 + &WRITE_STD(0, 256, 80),
35168 + &WRITE_QUAD(0, 256, 80),
35169 + 0
35172 + &ERASE_SECTOR_128K(0, _128K, 80),
35173 + 0
35181 + .id = {0xc9, 0x52},
35195 + 0
35198 + &WRITE_STD(0, 256, 80),
35199 + &WRITE_QUAD(0, 256, 80),
35200 + 0
35203 + &ERASE_SECTOR_128K(0, _128K, 80),
35204 + 0
35212 + .id = {0xc9, 0xd4},
35226 + 0
35229 + &WRITE_STD(0, 256, 80),
35230 + &WRITE_QUAD(0, 256, 80),
35231 + 0
35234 + &ERASE_SECTOR_256K(0, _256K, 80),
35235 + 0
35243 + .id = {0xe5, 0x71},
35255 + 0
35258 + &WRITE_STD(0, 256, 80),
35259 + &WRITE_QUAD(0, 256, 104),
35260 + 0
35263 + &ERASE_SECTOR_128K(0, _128K, 104),
35264 + 0
35272 + .id = {0x0B, 0xF1},
35286 + 0
35289 + &WRITE_STD(0, 256, 80),
35290 + &WRITE_QUAD(0, 256, 80),
35291 + 0
35294 + &ERASE_SECTOR_128K(0, _128K, 80),
35295 + 0
35303 + .id = {0xD5, 0x8D},
35317 + 0
35320 + &WRITE_STD(0, 256, 100),
35321 + &WRITE_QUAD(0, 256, 100),
35322 + 0
35325 + &ERASE_SECTOR_256K(0, _256K, 100),
35326 + 0
35334 + .id = {0xD5, 0x8C},
35348 + 0
35351 + &WRITE_STD(0, 256, 100),
35352 + &WRITE_QUAD(0, 256, 100),
35353 + 0
35356 + &ERASE_SECTOR_256K(0, _256K, 100),
35357 + 0
35365 + .id = {0xd5, 0x81},
35379 + 0
35382 + &WRITE_STD(0, 256, 80),
35383 + &WRITE_QUAD(0, 256, 104),
35384 + 0
35387 + &ERASE_SECTOR_128K(0, _128K, 104),
35388 + 0
35396 + .id = {0xd5, 0x22},
35410 + 0
35413 + &WRITE_STD(0, 256, 104),
35414 + &WRITE_QUAD(0, 256, 120),
35415 + 0
35418 + &ERASE_SECTOR_128K(0, _128K, 104),
35419 + 0
35427 + .id = {0x2C, 0x35},
35439 + 0
35442 + &WRITE_STD(0, 256, 80),
35443 + &WRITE_QUAD(0, 256, 80),
35444 + 0
35447 + &ERASE_SECTOR_256K(0, _256K, 80),
35448 + 0
35456 + .id = {0xe5, 0x72},
35468 + 0
35471 + &WRITE_STD(0, 256, 80),
35472 + &WRITE_QUAD(0, 256, 104),
35473 + 0
35476 + &ERASE_SECTOR_128K(0, _128K, 104),
35477 + 0
35485 + .id = {0xa1, 0xa1},
35499 + 0
35502 + &WRITE_STD(0, 256, 104), /* 104MHz */
35503 + &WRITE_QUAD(0, 256, 104), /* 104MHz */
35504 + 0
35507 + &ERASE_SECTOR_128K(0, _128K, 104), /* 104MHz */
35508 + 0
35516 + .id = {0xa1, 0xe4},
35530 + 0
35533 + &WRITE_STD(0, 256, 104), /* 104MHz */
35534 + &WRITE_QUAD(0, 256, 104), /* 104MHz */
35535 + 0
35538 + &ERASE_SECTOR_128K(0, _128K, 104), /* 104MHz */
35539 + 0
35544 + { .id_len = 0, },
35551 + int ix = 0;
35571 + spiop_erase->size = 0;
35572 + for (ix = 0; ix < MAX_SPI_OP; ix++) {
35595 + 0, 0,
35600 + 0, 0,
35606 + for (ix = 0; iftype_write[ix]; ix += 2) {
35615 + for (ix = 0; iftype_read[ix]; ix += 2) {
35745 + int len = 0;
35755 + host->cmd_op.cs, id[0], id[1]);
35887 @@ -0,0 +1,50 @@
35917 + int "the width of Read/Write HIGH Hold Time (0 to 15)"
35918 + range 0 15
35924 + int "the Read pulse width (0 to 15)"
35925 + range 0 15
35931 + int "the Write pulse width (0 to 15)"
35932 + range 0 15
35943 @@ -0,0 +1,26 @@
35975 @@ -0,0 +1,1170 @@
36088 + if (*host->bbm != 0xFF && *host->bbm != 0x00) {
36090 + "page: 0x%08x, mark: 0x%02x,\n",
36100 + reg = host->addr_value[0] & 0xffff0000;
36108 + *host->epm = 0x0000;
36122 + if ((host->addr_value[0] == host->cache_addr_value[0]) &&
36125 + host->addr_value[1], host->addr_value[0]);
36129 + host->page_status = 0;
36145 + reg = host->addr_value[0] & 0xffff0000;
36159 + host->cache_addr_value[0] = host->addr_value[0];
36175 + reg = host->addr_value[0];
36207 + unsigned int change = 0;
36280 + reg = 0;
36296 + host->addr_cycle = 0x0;
36332 + unsigned char value = 0;
36340 + host->cmd_op.l_cmd = 0;
36415 + if (err_num == 0xff) {
36480 + if (chipselect < 0) {
36532 + unsigned int addr_value = 0;
36533 + unsigned int addr_offset = 0;
36536 + host->addr_cycle = 0x0;
36537 + host->addr_value[0] = 0x0;
36538 + host->addr_value[1] = 0x0;
36549 + (((unsigned int)dat & 0xff) << addr_offset);
36555 + cmd = (unsigned int)dat & 0xff;
36559 + host->offset = 0;
36564 + is_cache_invalid = 0;
36565 + if (host->addr_value[0] == host->pagesize) {
36577 + memset((u_char *)(chip->IO_ADDR_R), 0, MAX_NAND_ID_LEN);
36609 + host->offset = 0x0;
36610 + host->column = (host->addr_value[0] & 0xffff);
36615 + host->cache_addr_value[0] = ~0;
36616 + host->cache_addr_value[1] = ~0;
36623 + return 0x1;
36628 + * 'host->epm' only use the first oobfree[0] field, it looks very simple, But...
36640 + return 0;
36653 + return 0;
36672 + return 0;
36685 + return 0;
36702 + return 0;
36715 + return 0;
36728 + {NAND_PAGE_16K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
36733 + {NAND_PAGE_8K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
36740 + {NAND_PAGE_4K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
36747 + {NAND_PAGE_2K, NAND_ECC_0BIT, 0, 32, &hifmc_ooblayout_default_ops},
36749 + {0, 0, 0, 0, NULL},
36754 + * 0 - This NAND NOT support randomizer
36767 + return 0;
36829 + unsigned int block_reg = 0;
36913 + struct mtd_oob_region hifmc_oobregion = {0, 0};
36924 + memset(host->buffer, 0xff, buffer_len);
36930 + info->ooblayout_ops->free(mtd, 0, &hifmc_oobregion);
36969 + /* Set the page_size, ecc_type, block_size of FMC_CFG[0x0] register */
36983 + unsigned int shift = 0;
36998 + return 0;
37006 + memset((char *)chip->IO_ADDR_R, 0xff, host->dma_len);
37068 + host->addr_cycle = 0;
37069 + host->addr_value[0] = 0;
37070 + host->addr_value[1] = 0;
37071 + host->cache_addr_value[0] = ~0;
37072 + host->cache_addr_value[1] = ~0;
37097 + return 0;
37134 + return 0;
37151 @@ -0,0 +1,151 @@
37186 +#define HIFMC100_ECC_ERR_NUM0_BUF0 0xc0
37187 +#define HIFMC100_ECC_ERR_NUM1_BUF0 0xc4
37188 +#define HIFMC100_ECC_ERR_NUM0_BUF1 0xc8
37189 +#define HIFMC100_ECC_ERR_NUM1_BUF1 0xcc
37191 +#define GET_ECC_ERR_NUM(_i, _reg) (((_reg) >> ((_i) * 8)) & 0xff)
37203 +#define REG_CNT_BLOCK_NUM_MASK 0x3ff
37206 +#define REG_CNT_PAGE_NUM_MASK 0x3f
37210 +#define HIFMC100_ADDR_CYCLE_MASK 0x4
37262 +#define HIFMC100_BAD_BLOCK_POS 0
37267 +#define HIFMC100_PS_UC_ECC 0x01 /* page has ecc error */
37268 +#define HIFMC100_PS_BAD_BLOCK 0x02 /* bad block */
37269 +#define HIFMC100_PS_EMPTY_PAGE 0x04 /* page is empty */
37270 +#define HIFMC100_PS_EPM_ERROR 0x0100 /* empty page mark word has error. */
37271 +#define HIFMC100_PS_BBM_ERROR 0x0200 /* bad block mark word has error. */
37308 @@ -0,0 +1,180 @@
37343 + int result = 0;
37347 + int nr_parts = 0;
37364 + memset((char *)host, 0, len);
37404 + return (result == 1) ? -ENODEV : 0;
37419 + return 0;
37430 + return 0;
37443 + return 0;
37453 + return 0;
37457 + for (cs = 0; cs < chip->numchips; cs++) {
37462 + return 0;
37494 @@ -0,0 +1,72 @@
37572 @@ -0,0 +1,982 @@
37618 +#define BBP_LAST_PAGE 0x01
37619 +#define BBP_FIRST_PAGE 0x02
37632 + int pagesizes[] = {_2K, _4K, _8K, 0};
37633 + int oobsizes[] = {128, 224, 448, 0, 0, 0, 0, 0};
37634 + int blocksizes[] = {_128K, _256K, _512K, _768K, _1M, _2M, 0, 0};
37636 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
37637 + int oobtype = (((id[3] >> 2) & 0x03) | ((id[3] >> 4) & 0x04));
37639 + type->options = 0;
37640 + type->pagesize = pagesizes[(id[3] & 0x03)];
37652 + int pagesizes[] = {_2K, _4K, _8K, 0};
37653 + int oobsizes[] = {0, 128, 218, 400, 436, 0, 0, 0};
37654 + int blocksizes[] = {_128K, _256K, _512K, _1M, 0, 0, 0, 0};
37656 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
37657 + int oobtype = (((id[3] >> 4) & 0x04) | ((id[3] >> 2) & 0x03));
37659 + type->options = 0;
37660 + type->pagesize = pagesizes[(id[3] & 0x03)];
37739 + .id = {0xC2, 0xAA, 0x90, 0x15, 0x06},
37746 + .options = 0,
37749 + .flags = 0,
37756 + .id = {0x01, 0xDA, 0x90, 0x95, 0x46, 0x00, 0x00, 0x00},
37763 + .options = 0,
37766 + .flags = 0,
37771 + .id = {0x01, 0xDC, 0x90, 0x95, 0x56, 0x00, 0x00, 0x00},
37778 + .options = 0,
37781 + .flags = 0,
37786 + .id = {0x01, 0xAA, 0x90, 0x15, 0x46, 0x00, 0x00, 0x00},
37793 + .options = 0,
37796 + .flags = 0,
37801 + .id = {0x01, 0xAC, 0x90, 0x15, 0x56, 0x00, 0x00, 0x00},
37808 + .options = 0,
37811 + .flags = 0,
37818 + .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
37825 + .options = 0,
37832 + .id = {0x2C, 0x44, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
37839 + .options = 0,
37846 + .id = {0x2C, 0x38, 0x00, 0x26, 0x85, 0x00, 0x00, 0x00},
37853 + .options = 0,
37856 + .flags = 0,
37860 + .id = {0x2C, 0x48, 0x04, 0x46, 0x85, 0x00, 0x00, 0x00},
37867 + .options = 0,
37870 + .flags = 0,
37874 + .id = {0x2C, 0x48, 0x04, 0x4A, 0xA5, 0x00, 0x00, 0x00},
37881 + .options = 0,
37884 + .flags = 0,
37888 + .id = {0x2C, 0x68, 0x04, 0x4A, 0xA9, 0x00, 0x00, 0x00},
37895 + .options = 0,
37898 + .flags = 0,
37902 + .id = {0x2C, 0x88, 0x04, 0x4B, 0xA9, 0x00, 0x00, 0x00},
37909 + .options = 0,
37916 + .id = {0x2C, 0xA8, 0x05, 0xCB, 0xA9, 0x00, 0x00, 0x00},
37923 + .options = 0,
37930 + .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
37937 + .options = 0,
37940 + .flags = 0,
37944 + .id = {0x2C, 0xD3, 0x90, 0xA6, 0x64, 0x00, 0x00, 0x00},
37951 + .options = 0,
37954 + .flags = 0,
37958 + .id = {0x2C, 0xDC, 0x90, 0xA6, 0x54, 0x00, 0x00, 0x00},
37965 + .options = 0,
37968 + .flags = 0,
37972 + .id = {0x2C, 0xDA, 0x90, 0x95, 0x04, 0x00, 0x00, 0x00},
37979 + .options = 0,
37982 + .flags = 0,
37986 + .id = {0x2C, 0xDA, 0x90, 0x95, 0x06, 0x00, 0x00, 0x00},
37993 + .options = 0,
37996 + .flags = 0,
38000 + .id = {0x2C, 0x48, 0x00, 0x26, 0xA9, 0x00, 0x00, 0x00},
38007 + .options = 0,
38010 + .flags = 0,
38017 + .id = {0x98, 0xD5, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
38024 + .options = 0,
38027 + .flags = 0,
38031 + .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
38038 + .options = 0,
38041 + .flags = 0,
38045 + .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x56, 0x08, 0x00},
38052 + .options = 0,
38059 + .id = {0x98, 0xDE, 0x94, 0x82, 0x76, 0x00, 0x00, 0x00},
38066 + .options = 0,
38069 + .flags = 0,
38073 + .id = {0x98, 0xDE, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
38080 + .options = 0,
38087 + .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
38094 + .options = 0,
38101 + .id = {0x98, 0xF1, 0x80, 0x15, 0x72, 0x00, 0x00, 0x00},
38108 + .options = 0,
38116 + .flags = 0,
38120 + .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x16, 0x08, 0x00},
38127 + .options = 0,
38130 + .flags = 0,
38134 + .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x14, 0x03, 0x00},
38141 + .options = 0,
38144 + .flags = 0,
38148 + .id = {0x98, 0xD3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08},
38155 + .options = 0,
38158 + .flags = 0,
38162 + .id = {0x98, 0xD3, 0x91, 0x26, 0x76, 0x16, 0x08, 0x00},
38169 + .options = 0,
38172 + .flags = 0,
38176 + .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00},
38183 + .options = 0,
38186 + .flags = 0,
38190 + .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08},
38197 + .options = 0,
38200 + .flags = 0,
38204 + .id = {0x98, 0xDC, 0x91, 0x15, 0x76},
38211 + .options = 0,
38214 + .flags = 0,
38219 + .id = {0x98, 0xD7, 0x98, 0x92, 0x72, 0x57, 0x08, 0x10},
38226 + .options = 0,
38234 + .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x50, 0x08, 0x04},
38241 + .options = 0,
38248 + .id = {0x98, 0xDE, 0x94, 0x93, 0x76, 0x50},
38255 + .options = 0,
38263 + .id = {0xEC, 0xD7, 0xD5, 0x29, 0x38, 0x41, 0x00, 0x00},
38269 + .flags = 0,
38273 + .id = {0xEC, 0xD5, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
38279 + .flags = 0,
38283 + .id = {0xEC, 0xD7, 0xC5, 0x72, 0x54, 0x42, 0x00, 0x00},
38289 + .flags = 0,
38293 + .id = {0xEC, 0xD3, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
38299 + .flags = 0,
38303 + .id = {0xEC, 0xD5, 0x94, 0x76, 0x54, 0x43, 0x00, 0x00},
38310 + .options = 0,
38313 + .flags = 0,
38317 + .id = {0xEC, 0xD7, 0x55, 0xB6, 0x78, 0x00, 0x00, 0x00},
38324 + .options = 0,
38327 + .flags = 0,
38331 + .id = {0xEC, 0xD7, 0x94, 0x7A, 0x54, 0x43, 0x00, 0x00},
38338 + .options = 0,
38345 + .id = {0xEC, 0xD7, 0x94, 0x7E, 0x64, 0x44, 0x00, 0x00},
38352 + .options = 0,
38361 + .id = { 0xAD, 0xD5, 0x94, 0x25, 0x44, 0x41, },
38367 + .flags = 0,
38371 + .id = { 0xAD, 0xD5, 0x94, 0x9A, 0x74, 0x42, },
38377 + .flags = 0,
38381 + .id = { 0xAD, 0xD7, 0x94, 0x9A, 0x74, 0x42, },
38387 + .flags = 0,
38391 + .id = { 0xAD, 0xD7, 0x94, 0xDA, 0x74, 0xC3, },
38398 + .options = 0,
38405 + .id = { 0xAD, 0xDE, 0x94, 0xDA, 0x74, 0xC4, },
38412 + .options = 0,
38419 + .id = { 0xAD, 0xD7, 0x94, 0x91, 0x60, 0x44, },
38426 + .options = 0,
38435 + .id = { 0xC8, 0xD5, 0x14, 0x29, 0x34, 0x01, },
38442 + .options = 0,
38445 + .flags = 0,
38453 + .id = { 0xC8, 0xD3, 0x90, 0x19, 0x34, 0x01, },
38460 + .options = 0,
38463 + .flags = 0,
38467 + .id = { 0x7F, 0x7F, 0x7F, 0x7F, 0xC8, 0xDA, 0x00, 0x15, },
38474 + .options = 0,
38477 + .flags = 0,
38479 + {{0}, 0, 0, 0, 0, 0, 0, 0, 0},
38494 + pr_info("Nand ID: %#X %#X %#X %#X %#X %#X %#X %#X\n", id[0], id[1],
38540 + chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
38573 @@ -0,0 +1,237 @@
38635 + return ecctype_string[(ecctype & 0x07)];
38658 + return pagesize_str[(pagetype & 0x07)];
38673 + _512B, _2K, _4K, _8K, _16K, 0, 0, 0
38675 + return pagesize[(pagetype & 0x07)];
38700 + int ret = 0;
38703 + return 0;
38705 + if (n > 0xFFFF)
38706 + loop = n > 0xFFFFFF ? 32 : 24;
38708 + loop = n > 0xFF ? 16 : 8;
38710 + while (loop-- > 0 && n) {
38718 +#define et_ecc_none 0x00
38719 +#define et_ecc_4bit 0x02
38720 +#define et_ecc_8bit 0x03
38721 +#define et_ecc_24bit1k 0x04
38722 +#define et_ecc_40bit1k 0x05
38723 +#define et_ecc_64bit1k 0x06
38817 @@ -0,0 +1,281 @@
38845 +#define HINFC_VER_300 (0x300)
38846 +#define HINFC_VER_301 (0x301)
38847 +#define HINFC_VER_310 (0x310)
38848 +#define HINFC_VER_504 (0x504)
38849 +#define HINFC_VER_505 (0x505)
38850 +#define HINFC_VER_600 (0x600)
38851 +#define HINFC_VER_610 (0x610)
38852 +#define HINFC_VER_620 (0x620)
38854 +#define HISNFC_VER_100 (0x400)
38856 +#define NAND_PAGE_512B 0
38864 +#define NAND_ECC_NONE 0
38865 +#define NAND_ECC_0BIT 0
38891 + et_ecc_none = 0x00,
38892 + et_ecc_1bit = 0x01,
38893 + et_ecc_4bit = 0x02,
38894 + et_ecc_8bit = 0x03,
38895 + et_ecc_24bit1k = 0x04,
38896 + et_ecc_40bit1k = 0x05,
38897 + et_ecc_64bit1k = 0x06,
38901 + pt_pagesize_512 = 0x00,
38902 + pt_pagesize_2K = 0x01,
38903 + pt_pagesize_4K = 0x02,
38904 + pt_pagesize_8K = 0x03,
38905 + pt_pagesize_16K = 0x04,
38920 + ((((_mfr) & 0xFF) << 16) | (((_version) & 0xFF) << 8) \
38921 + | ((_onfi) & 0xFF))
38923 +#define GET_NAND_SYNC_TYPE_MFR(_type) (((_type) >> 16) & 0xFF)
38924 +#define GET_NAND_SYNC_TYPE_VER(_type) (((_type) >> 8) & 0xFF)
38925 +#define GET_NAND_SYNC_TYPE_INF(_type) ((_type) & 0xFF)
38928 + SET_NAND_SYNC_TYPE(NAND_MFR_MICRON, NAND_IS_ONFI, 0x23)
38930 + SET_NAND_SYNC_TYPE(NAND_MFR_MICRON, NAND_IS_ONFI, 0x30)
38932 + SET_NAND_SYNC_TYPE(NAND_MFR_TOSHIBA, 0, 0)
38934 + SET_NAND_SYNC_TYPE(NAND_MFR_SAMSUNG, 0, 0)
38936 +#define NAND_TYPE_TOGGLE_10 SET_NAND_SYNC_TYPE(0, 0, 0x10)
38937 +#define NAND_TYPE_ONFI_30 SET_NAND_SYNC_TYPE(0, NAND_IS_ONFI, 0x30)
38938 +#define NAND_TYPE_ONFI_23 SET_NAND_SYNC_TYPE(0, NAND_IS_ONFI, 0x23)
38971 +#define NANDC_HW_AUTO 0x01
38974 +#define NANDC_CONFIG_DONE 0x02
38976 +#define NANDC_IS_SYNC_BOOT 0x04
38979 +#define NAND_RANDOMIZER 0x10
38981 +#define NAND_IS_ONFI 0x20
38983 +#define NAND_MODE_SYNC_ASYNC 0x40
38985 +#define NAND_MODE_ONLY_SYNC 0x80
38989 + * toggle1.0 interface */
38991 +/* This NAND is only sync mode, toggle2.0 interface */
38998 +#define NAND_RR_NONE 0x00
38999 +#define NAND_RR_HYNIX_BG_BDIE 0x10
39000 +#define NAND_RR_HYNIX_BG_CDIE 0x11
39001 +#define NAND_RR_HYNIX_CG_ADIE 0x12
39002 +#define NAND_RR_MICRON 0x20
39003 +#define NAND_RR_SAMSUNG 0x30
39004 +#define NAND_RR_TOSHIBA_24nm 0x40
39005 +#define NAND_RR_TOSHIBA_19nm 0x41
39023 +#define DISABLE 0
39073 +} while (0)
39102 index 000000000..0fd7db974
39105 @@ -0,0 +1,970 @@
39141 +#define BBP_LAST_PAGE 0x01
39142 +#define BBP_FIRST_PAGE 0x02
39157 + int pagesizes[] = {SZ_2K, SZ_4K, SZ_8K, 0};
39158 + int oobsizes[] = {128, 224, 448, 0, 0, 0, 0, 0};
39160 + (SZ_256K + SZ_512K), SZ_1M, SZ_2M, 0, 0
39163 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
39164 + int oobtype = (((id[3] >> 2) & 0x03) | ((id[3] >> 4) & 0x04));
39166 + type->options = 0;
39167 + type->pagesize = pagesizes[(id[3] & 0x03)];
39181 + int pagesizes[] = {SZ_2K, SZ_4K, SZ_8K, 0};
39182 + int oobsizes[] = {0, 128, 218, 400, 436, 0, 0, 0};
39183 + int blocksizes[] = {SZ_128K, SZ_256K, SZ_512K, SZ_1M, 0, 0, 0, 0};
39185 + int blocktype = (((id[3] >> 5) & 0x04) | ((id[3] >> 4) & 0x03));
39186 + int oobtype = (((id[3] >> 4) & 0x04) | ((id[3] >> 2) & 0x03));
39188 + type->options = 0;
39189 + type->pagesize = pagesizes[(id[3] & 0x03)];
39268 + .id = {0x01, 0xDA, 0x90, 0x95, 0x46, 0x00, 0x00, 0x00},
39275 + .options = 0,
39278 + .flags = 0,
39283 + .id = {0x01, 0xDC, 0x90, 0x95, 0x56, 0x00, 0x00, 0x00},
39290 + .options = 0,
39293 + .flags = 0,
39299 + .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
39306 + .options = 0,
39313 + .id = {0x2C, 0x44, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
39320 + .options = 0,
39327 + .id = {0x2C, 0x38, 0x00, 0x26, 0x85, 0x00, 0x00, 0x00},
39334 + .options = 0,
39337 + .flags = 0,
39341 + .id = {0x2C, 0x48, 0x04, 0x46, 0x85, 0x00, 0x00, 0x00},
39348 + .options = 0,
39351 + .flags = 0,
39355 + .id = {0x2C, 0x48, 0x04, 0x4A, 0xA5, 0x00, 0x00, 0x00},
39362 + .options = 0,
39365 + .flags = 0,
39369 + .id = {0x2C, 0x68, 0x04, 0x4A, 0xA9, 0x00, 0x00, 0x00},
39376 + .options = 0,
39379 + .flags = 0,
39383 + .id = {0x2C, 0x88, 0x04, 0x4B, 0xA9, 0x00, 0x00, 0x00},
39390 + .options = 0,
39393 + .flags = 0,
39397 + .id = {0x2C, 0xA8, 0x05, 0xCB, 0xA9, 0x00, 0x00, 0x00},
39404 + .options = 0,
39407 + .flags = 0,
39411 + .id = {0x2C, 0x64, 0x44, 0x4B, 0xA9, 0x00, 0x00, 0x00},
39418 + .options = 0,
39421 + .flags = 0,
39425 + .id = {0x2C, 0xD3, 0x90, 0xA6, 0x64, 0x00, 0x00, 0x00},
39432 + .options = 0,
39435 + .flags = 0,
39439 + .id = {0x2C, 0xDC, 0x90, 0xA6, 0x54, 0x00, 0x00, 0x00},
39446 + .options = 0,
39449 + .flags = 0,
39453 + .id = {0x2C, 0xDA, 0x90, 0x95, 0x04, 0x00, 0x00, 0x00},
39460 + .options = 0,
39463 + .flags = 0,
39467 + .id = {0x2C, 0xDA, 0x90, 0x95, 0x06, 0x00, 0x00, 0x00},
39474 + .options = 0,
39477 + .flags = 0,
39481 + .id = {0x2C, 0x48, 0x00, 0x26, 0xA9, 0x00, 0x00, 0x00},
39488 + .options = 0,
39491 + .flags = 0,
39498 + .id = {0x98, 0xD5, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
39505 + .options = 0,
39508 + .flags = 0,
39512 + .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x55, 0x00, 0x00},
39519 + .options = 0,
39522 + .flags = 0,
39526 + .id = {0x98, 0xD7, 0x94, 0x32, 0x76, 0x56, 0x08, 0x00},
39533 + .options = 0,
39540 + .id = {0x98, 0xDE, 0x94, 0x82, 0x76, 0x00, 0x00, 0x00},
39547 + .options = 0,
39550 + .flags = 0,
39554 + .id = {0x98, 0xDE, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
39561 + .options = 0,
39568 + .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x57, 0x08, 0x04},
39575 + .options = 0,
39582 + .id = {0x98, 0xF1, 0x80, 0x15, 0x72, 0x00, 0x00, 0x00},
39589 + .options = 0,
39597 + .flags = 0,
39601 + .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x16, 0x08, 0x00},
39608 + .options = 0,
39611 + .flags = 0,
39615 + .id = {0x98, 0xDA, 0x90, 0x15, 0x76, 0x14, 0x03, 0x00},
39622 + .options = 0,
39625 + .flags = 0,
39629 + .id = {0x98, 0xD3, 0x90, 0x26, 0x76, 0x15, 0x02, 0x08},
39636 + .options = 0,
39639 + .flags = 0,
39643 + .id = {0x98, 0xD3, 0x91, 0x26, 0x76, 0x16, 0x08, 0x00},
39650 + .options = 0,
39653 + .flags = 0,
39657 + .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x16, 0x08, 0x00},
39664 + .options = 0,
39667 + .flags = 0,
39671 + .id = {0x98, 0xDC, 0x90, 0x26, 0x76, 0x15, 0x01, 0x08},
39678 + .options = 0,
39681 + .flags = 0,
39685 + .id = {0x98, 0xDC, 0x91, 0x15, 0x76},
39692 + .options = 0,
39695 + .flags = 0,
39699 + .id = {0x98, 0xD7, 0x98, 0x92, 0x72, 0x57, 0x08, 0x10},
39706 + .options = 0,
39714 + .id = {0x98, 0xD7, 0x84, 0x93, 0x72, 0x50, 0x08, 0x04},
39721 + .options = 0,
39728 + .id = {0x98, 0xDE, 0x94, 0x93, 0x76, 0x50},
39735 + .options = 0,
39743 + .id = {0xEC, 0xD7, 0xD5, 0x29, 0x38, 0x41, 0x00, 0x00},
39749 + .flags = 0,
39753 + .id = {0xEC, 0xD5, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
39759 + .flags = 0,
39763 + .id = {0xEC, 0xD7, 0xC5, 0x72, 0x54, 0x42, 0x00, 0x00},
39769 + .flags = 0,
39773 + .id = {0xEC, 0xD3, 0x84, 0x72, 0x50, 0x42, 0x00, 0x00},
39779 + .flags = 0,
39783 + .id = {0xEC, 0xD5, 0x94, 0x76, 0x54, 0x43, 0x00, 0x00},
39790 + .options = 0,
39793 + .flags = 0,
39797 + .id = {0xEC, 0xD7, 0x55, 0xB6, 0x78, 0x00, 0x00, 0x00},
39804 + .options = 0,
39807 + .flags = 0,
39811 + .id = {0xEC, 0xD7, 0x94, 0x7A, 0x54, 0x43, 0x00, 0x00},
39818 + .options = 0,
39825 + .id = {0xEC, 0xD7, 0x94, 0x7E, 0x64, 0x44, 0x00, 0x00},
39832 + .options = 0,
39841 + .id = { 0xAD, 0xD5, 0x94, 0x25, 0x44, 0x41, },
39847 + .flags = 0,
39851 + .id = { 0xAD, 0xD5, 0x94, 0x9A, 0x74, 0x42, },
39857 + .flags = 0,
39861 + .id = { 0xAD, 0xD7, 0x94, 0x9A, 0x74, 0x42, },
39867 + .flags = 0,
39871 + .id = { 0xAD, 0xD7, 0x94, 0xDA, 0x74, 0xC3, },
39878 + .options = 0,
39885 + .id = { 0xAD, 0xDE, 0x94, 0xDA, 0x74, 0xC4, },
39892 + .options = 0,
39899 + .id = { 0xAD, 0xD7, 0x94, 0x91, 0x60, 0x44, },
39906 + .options = 0,
39915 + .id = { 0xC8, 0xD5, 0x14, 0x29, 0x34, 0x01, },
39922 + .options = 0,
39925 + .flags = 0,
39933 + .id = { 0xC8, 0xD3, 0x90, 0x19, 0x34, 0x01, },
39940 + .options = 0,
39943 + .flags = 0,
39947 + .id = { 0x7F, 0x7F, 0x7F, 0x7F, 0xC8, 0xDA, 0x00, 0x15, },
39954 + .options = 0,
39957 + .flags = 0,
39959 + {{0}, 0, 0, 0, 0, 0, 0, 0, 0},
39979 + hinfc_pr_msg("Nand ID: 0x%02X 0x%02X 0x%02X 0x%02X",
39980 + byte[0], byte[1], byte[2], byte[3]);
39981 + hinfc_pr_msg(" 0x%02X 0x%02X 0x%02X 0x%02X\n",
40020 + memset(nand_dev, 0, sizeof(struct nand_dev_t));
40083 #define NAND_MFR_AMD 0x01
40084 -#define NAND_MFR_ATO 0x9b
40085 #define NAND_MFR_EON 0x92
40086 +#define NAND_MFR_WINBOND 0xef
40087 +#define NAND_MFR_ATO 0x9b
40088 +#define NAND_MFR_MXIC 0xc2
40089 +#define NAND_MFR_ALL_FLASH 0xc1
40090 +#define NAND_MFR_PARAGON 0xa1
40091 #define NAND_MFR_ESMT 0xc8
40092 #define NAND_MFR_FUJITSU 0x04
40093 #define NAND_MFR_HYNIX 0xad
40095 #define NAND_MFR_STMICRO 0x20
40097 #define NAND_MFR_TOSHIBA 0x98
40098 -#define NAND_MFR_WINBOND 0xef
40099 +#define NAND_MFR_GD_ESMT 0xc8
40100 +#define NAND_MFR_HEYANGTEK 0xc9
40101 +#define NAND_MFR_DOSILICON 0xe5
40102 +#define NAND_MFR_FIDELIX 0xf8
40111 @@ -0,0 +1,102 @@
40125 + while (length-- > 0) {
40136 + while (length-- > 0) {
40148 + while (length-- > 0) {
40160 + while (length-- > 0) {
40171 + while (nr_table-- > 0) {
40182 + while (nr_table-- > 0) {
40194 + while (nr_table-- > 0) {
40206 + while (nr_table-- > 0) {
40219 @@ -0,0 +1,51 @@
40246 +#define MATCH_SET_TYPE_REG(_type, _reg) {(_type), (_reg), (void *)0}
40247 +#define MATCH_SET_TYPE_DATA(_type, _data) {(_type), 0, (void *)(_data)}
40285 int oob_required = oob ? 1 : 0;
40291 ops->retlen = 0;
40293 return 0;
40299 + int busw = 0;
40300 + int ret = 0;
40360 return 0;
40387 + {0x0, "Unknown"}
40443 + from 0 address.
40471 @@ -0,0 +1,106 @@
40537 + default "0xFFFF"
40541 + This value is 16 bit, so its value is 0x0000~0xFFFF.
40542 + The default value is 0xFFFF.
40546 + default "0xFFFF"
40552 + This value is 16 bit, so its value is 0x0000~0xFFFF.
40553 + The default value is 0xFFFF.
40583 @@ -0,0 +1,2 @@
40591 @@ -0,0 +1,162 @@
40606 + u32 link_stat = 0;
40645 + /* EEE_1us: 0x7c for 125M */
40646 + writel(0x7c, ld->gmac_iobase +
40648 + writel(0x1e0400, ld->gmac_iobase + EEE_TIMER);
40651 + v |= 0x3 << 1; /* auto EEE and ... */
40689 + pr_info("fit phy_id:0x%x, phy_name:%s, eee:%d\n",
40705 + if (lp_eee_capable < 0)
40759 @@ -0,0 +1,52 @@
40772 +#define NO_EEE 0
40785 +#define EEE_CLK 0x800
40786 +#define MASK_EEE_CLK (0x3 << 20)
40789 +#define EEE_ENABLE 0x808
40790 +#define BIT_EEE_ENABLE BIT(0)
40791 +#define EEE_TIMER 0x80C
40792 +#define EEE_LINK_STATUS 0x810
40793 +#define BIT_PHY_LINK_STATUS BIT(0)
40794 +#define EEE_TIME_CLK_CNT 0x814
40798 +#define MACR 0x0D
40799 +#define MAADR 0x0E
40800 +#define EEE_DEV 0x3
40801 +#define EEE_CAPABILITY 0x14
40802 +#define EEELPAR_DEV 0x7
40803 +#define EEELPAR 0x3D /* EEE link partner ability register */
40804 +#define EEE_ADVERTISE 0x3c
40817 @@ -0,0 +1,184 @@
40838 + for (i = 0; phy_info_table[i].name; i++) {
40853 + phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */
40863 + phy_write(phy_dev, MACR, 0x4000 | mmd_device); /* function = 01 data */
40870 + static int first_time = 0;
40872 + u32 eee_type = 0;
40878 + eee_lan = phy_read(phy_dev, 0x10);
40879 + if (eee_lan < 0)
40881 + eee_lan = (u32)eee_lan | 0x4;
40882 + phy_write(phy_dev, 0x10, eee_lan);
40883 + eee_lan = phy_read(phy_dev, 0x10);
40884 + if (eee_lan < 0)
40887 + eee_lan = phy_read(phy_dev, 0x0);
40888 + if (eee_lan < 0)
40890 + eee_lan = (u32)eee_lan | 0x200;
40891 + phy_write(phy_dev, 0x0, eee_lan);
40904 +#define RTL8211EG_MAC 0
40908 + static int first_time = 0;
40911 + u32 eee_type = 0;
40916 + phy_write(phy_dev, 0x1f, 0x0);
40925 + phy_write(phy_dev, 0x1f, 0x7);
40926 + phy_write(phy_dev, 0x1e, 0x20);
40927 + phy_write(phy_dev, 0x1b, 0xa03a);
40928 + phy_write(phy_dev, 0x1f, 0x0);
40944 + u32 eee_type = 0;
40959 + static int first_time_init = 0;
40961 + u32 eee_type = 0;
40975 + if (v < 0)
40994 + {"SMSC LAN8740", 0x0007c110, MAC_EEE, &smsc_lan8740_init},
40996 + {"Realtek 8211EG", 0x001cc915, MAC_EEE, &rtl8211eg_mac_init},
40998 + {"Realtek 8211EG", 0x001cc915, PHY_EEE, &rtl8211eg_init},
41007 @@ -0,0 +1,118 @@
41054 + /* write 0 to cancel reset */
41059 + /* RST_BIT, write 0 to reset phy, write 1 to cancel reset */
41068 + /* write 0 to cancel reset */
41131 @@ -0,0 +1,2645 @@
41175 +#define has_tso_cap(hw_cap) ((((hw_cap) >> 28) & 0x3) == VER_TSO)
41182 +MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
41195 + writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
41209 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
41216 + writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
41223 + writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
41240 + writel(0, priv->gmac_iobase + RX_FQ_REG_EN);
41257 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
41274 + writel(0, priv->gmac_iobase + TX_BQ_REG_EN);
41291 + writel(0, priv->gmac_iobase + TX_RQ_REG_EN);
41321 + writel(0, priv->gmac_iobase + RX_BQ_REG_EN);
41327 + u32 val = 0;
41361 + writel(0, priv->gmac_iobase + ENA_PMU_INT);
41362 + writel(~0, priv->gmac_iobase + RAW_PMU_INT);
41366 + writel(0, priv->gmac_iobase + reg);
41368 + writel(~0, priv->gmac_iobase + RSS_RAW_PMU_INT);
41384 + writel(0, priv->gmac_iobase + COL_SLOT_TIME);
41394 + writel(0x10000, priv->gmac_iobase + RX_BQ_IN_TIMEOUT_TH);
41396 + writel(0x18000, priv->gmac_iobase + TX_RQ_IN_TIMEOUT_TH);
41417 + writel(~0, ld->gmac_iobase + reg);
41428 + for (i = 0; i < ld->num_rxqs; i++)
41436 + writel(0, ld->gmac_iobase + ENA_PMU_INT);
41446 + writel(0, ld->gmac_iobase + reg);
41457 + for (i = 0; i < ld->num_rxqs; i++)
41479 + writel(0xF, ld->gmac_iobase + DESC_WR_RD_ENA);
41486 + writel(0, ld->gmac_iobase + DESC_WR_RD_ENA);
41499 + writel(0, ld->gmac_iobase + PORT_EN);
41529 + writel(0, ld->gmac_iobase + PORT_MC_ADDR_LOW);
41530 + writel(0, ld->gmac_iobase + PORT_MC_ADDR_HIGH);
41538 + d = (ha->addr[0] << 8) | (ha->addr[1]); /* shift left 8bits */
41597 + for (i = 0; i < ld->RX_FQ.count; i++) {
41624 + for (i = 0; i < ld->TX_BQ.count; i++) {
41640 + val = mac[1] | (mac[0] << 8); /* shift left 8 bits */
41642 + /* mac 2 3 4 5 shift left 24 16 8 0 bits */
41654 + for (i = 0; i < ld->RX_FQ.count; i++) {
41679 + for (i = 0; i < ld->TX_BQ.count; i++) {
41761 + (long long)time_limit >= 0))
41826 + priv->old_link = 0;
41867 + pr_info("Higmac dma_sg_phy: 0x%pK\n", (void *)(uintptr_t)ld->dma_sg_phy);
41870 + ld->sg_head = 0;
41871 + ld->sg_tail = 0;
41873 + return 0;
41946 + for (rxq_id = 0; rxq_id < ld->num_rxqs; rxq_id++) {
41964 + u32 refill_cnt = 0;
41972 + for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) {
42000 + desc->data_len = 0;
42001 + desc->fl = 0;
42087 + netdev_err(dev, "desc->skb(0x%p),RX_FQ.skb[%d](0x%p)\n",
42091 + return 0;
42100 + return 0;
42125 + for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) {
42168 + "TX ERR: desc1=0x%x, desc2=0x%x, desc5=0x%x\n",
42174 + for (i = 0; i < sizeof(struct sg_desc) / sizeof(int); i++)
42175 + pr_err("%s,%d: sg_desc word[%d]=0x%x\n",
42181 + return 0;
42206 + for (i = 0; i < nfrags; i++) {
42228 + if (unlikely(higmac_check_tx_err(ld, tx_rq_desc, desc_pos) < 0)) {
42266 + id_free = 0;
42267 + pkt_rec[id_free].status = 0;
42271 + return 0;
42292 + return 0;
42300 + unsigned int bytes_compl = 0;
42301 + unsigned int pkts_compl = 0;
42313 + for (i = 0, dma_info.pos = dma_info.start; i < dma_info.num; i++) {
42330 + if (higmac_xmit_reclaim_release(dev, skb, desc, dma_info.pos) < 0)
42357 + int work_done = 0;
42433 + for (i = 0; i < nfrags; i++) {
42438 + dma_addr = skb_frag_dma_map(ld->dev, frag, 0,
42474 + return 0;
42529 + return 0;
42580 + id_send = 0;
42585 + return 0;
42597 + if (gso_segs == 0 && skb_shinfo(skb)->gso_size != 0)
42665 + return 0;
42676 + return 0;
42687 + if (unlikely(higmac_check_skb_len(skb, dev) < 0))
42716 + if (unlikely(ret < 0)) {
42730 + if (unlikely(ret < 0)) {
42762 + for (i = 0; i < priv->num_rxqs; i++) {
42774 + for (i = 0; i < priv->num_rxqs; i++) {
42822 + return 0;
42843 + return 0;
42884 + return 0;
42931 + return 0;
42938 + for (i = 0; i < QUEUE_NUMS + RSS_NUM_RXQS - 1; i++) {
42996 + return 0;
43003 + dma_addr_t phys_addr = 0;
43018 + for (i = 0; i < (QUEUE_NUMS + RSS_NUM_RXQS - 1); i++) {
43023 + memset(virt_addr, 0, size);
43029 + memset(virt_addr, 0, size);
43046 + return 0;
43060 + for (i = 0; i < priv->num_rxqs; i++) {
43075 + for (i = 0; i < priv->num_rxqs; i++) {
43091 + for (i = 0; i < priv->num_rxqs; i++) {
43093 + if (ret < 0) {
43108 + return 0;
43163 + if (ret < 0) {
43167 + return 0;
43181 + if (ret < 0) {
43186 + return 0;
43200 + ndev->irq = priv->irq[0];
43223 + timer_setup(&priv->monitor, higmac_monitor_func, 0);
43253 + return 0;
43266 + &higmac_adjust_link, 0, priv->phy_mode);
43273 + if ((priv->phy->phy_id == 0) && !fixed_link) {
43279 + pr_info("attached PHY %d to driver %s, PHY_ID=0x%x\n",
43310 + return 0;
43367 + if (ret < 0) {
43373 + priv->phy_node = of_parse_phandle(node, "phy-handle", 0);
43378 + if (ret < 0) {
43395 + return 0;
43433 + return 0;
43577 + return 0;
43585 + for (i = 0; i < priv->num_rxqs; i++)
43593 + for (i = 0; i < priv->num_rxqs; i++)
43646 + return 0;
43701 + priv->old_link = 0;
43717 + return 0;
43761 + return 0;
43782 @@ -0,0 +1,603 @@
43801 +#define STATION_ADDR_LOW 0x0000
43802 +#define STATION_ADDR_HIGH 0x0004
43803 +#define MAC_DUPLEX_HALF_CTRL 0x0008
43805 +#define PORT_MODE 0x0040
43807 +#define PORT_EN 0x0044
43811 +#define FC_TX_TIMER 0x001C
43813 +#define PAUSE_THR 0x0038
43815 +#define PAUSE_EN 0x0048
43816 +#define BIT_RX_FDFC BIT(0)
43819 +#define RX_PAUSE_EN 0x02A4
43820 +#define BIT_RX_FQ_PAUSE_EN BIT(0)
43823 +#define CRF_TX_PAUSE 0x0340
43826 +#define BITS_Q_PAUSE_TH_MASK 0xFFFF
43828 +#define REC_FILT_CONTROL 0x0064
43834 +#define BIT_UC_MATCH_EN BIT(0)
43836 +#define PORT_MC_ADDR_LOW 0x0068
43837 +#define PORT_MC_ADDR_HIGH 0x006C
43838 +#define MAC_CLEAR 0x0070
43839 +#define BIT_TX_SOFT_RESET BIT(0)
43841 +#define MODE_CHANGE_EN 0x01b4
43842 +#define BIT_MODE_CHANGE_EN BIT(0)
43844 +#define COL_SLOT_TIME 0x01c0
43846 +#define CRF_MIN_PACKET 0x0210
43850 +#define CONTROL_WORD 0x0214
43851 +#define CONTROL_WORD_CONFIG 0x640
43853 +#define TSO_COE_CTRL 0x02e8
43861 +#define RX_FQ_START_ADDR 0x0500
43862 +#define RX_FQ_DEPTH 0x0504
43866 +#define TX_DESC_HI8_MASK 0xff
43868 +#define RX_FQ_WR_ADDR 0x0508
43869 +#define BITS_RX_FQ_WR_ADDR mk_bits(0, 21)
43870 +#define RX_FQ_RD_ADDR 0x050c
43871 +#define BITS_RX_FQ_RD_ADDR mk_bits(0, 21)
43872 +#define RX_FQ_VLDDESC_CNT 0x0510
43873 +#define BITS_RX_FQ_VLDDESC_CNT mk_bits(0, 16)
43874 +#define RX_FQ_ALEMPTY_TH 0x0514
43875 +#define BITS_RX_FQ_ALEMPTY_TH mk_bits(0, 16)
43876 +#define RX_FQ_REG_EN 0x0518
43879 +#define BITS_RX_FQ_RD_ADDR_EN mk_bits(0, 1)
43880 +#define RX_FQ_ALFULL_TH 0x051c
43881 +#define BITS_RX_FQ_ALFULL_TH mk_bits(0, 16)
43883 +#define RX_BQ_START_ADDR 0x0520
43884 +#define RX_BQ_DEPTH 0x0524
43885 +#define RX_BQ_WR_ADDR 0x0528
43886 +#define RX_BQ_RD_ADDR 0x052c
43887 +#define RX_BQ_FREE_DESC_CNT 0x0530
43888 +#define BITS_RX_BQ_FREE_DESC_CNT mk_bits(0, 16)
43889 +#define RX_BQ_ALEMPTY_TH 0x0534
43890 +#define BITS_RX_BQ_ALEMPTY_TH mk_bits(0, 16)
43891 +#define RX_BQ_REG_EN 0x0538
43894 +#define BITS_RX_BQ_WR_ADDR_EN mk_bits(0, 1)
43895 +#define RX_BQ_ALFULL_TH 0x053c
43896 +#define BITS_RX_BQ_ALFULL_TH mk_bits(0, 16)
43898 +#define TX_BQ_START_ADDR 0x0580
43899 +#define TX_BQ_DEPTH 0x0584
43900 +#define TX_BQ_WR_ADDR 0x0588
43901 +#define BITS_TX_BQ_WR_ADDR mk_bits(0, 21)
43902 +#define TX_BQ_RD_ADDR 0x058c
43903 +#define BITS_TX_BQ_RD_ADDR mk_bits(0, 21)
43904 +#define TX_BQ_VLDDESC_CNT 0x0590
43905 +#define BITS_TX_BQ_VLDDESC_CNT mk_bits(0, 16)
43906 +#define TX_BQ_ALEMPTY_TH 0x0594
43907 +#define BITS_TX_BQ_ALEMPTY_TH mk_bits(0, 16)
43908 +#define TX_BQ_REG_EN 0x0598
43911 +#define BITS_TX_BQ_RD_ADDR_EN mk_bits(0, 1)
43912 +#define TX_BQ_ALFULL_TH 0x059c
43913 +#define BITS_TX_BQ_ALFULL_TH mk_bits(0, 16)
43915 +#define TX_RQ_START_ADDR 0x05a0
43916 +#define TX_RQ_DEPTH 0x05a4
43917 +#define TX_RQ_WR_ADDR 0x05a8
43918 +#define BITS_TX_RQ_WR_ADDR mk_bits(0, 21)
43919 +#define TX_RQ_RD_ADDR 0x05ac
43920 +#define BITS_TX_RQ_RD_ADDR mk_bits(0, 21)
43921 +#define TX_RQ_FREE_DESC_CNT 0x05b0
43922 +#define BITS_TX_RQ_FREE_DESC_CNT mk_bits(0, 16)
43923 +#define TX_RQ_ALEMPTY_TH 0x05b4
43924 +#define BITS_TX_RQ_ALEMPTY_TH mk_bits(0, 16)
43925 +#define TX_RQ_REG_EN 0x05b8
43928 +#define BITS_TX_RQ_WR_ADDR_EN mk_bits(0, 1)
43929 +#define TX_RQ_ALFULL_TH 0x05bc
43930 +#define BITS_TX_RQ_ALFULL_TH mk_bits(0, 16)
43932 +#define RAW_PMU_INT 0x05c0
43933 +#define ENA_PMU_INT 0x05c4
43935 +#define DESC_WR_RD_ENA 0x05CC
43937 +#define IN_QUEUE_TH 0x05d8
43940 +#define RX_BQ_IN_TIMEOUT_TH 0x05E0
43942 +#define TX_RQ_IN_TIMEOUT_TH 0x05e4
43944 +#define STOP_CMD 0x05e8
43946 +#define BITS_RX_STOP_EN BIT(0)
43949 +#define RSS_IND_TBL 0x0c0c
43952 +#define RSS_RAW_PMU_INT 0x0c10
43953 +#define RSS_QUEUE1_START_ADDR 0x0c20
43955 + ((i) - 1) * 0x10)
43956 +#define RSS_QUEUE1_DEPTH 0x0c24
43957 +#define RX_BQ_WR_ADDR_QUEUE1 0x0c28
43958 +#define RX_BQ_RD_ADDR_QUEUE1 0x0c2c
43959 +#define RSS_QUEUE1_ENA_INT 0x0c90
43960 +#define rss_ena_int_queue(i) (RSS_QUEUE1_ENA_INT + ((i) - 1) * 0x4)
43961 +#define rx_bq_depth_queue(i) (RSS_QUEUE1_DEPTH + ((i) - 1) * 0x10)
43963 + ((i) - 1) * 0x10) : RX_BQ_WR_ADDR)
43965 + ((i) - 1) * 0x10) : RX_BQ_RD_ADDR)
43967 +#define def_int_mask_queue(i) (0x3 << (2 * ((i) - 1)))
43970 +#define BURST_OUTSTANDING_REG 0x3014
43971 +#define BURST4_OUTSTANDING1 0x81ff
43974 +#define GMAC_SPEED_1000 0x05
43975 +#define GMAC_SPEED_100 0x01
43976 +#define GMAC_SPEED_10 0x00
43978 +#define IPV4_HEAD_LENGTH 0x5
43981 + ERR_NONE = 0,
43982 + ERR_DESC_CFG = (1 << 0),
44045 +#define HIGMAC_IOSIZE 0x1000
44057 +#define higmac_sync_barrier() do { isb(); smp_mb(); } while (0)
44059 +#define HISILICON_PHY_ID_FESTAV200 0x20669823
44060 +#define PHY_ID_KSZ8051MNL 0x00221550
44061 +#define PHY_ID_KSZ8081RNB 0x00221560
44062 +#define PHY_ID_UNKNOWN 0x00221513
44063 +#define DEFAULT_PHY_MASK 0xfffffff0
44064 +#define REALTEK_PHY_ID_8211E 0x001cc915
44065 +#define REALTEK_PHY_MASK 0x001fffff
44081 +#define HIGMAC_LINKED BIT(0)
44087 +#define FLOW_OFF 0
44092 +#define RX_BQ_INT_THRESHOLD 0x40
44093 +#define TX_RQ_INT_THRESHOLD 0x20
44100 +#define DESC_VLD_FREE 0
44104 +#define DESC_FL_MID 0
44129 +#define HW_CAP_TSO BIT(0)
44245 +#define SKB_MAGIC ((struct sk_buff *)0x5a)
44274 + int index; /* 0 -- mac0, 1 -- mac1 */
44298 +#define RX_FQ pool[0]
44344 +#define INIT 0 /* init gmac */
44350 + VER_NO_TSO = 0x0,
44351 + VER_BYTE_SPLICE = 0x1,
44352 + VER_SG_COE = 0x2,
44353 + VER_TSO = 0x3,
44391 @@ -0,0 +1,341 @@
44410 + int len = 0;
44412 + memset(data, 0, sizeof(data));
44414 + for (i = 0; i < N; i++) {
44415 + if (mask & 0x1)
44441 +#define PM_CLEAR 0
44447 + unsigned int cmd = 0;
44448 + unsigned int offset = 0;
44449 + unsigned short crc[FILTERS] = { 0 };
44455 + * 0 * * no use the filter
44456 + * 1 0 * all pkts can wake-up(non-exist)
44457 + * 1 1 0 all pkts can wake-up
44458 + * 1 1 !0 normal filter
44461 + for (i = 0; i < FILTERS; i++) {
44472 + * for logic, mask valid bit(bit31) must set to 0,
44473 + * 0 is enable
44483 + v &= ~(0xFFFF << (16 * i)); /* 16 bits mask */
44488 + v &= ~(0xFFFF << (16 * (i - 2))); /* filer 2 3, 16 bits mask */
44522 + v = 0;
44530 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
44537 + return 0;
44558 + return 0;
44572 + v |= BIT(0); /* enter power down */
44574 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
44594 + v &= ~BIT(0); /* enter power down */
44597 + v |= 0x3 << 5; /* set bit5 bit6, clear irq status */
44646 +#define POLYNOMIAL 0x8005
44647 +#define INITIAL_REMAINDER 0xFFFF
44648 +#define FINAL_XOR_VALUE 0x0000
44677 + unsigned int reversed = 0x00000000;
44681 + for (bit = 0; bit < nbits; ++bit) {
44683 + if (data & 0x01)
44699 + for (dividend = 0; dividend < CRC_TABLE_LEN; ++dividend) {
44704 + for (bit = 8; bit > 0; --bit) {
44724 + for (byte = 0; byte < nbytes; ++byte) {
44738 @@ -0,0 +1,59 @@
44780 +#define PMT_CTRL 0xa00
44781 +#define PMT_MASK0 0xa04
44782 +#define PMT_MASK1 0xa08
44783 +#define PMT_MASK2 0xa0c
44784 +#define PMT_MASK3 0xa10
44785 +#define PMT_CMD 0xa14
44786 +#define PMT_OFFSET 0xa18
44787 +#define PMT_CRC1_0 0xa1c
44788 +#define PMT_CRC3_2 0xa20
44804 @@ -0,0 +1,119 @@
44818 + return 0;
44824 + return 0;
44829 + return 0;
44868 + for (i = 0; i < ARRAY_SIZE(proc_file); i++) {
44871 + entry = proc_create(proc_file[i].name, 0, higmac_proc_root,
44882 + for (i = 0; i < ARRAY_SIZE(proc_file); i++)
44892 + int val = 0;
44922 + return 0;
44929 @@ -0,0 +1,19 @@
44954 @@ -0,0 +1,59 @@
45019 @@ -0,0 +1,975 @@
45100 + writel_relaxed(0, priv->gmac_iobase + MODE_CHANGE_EN);
45128 + return 0;
45152 + if (tx_flow_ctrl_pause_time < 0 ||
45156 + if (tx_flow_ctrl_pause_interval < 0 ||
45216 + writel(0, ld->gmac_iobase + CRF_TX_PAUSE);
45290 + return 0;
45313 + return 0;
45352 + return 0;
45363 + csum = skb_checksum(skb, offset, skb->len - offset, 0);
45368 + if (udp_csum == 0)
45409 + *coe_enable = 0;
45424 + *coe_enable = 0;
45427 + return 0;
45436 + unsigned char coe_enable = 0;
45445 + tx_bq_desc->desc1.val = 0;
45456 + if (ret < 0)
45475 + return 0;
45492 + return ld->phy->link ? HIGMAC_LINKED : 0;
45528 + pause->rx_pause = 0;
45529 + pause->tx_pause = 0;
45566 + return 0;
45610 + for (i = 0; i < rss->ind_tbl_size; i++)
45614 + return 0;
45641 + for (i = 0; !(readl(base + RSS_IND_TBL) & BIT_IND_TBL_READY); i++) {
45649 + return 0;
45660 + for (i = 0; i < rss->ind_tbl_size; i++) {
45661 + if (higmac_wait_rss_ready(priv) != 0)
45676 + for (i = 0; i < rss->ind_tbl_size; i++) {
45677 + if (higmac_wait_rss_ready(priv) != 0)
45680 + if (higmac_wait_rss_ready(priv) != 0)
45683 + rss->ind_tbl[i] = (rss_val >> 10) & 0x3; /* right shift 10 */
45699 + for (i = 0; i < rss->ind_tbl_size; i++)
45710 + return 0;
45729 + info->data = 0;
45749 + higmac_get_rss_hash(info, hash_cfg, IPV4_L3_HASH_EN, 0,
45753 + higmac_get_rss_hash(info, hash_cfg, IPV6_L3_HASH_EN, 0,
45760 + return 0;
45773 + ret = 0;
45794 + case 0: // all bits is 0
45807 + return 0;
45819 + return 0;
45874 + return 0;
45897 + return 0;
45899 + ret = phy_read(phy_dev, 0x1F);
45900 + if (ret < 0)
45904 + phy_write(phy_dev, 0x1F, v);
45906 + ret = phy_read(phy_dev, 0x16);
45907 + if (ret < 0)
45911 + phy_write(phy_dev, 0x16, v);
45913 + return 0;
45922 + return 0;
45924 + ret = phy_read(phy_dev, 0x1F);
45925 + if (ret < 0)
45929 + phy_write(phy_dev, 0x1F, v);
45931 + return 0;
45940 + return 0;
45942 + ret = phy_read(phy_dev, 0x1F);
45943 + if (ret < 0)
45947 + phy_write(phy_dev, 0x1F, v);
45949 + return 0;
45958 + phy_write(phy_dev, 0x1f, 0x7);
45960 + phy_write(phy_dev, 0x1e, 0xa4);
45963 + ret = phy_read(phy_dev, 0x1c);
45964 + if (ret < 0)
45967 + v = (v & 0xff03) | 0xfc;
45968 + phy_write(phy_dev, 0x1c, v);
45970 + /* select to page 0 */
45971 + phy_write(phy_dev, 0x1f, 0);
45973 + return 0;
46000 @@ -0,0 +1,102 @@
46016 +#define mk_bits(shift, nbits) ((((shift) & 0x1F) << 16) | ((nbits) & 0x3F))
46025 +#define FC_PAUSE_TIME_DEFAULT 0xFFFF
46026 +#define FC_PAUSE_INTERVAL_DEFAULT 0xFFFF
46027 +#define FC_PAUSE_TIME_MAX 0xFFFF
46029 +#define HW_CAP_EN 0x0c00
46030 +#define BIT_RSS_CAP BIT(0)
46032 +#define RSS_HASH_KEY 0x0c04
46033 +#define RSS_HASH_CONFIG 0x0c08
46034 +#define TCPV4_L3_HASH_EN BIT(0)
46050 +#define DEF_HASH_CFG 0x377377
46052 +#define RGMII_SPEED_1000 0x2c
46053 +#define RGMII_SPEED_100 0x2f
46054 +#define RGMII_SPEED_10 0x2d
46055 +#define MII_SPEED_100 0x0f
46056 +#define MII_SPEED_10 0x0d
46057 +#define RMII_SPEED_100 0x8f
46058 +#define RMII_SPEED_10 0x8d
46108 @@ -0,0 +1,6 @@
46120 @@ -0,0 +1,191 @@
46130 + 0x33f9, 0xbd, 0x33fa, 0x34, 0x33fb, 0x00,
46131 + 0x33fc, 0x39, 0x3400, 0x39, 0x3401, 0xCC,
46132 + 0x3402, 0x2C, 0x3403, 0x02, 0x3404, 0xFD,
46133 + 0x3405, 0xFF, 0x3406, 0xF0, 0x3407, 0xF6,
46134 + 0x3408, 0x36, 0x3409, 0x18, 0x340A, 0x26,
46135 + 0x340B, 0x05, 0x340C, 0xC6, 0x340D, 0x01,
46136 + 0x340E, 0xF7, 0x340F, 0x36, 0x3410, 0x18,
46137 + 0x3411, 0xCC, 0x3412, 0x35, 0x3413, 0x9F,
46138 + 0x3414, 0x1A, 0x3415, 0xB3, 0x3416, 0x00,
46139 + 0x3417, 0xD2, 0x3418, 0x27, 0x3419, 0x09,
46140 + 0x341A, 0xFD, 0x341B, 0x00, 0x341C, 0xD2,
46141 + 0x341D, 0x7F, 0x341E, 0x01, 0x341F, 0xBF,
46142 + 0x3420, 0x7F, 0x3421, 0x01, 0x3422, 0xB1,
46143 + 0x3423, 0x39, 0x3424, 0x3C, 0x3425, 0x3C,
46144 + 0x3426, 0x30, 0x3427, 0xF6, 0x3428, 0x30,
46145 + 0x3429, 0x55, 0x342A, 0xC0, 0x342B, 0x07,
46146 + 0x342C, 0x18, 0x342D, 0xFE, 0x342E, 0x30,
46147 + 0x342F, 0x4C, 0x3430, 0x18, 0x3431, 0x3A,
46148 + 0x3432, 0x18, 0x3433, 0xE6, 0x3434, 0x00,
46149 + 0x3435, 0x5C, 0x3436, 0xE7, 0x3437, 0x01,
46150 + 0x3438, 0xC1, 0x3439, 0x07, 0x343A, 0x23,
46151 + 0x343B, 0x04, 0x343C, 0xC6, 0x343D, 0x07,
46152 + 0x343E, 0xE7, 0x343F, 0x01, 0x3440, 0x58,
46153 + 0x3441, 0x58, 0x3442, 0x58, 0x3443, 0x58,
46154 + 0x3444, 0x58, 0x3445, 0xE7, 0x3446, 0x00,
46155 + 0x3447, 0xF6, 0x3448, 0x20, 0x3449, 0x04,
46156 + 0x344A, 0xC4, 0x344B, 0x1F, 0x344C, 0xEA,
46157 + 0x344D, 0x00, 0x344E, 0xF7, 0x344F, 0x20,
46158 + 0x3450, 0x04, 0x3451, 0x38, 0x3452, 0x38,
46159 + 0x3453, 0x39, 0x3454, 0x3C, 0x3455, 0x37,
46160 + 0x3456, 0x36, 0x3457, 0x30, 0x3458, 0x1A,
46161 + 0x3459, 0xEE, 0x345A, 0x00, 0x345B, 0x18,
46162 + 0x345C, 0xE6, 0x345D, 0x00, 0x345E, 0x26,
46163 + 0x345F, 0x1C, 0x3460, 0xF6, 0x3461, 0x00,
46164 + 0x3462, 0x5C, 0x3463, 0xC5, 0x3464, 0x04,
46165 + 0x3465, 0x27, 0x3466, 0x06, 0x3467, 0xCC,
46166 + 0x3468, 0x36, 0x3469, 0x12, 0x346A, 0xBD,
46167 + 0x346B, 0xF0, 0x346C, 0xA5, 0x346D, 0xF6,
46168 + 0x346E, 0x00, 0x346F, 0x47, 0x3470, 0xC4,
46169 + 0x3471, 0xF3, 0x3472, 0xF7, 0x3473, 0x00,
46170 + 0x3474, 0x47, 0x3475, 0xC6, 0x3476, 0x01,
46171 + 0x3477, 0x1A, 0x3478, 0xEE, 0x3479, 0x00,
46172 + 0x347A, 0x20, 0x347B, 0x10, 0x347C, 0x5A,
46173 + 0x347D, 0x26, 0x347E, 0x14, 0x347F, 0xF6,
46174 + 0x3480, 0x00, 0x3481, 0x46, 0x3482, 0x4F,
46175 + 0x3483, 0xC4, 0x3484, 0x0C, 0x3485, 0x83,
46176 + 0x3486, 0x00, 0x3487, 0x08, 0x3488, 0x26,
46177 + 0x3489, 0x05, 0x348A, 0xC6, 0x348B, 0x02,
46178 + 0x348C, 0x18, 0x348D, 0xE7, 0x348E, 0x00,
46179 + 0x348F, 0x5F, 0x3490, 0x38, 0x3491, 0x38,
46180 + 0x3492, 0x39, 0x3493, 0xF6, 0x3494, 0x00,
46181 + 0x3495, 0x5C, 0x3496, 0xC5, 0x3497, 0x04,
46182 + 0x3498, 0x27, 0x3499, 0x06, 0x349A, 0xCC,
46183 + 0x349B, 0x36, 0x349C, 0x08, 0x349D, 0xBD,
46184 + 0x349E, 0xF0, 0x349F, 0xA5, 0x34A0, 0xF6,
46185 + 0x34A1, 0x00, 0x34A2, 0x47, 0x34A3, 0xC4,
46186 + 0x34A4, 0xF3, 0x34A5, 0xCA, 0x34A6, 0x08,
46187 + 0x34A7, 0xF7, 0x34A8, 0x00, 0x34A9, 0x47,
46188 + 0x34AA, 0x18, 0x34AB, 0xFE, 0x34AC, 0x00,
46189 + 0x34AD, 0xB6, 0x34AE, 0x18, 0x34AF, 0xAD,
46190 + 0x34B0, 0x00, 0x34B1, 0xBD, 0x34B2, 0x34,
46191 + 0x34B3, 0x24, 0x34B4, 0xF6, 0x34B5, 0x1E,
46192 + 0x34B6, 0x05, 0x34B7, 0xC5, 0x34B8, 0x02,
46193 + 0x34B9, 0x27, 0x34BA, 0x0A, 0x34BB, 0xF6,
46194 + 0x34BC, 0x1E, 0x34BD, 0x07, 0x34BE, 0xC5,
46195 + 0x34BF, 0x02, 0x34C0, 0x27, 0x34C1, 0x03,
46196 + 0x34C2, 0xBD, 0x34C3, 0xC0, 0x34C4, 0x33,
46197 + 0x34C5, 0xF6, 0x34C6, 0x31, 0x34C7, 0x1F,
46198 + 0x34C8, 0x37, 0x34C9, 0xC6, 0x34CA, 0x52,
46199 + 0x34CB, 0xBD, 0x34CC, 0xDC, 0x34CD, 0x53,
46200 + 0x34CE, 0x31, 0x34CF, 0xF6, 0x34D0, 0x00,
46201 + 0x34D1, 0x41, 0x34D2, 0xC5, 0x34D3, 0x10,
46202 + 0x34D4, 0x26, 0x34D5, 0x04, 0x34D6, 0x13,
46203 + 0x34D7, 0x23, 0x34D8, 0x40, 0x34D9, 0x0D,
46204 + 0x34DA, 0xBD, 0x34DB, 0x93, 0x34DC, 0xCE,
46205 + 0x34DD, 0x1A, 0x34DE, 0xEE, 0x34DF, 0x00,
46206 + 0x34E0, 0x18, 0x34E1, 0x6F, 0x34E2, 0x00,
46207 + 0x34E3, 0xC6, 0x34E4, 0x04, 0x34E5, 0x20,
46208 + 0x34E6, 0xA9, 0x34E7, 0x1A, 0x34E8, 0xEE,
46209 + 0x34E9, 0x00, 0x34EA, 0x18, 0x34EB, 0x6F,
46210 + 0x34EC, 0x00, 0x34ED, 0xC6, 0x34EE, 0x01,
46211 + 0x34EF, 0x20, 0x34F0, 0x9F, 0x34F1, 0x3C,
46212 + 0x34F2, 0x37, 0x34F3, 0x36, 0x34F4, 0x30,
46213 + 0x34F5, 0x1A, 0x34F6, 0xEE, 0x34F7, 0x00,
46214 + 0x34F8, 0x18, 0x34F9, 0xE6, 0x34FA, 0x00,
46215 + 0x34FB, 0x26, 0x34FC, 0x49, 0x34FD, 0xF6,
46216 + 0x34FE, 0x00, 0x34FF, 0x5C, 0x3500, 0xC5,
46217 + 0x3501, 0x04, 0x3502, 0x27, 0x3503, 0x06,
46218 + 0x3504, 0xCC, 0x3505, 0x35, 0x3506, 0xFC,
46219 + 0x3507, 0xBD, 0x3508, 0xF0, 0x3509, 0xA5,
46220 + 0x350A, 0xC6, 0x350B, 0x52, 0x350C, 0xBD,
46221 + 0x350D, 0xDC, 0x350E, 0xF3, 0x350F, 0x5D,
46222 + 0x3510, 0x27, 0x3511, 0x03, 0x3512, 0xBD,
46223 + 0x3513, 0xC0, 0x3514, 0x22, 0x3515, 0xF6,
46224 + 0x3516, 0x00, 0x3517, 0x46, 0x3518, 0xC5,
46225 + 0x3519, 0x0C, 0x351A, 0x26, 0x351B, 0x0A,
46226 + 0x351C, 0x1A, 0x351D, 0xEE, 0x351E, 0x00,
46227 + 0x351F, 0x18, 0x3520, 0x6F, 0x3521, 0x00,
46228 + 0x3522, 0xC6, 0x3523, 0x07, 0x3524, 0x20,
46229 + 0x3525, 0x1D, 0x3526, 0xFC, 0x3527, 0x30,
46230 + 0x3528, 0x0C, 0x3529, 0xBD, 0x352A, 0x93,
46231 + 0x352B, 0x19, 0x352C, 0xBD, 0x352D, 0x9F,
46232 + 0x352E, 0x0B, 0x352F, 0xC6, 0x3530, 0x02,
46233 + 0x3531, 0x37, 0x3532, 0xC6, 0x3533, 0x51,
46234 + 0x3534, 0xBD, 0x3535, 0xDC, 0x3536, 0x53,
46235 + 0x3537, 0x31, 0x3538, 0x7F, 0x3539, 0x02,
46236 + 0x353A, 0x07, 0x353B, 0xC6, 0x353C, 0x02,
46237 + 0x353D, 0x1A, 0x353E, 0xEE, 0x353F, 0x00,
46238 + 0x3540, 0x18, 0x3541, 0xE7, 0x3542, 0x00,
46239 + 0x3543, 0x38, 0x3544, 0x38, 0x3545, 0x39,
46240 + 0x3546, 0xC6, 0x3547, 0x52, 0x3548, 0xBD,
46241 + 0x3549, 0xDC, 0x354A, 0xF3, 0x354B, 0x5D,
46242 + 0x354C, 0x27, 0x354D, 0x03, 0x354E, 0xBD,
46243 + 0x354F, 0xC0, 0x3550, 0x22, 0x3551, 0xF6,
46244 + 0x3552, 0x00, 0x3553, 0x46, 0x3554, 0xC5,
46245 + 0x3555, 0x0C, 0x3556, 0x26, 0x3557, 0x0A,
46246 + 0x3558, 0x1A, 0x3559, 0xEE, 0x355A, 0x00,
46247 + 0x355B, 0x18, 0x355C, 0x6F, 0x355D, 0x00,
46248 + 0x355E, 0xC6, 0x355F, 0x07, 0x3560, 0x20,
46249 + 0x3561, 0xE1, 0x3562, 0xC6, 0x3563, 0x51,
46250 + 0x3564, 0xBD, 0x3565, 0xDC, 0x3566, 0xF3,
46251 + 0x3567, 0x5D, 0x3568, 0x26, 0x3569, 0x04,
46252 + 0x356A, 0xC6, 0x356B, 0x02, 0x356C, 0x20,
46253 + 0x356D, 0xD5, 0x356E, 0xF6, 0x356F, 0x00,
46254 + 0x3570, 0x41, 0x3571, 0xC5, 0x3572, 0x10,
46255 + 0x3573, 0x26, 0x3574, 0x20, 0x3575, 0xF6,
46256 + 0x3576, 0x02, 0x3577, 0x07, 0x3578, 0xC1,
46257 + 0x3579, 0x02, 0x357A, 0x24, 0x357B, 0x19,
46258 + 0x357C, 0x18, 0x357D, 0xFE, 0x357E, 0x02,
46259 + 0x357F, 0x08, 0x3580, 0x18, 0x3581, 0xAD,
46260 + 0x3582, 0x00, 0x3583, 0xF6, 0x3584, 0x02,
46261 + 0x3585, 0x06, 0x3586, 0x27, 0x3587, 0x0D,
46262 + 0x3588, 0xC6, 0x3589, 0x02, 0x358A, 0x37,
46263 + 0x358B, 0xC6, 0x358C, 0x51, 0x358D, 0xBD,
46264 + 0x358E, 0xDC, 0x358F, 0x53, 0x3590, 0x31,
46265 + 0x3591, 0xC6, 0x3592, 0x02, 0x3593, 0x20,
46266 + 0x3594, 0xAE, 0x3595, 0x1A, 0x3596, 0xEE,
46267 + 0x3597, 0x00, 0x3598, 0x18, 0x3599, 0x6F,
46268 + 0x359A, 0x00, 0x359B, 0xC6, 0x359C, 0x03,
46269 + 0x359D, 0x20, 0x359E, 0xA4, 0x359F, 0xF6,
46270 + 0x35A0, 0x01, 0x35A1, 0xBF, 0x35A2, 0xC1,
46271 + 0x35A3, 0x08, 0x35A4, 0x24, 0x35A5, 0x55,
46272 + 0x35A6, 0xBD, 0x35A7, 0xF6, 0x35A8, 0xD3,
46273 + 0x35A9, 0x35, 0x35AA, 0xBA, 0x35AB, 0x35,
46274 + 0x35AC, 0xC2, 0x35AD, 0x35, 0x35AE, 0xCA,
46275 + 0x35AF, 0x35, 0x35B0, 0xD2, 0x35B1, 0x35,
46276 + 0x35B2, 0xDA, 0x35B3, 0x35, 0x35B4, 0xE2,
46277 + 0x35B5, 0x35, 0x35B6, 0xEA, 0x35B7, 0x35,
46278 + 0x35B8, 0xF2, 0x35B9, 0x39, 0x35BA, 0xCC,
46279 + 0x35BB, 0x01, 0x35BC, 0xB1, 0x35BD, 0xBD,
46280 + 0x35BE, 0x34, 0x35BF, 0x54, 0x35C0, 0x20,
46281 + 0x35C1, 0x36, 0x35C2, 0xCC, 0x35C3, 0x01,
46282 + 0x35C4, 0xB1, 0x35C5, 0xBD, 0x35C6, 0xC1,
46283 + 0x35C7, 0x52, 0x35C8, 0x20, 0x35C9, 0x2E,
46284 + 0x35CA, 0xCC, 0x35CB, 0x01, 0x35CC, 0xB1,
46285 + 0x35CD, 0xBD, 0x35CE, 0x34, 0x35CF, 0xF1,
46286 + 0x35D0, 0x20, 0x35D1, 0x26, 0x35D2, 0xCC,
46287 + 0x35D3, 0x01, 0x35D4, 0xB1, 0x35D5, 0xBD,
46288 + 0x35D6, 0xC3, 0x35D7, 0x9A, 0x35D8, 0x20,
46289 + 0x35D9, 0x1E, 0x35DA, 0xCC, 0x35DB, 0x01,
46290 + 0x35DC, 0xB1, 0x35DD, 0xBD, 0x35DE, 0xC4,
46291 + 0x35DF, 0x39, 0x35E0, 0x20, 0x35E1, 0x16,
46292 + 0x35E2, 0xCC, 0x35E3, 0x01, 0x35E4, 0xB1,
46293 + 0x35E5, 0xBD, 0x35E6, 0xC5, 0x35E7, 0x0B,
46294 + 0x35E8, 0x20, 0x35E9, 0x0E, 0x35EA, 0xCC,
46295 + 0x35EB, 0x01, 0x35EC, 0xB1, 0x35ED, 0xBD,
46296 + 0x35EE, 0xC6, 0x35EF, 0x3A, 0x35F0, 0x20,
46297 + 0x35F1, 0x06, 0x35F2, 0xCC, 0x35F3, 0x01,
46298 + 0x35F4, 0xB1, 0x35F5, 0xBD, 0x35F6, 0xC7,
46299 + 0x35F7, 0xC2, 0x35F8, 0xF7, 0x35F9, 0x01,
46300 + 0x35FA, 0xBF, 0x35FB, 0x39, 0x35FC, 0x43,
46301 + 0x35FD, 0x3A, 0x35FE, 0x41, 0x35FF, 0x44,
46302 + 0x3600, 0x54, 0x3601, 0x5F, 0x3602, 0x41,
46303 + 0x3603, 0x54, 0x3604, 0x4E, 0x3605, 0x0A,
46304 + 0x3606, 0x0D, 0x3607, 0x00, 0x3608, 0x43,
46305 + 0x3609, 0x3A, 0x360A, 0x45, 0x360B, 0x6E,
46306 + 0x360C, 0x5F, 0x360D, 0x53, 0x360E, 0x74,
46307 + 0x360F, 0x0A, 0x3610, 0x0D, 0x3611, 0x00,
46308 + 0x3612, 0x43, 0x3613, 0x3A, 0x3614, 0x49,
46309 + 0x3615, 0x0A, 0x3616, 0x0D, 0x3617, 0x00,
46310 + 0x3618, 0x00, 0x3400, 0x01, 0x33f8, 0x01
46318 @@ -0,0 +1,84 @@
46328 + 0x33f9, 0xbd, 0x33fa, 0x34, 0x33fb, 0x00,
46329 + 0x33fc, 0x39, 0x3400, 0x39, 0x3401, 0xCC,
46330 + 0x3402, 0x2E, 0x3403, 0x01, 0x3404, 0xFD,
46331 + 0x3405, 0xFF, 0x3406, 0xF2, 0x3407, 0x4F,
46332 + 0x3408, 0xFD, 0x3409, 0xFF, 0x340A, 0xF0,
46333 + 0x340B, 0xF6, 0x340C, 0x34, 0x340D, 0xD7,
46334 + 0x340E, 0x26, 0x340F, 0x05, 0x3410, 0xC6,
46335 + 0x3411, 0x01, 0x3412, 0xF7, 0x3413, 0x34,
46336 + 0x3414, 0xD7, 0x3415, 0xF6, 0x3416, 0x08,
46337 + 0x3417, 0x00, 0x3418, 0xF7, 0x3419, 0x34,
46338 + 0x341A, 0xD8, 0x341B, 0xC6, 0x341C, 0x01,
46339 + 0x341D, 0xF7, 0x341E, 0x08, 0x341F, 0x00,
46340 + 0x3420, 0x20, 0x3421, 0x0F, 0x3422, 0xCC,
46341 + 0x3423, 0x34, 0x3424, 0x3F, 0x3425, 0x1A,
46342 + 0x3426, 0xB3, 0x3427, 0x00, 0x3428, 0xCC,
46343 + 0x3429, 0x27, 0x342A, 0x03, 0x342B, 0xFD,
46344 + 0x342C, 0x00, 0x342D, 0xCC, 0x342E, 0x78,
46345 + 0x342F, 0x08, 0x3430, 0x00, 0x3431, 0xF6,
46346 + 0x3432, 0x08, 0x3433, 0x00, 0x3434, 0xC1,
46347 + 0x3435, 0x02, 0x3436, 0x26, 0x3437, 0xEA,
46348 + 0x3438, 0xF6, 0x3439, 0x34, 0x343A, 0xD8,
46349 + 0x343B, 0xF7, 0x343C, 0x08, 0x343D, 0x00,
46350 + 0x343E, 0x39, 0x343F, 0xBD, 0x3440, 0xF7,
46351 + 0x3441, 0xFA, 0x3442, 0x08, 0x3443, 0xCC,
46352 + 0x3444, 0x20, 0x3445, 0xA1, 0x3446, 0xED,
46353 + 0x3447, 0x05, 0x3448, 0xC6, 0x3449, 0xA4,
46354 + 0x344A, 0xED, 0x344B, 0x03, 0x344C, 0xBD,
46355 + 0x344D, 0x8B, 0x344E, 0x82, 0x344F, 0xE7,
46356 + 0x3450, 0x07, 0x3451, 0xC0, 0x3452, 0x02,
46357 + 0x3453, 0x27, 0x3454, 0x11, 0x3455, 0x5A,
46358 + 0x3456, 0x27, 0x3457, 0x0E, 0x3458, 0x5A,
46359 + 0x3459, 0x27, 0x345A, 0x39, 0x345B, 0x5A,
46360 + 0x345C, 0x27, 0x345D, 0x36, 0x345E, 0x5A,
46361 + 0x345F, 0x27, 0x3460, 0x51, 0x3461, 0x5A,
46362 + 0x3462, 0x27, 0x3463, 0x4E, 0x3464, 0x20,
46363 + 0x3465, 0x6D, 0x3466, 0x18, 0x3467, 0xFE,
46364 + 0x3468, 0x30, 0x3469, 0x1E, 0x346A, 0xF6,
46365 + 0x346B, 0x30, 0x346C, 0x22, 0x346D, 0x18,
46366 + 0x346E, 0x3A, 0x346F, 0x18, 0x3470, 0xE6,
46367 + 0x3471, 0x00, 0x3472, 0x58, 0x3473, 0x58,
46368 + 0x3474, 0xE7, 0x3475, 0x02, 0x3476, 0x1A,
46369 + 0x3477, 0xEE, 0x3478, 0x05, 0x3479, 0x18,
46370 + 0x347A, 0xE6, 0x347B, 0x00, 0x347C, 0xC4,
46371 + 0x347D, 0x03, 0x347E, 0xEA, 0x347F, 0x02,
46372 + 0x3480, 0x18, 0x3481, 0xE7, 0x3482, 0x00,
46373 + 0x3483, 0x1A, 0x3484, 0xEE, 0x3485, 0x03,
46374 + 0x3486, 0x18, 0x3487, 0xE6, 0x3488, 0x00,
46375 + 0x3489, 0xC4, 0x348A, 0x1F, 0x348B, 0xCA,
46376 + 0x348C, 0xC0, 0x348D, 0x18, 0x348E, 0xE7,
46377 + 0x348F, 0x00, 0x3490, 0xC6, 0x3491, 0x09,
46378 + 0x3492, 0x20, 0x3493, 0x3A, 0x3494, 0x1A,
46379 + 0x3495, 0xEE, 0x3496, 0x05, 0x3497, 0x18,
46380 + 0x3498, 0xE6, 0x3499, 0x00, 0x349A, 0xC4,
46381 + 0x349B, 0x03, 0x349C, 0xCA, 0x349D, 0x54,
46382 + 0x349E, 0x18, 0x349F, 0xE7, 0x34A0, 0x00,
46383 + 0x34A1, 0x1A, 0x34A2, 0xEE, 0x34A3, 0x03,
46384 + 0x34A4, 0x18, 0x34A5, 0xE6, 0x34A6, 0x00,
46385 + 0x34A7, 0xC4, 0x34A8, 0x1F, 0x34A9, 0xCA,
46386 + 0x34AA, 0x20, 0x34AB, 0x18, 0x34AC, 0xE7,
46387 + 0x34AD, 0x00, 0x34AE, 0xC6, 0x34AF, 0x74,
46388 + 0x34B0, 0x20, 0x34B1, 0x1C, 0x34B2, 0x1A,
46389 + 0x34B3, 0xEE, 0x34B4, 0x05, 0x34B5, 0x18,
46390 + 0x34B6, 0xE6, 0x34B7, 0x00, 0x34B8, 0xC4,
46391 + 0x34B9, 0x03, 0x34BA, 0xCA, 0x34BB, 0x48,
46392 + 0x34BC, 0x18, 0x34BD, 0xE7, 0x34BE, 0x00,
46393 + 0x34BF, 0x1A, 0x34C0, 0xEE, 0x34C1, 0x03,
46394 + 0x34C2, 0x18, 0x34C3, 0xE6, 0x34C4, 0x00,
46395 + 0x34C5, 0xC4, 0x34C6, 0x1F, 0x34C7, 0xCA,
46396 + 0x34C8, 0x20, 0x34C9, 0x18, 0x34CA, 0xE7,
46397 + 0x34CB, 0x00, 0x34CC, 0xC6, 0x34CD, 0x52,
46398 + 0x34CE, 0x18, 0x34CF, 0x08, 0x34D0, 0x18,
46399 + 0x34D1, 0xE7, 0x34D2, 0x00, 0x34D3, 0xAE,
46400 + 0x34D4, 0x00, 0x34D5, 0x38, 0x34D6, 0x39,
46401 + 0x34D7, 0x00, 0x3400, 0x01, 0x33f8, 0x01
46408 @@ -0,0 +1,44 @@
46418 + 0x33f9, 0xbd, 0x33fa, 0x34, 0x33fb, 0x00,
46419 + 0x33fc, 0x39, 0x3400, 0x39, 0x3401, 0xCC,
46420 + 0x3402, 0x27, 0x3403, 0x23, 0x3404, 0xFD,
46421 + 0x3405, 0xFF, 0x3406, 0xF0, 0x3407, 0x20,
46422 + 0x3408, 0x00, 0x3409, 0x3C, 0x340A, 0x3C,
46423 + 0x340B, 0x30, 0x340C, 0xF6, 0x340D, 0x00,
46424 + 0x340E, 0x4A, 0x340F, 0xC4, 0x3410, 0x7F,
46425 + 0x3411, 0xE7, 0x3412, 0x01, 0x3413, 0xF6,
46426 + 0x3414, 0x01, 0x3415, 0xBE, 0x3416, 0xC1,
46427 + 0x3417, 0x02, 0x3418, 0x27, 0x3419, 0x0E,
46428 + 0x341A, 0xE6, 0x341B, 0x01, 0x341C, 0xC1,
46429 + 0x341D, 0x14, 0x341E, 0x27, 0x341F, 0x08,
46430 + 0x3420, 0xC1, 0x3421, 0x18, 0x3422, 0x25,
46431 + 0x3423, 0x09, 0x3424, 0xC1, 0x3425, 0x1B,
46432 + 0x3426, 0x22, 0x3427, 0x05, 0x3428, 0xC6,
46433 + 0x3429, 0x5C, 0x342A, 0xF7, 0x342B, 0x20,
46434 + 0x342C, 0xA1, 0x342D, 0xF6, 0x342E, 0x01,
46435 + 0x342F, 0xBF, 0x3430, 0xC1, 0x3431, 0x01,
46436 + 0x3432, 0x26, 0x3433, 0x29, 0x3434, 0xF6,
46437 + 0x3435, 0x30, 0x3436, 0x55, 0x3437, 0xC0,
46438 + 0x3438, 0x05, 0x3439, 0xE7, 0x343A, 0x01,
46439 + 0x343B, 0xC1, 0x343C, 0x13, 0x343D, 0x23,
46440 + 0x343E, 0x04, 0x343F, 0xC6, 0x3440, 0x13,
46441 + 0x3441, 0xE7, 0x3442, 0x01, 0x3443, 0x18,
46442 + 0x3444, 0xFE, 0x3445, 0x30, 0x3446, 0x4C,
46443 + 0x3447, 0x18, 0x3448, 0x3A, 0x3449, 0x18,
46444 + 0x344A, 0xE6, 0x344B, 0x00, 0x344C, 0x58,
46445 + 0x344D, 0x58, 0x344E, 0x58, 0x344F, 0x58,
46446 + 0x3450, 0x58, 0x3451, 0xE7, 0x3452, 0x00,
46447 + 0x3453, 0xF6, 0x3454, 0x20, 0x3455, 0x04,
46448 + 0x3456, 0xC4, 0x3457, 0x1F, 0x3458, 0xEA,
46449 + 0x3459, 0x00, 0x345A, 0xF7, 0x345B, 0x20,
46450 + 0x345C, 0x04, 0x345D, 0x38, 0x345E, 0x38,
46451 + 0x345F, 0x39, 0x3400, 0x01, 0x33f8, 0x01
46459 @@ -0,0 +1,1588 @@
46501 +static u32 highflag = 0;
46502 +static u32 lowflag = 0;
46507 + int table[32] = {0x11, 0x10, 0x10, 0xf, 0xe, 0xd, 0xd, 0xc,
46508 + 0xb, 0xa, 0xa, 0x9, 0x8, 0x7, 0x7, 0x6,
46509 + 0x5, 0x5, 0x4, 0x3, 0x2, 0x2, 0x1, 0x0,
46510 + 0x3f, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a
46515 + val &= 0x1f;
46519 + val = (val1 << 2) | (val & 0x3); /* shift left 2 bits */
46539 + if ((temp > HIGH_TEMP) && (highflag == 0)) {
46541 + if ((val & 0x1f) > 1)
46542 + val = (val & 0xe0) | ((val & 0x1f) - 1);
46548 + highflag = 0;
46549 + if ((val & 0x1f) < 0x1f)
46550 + val = (val & 0xe0) | ((val & 0x1f) + 1);
46555 + if ((temp > NORMAL_TEMP2) && (lowflag == 0)) {
46557 + if ((val & 0x1f) > 1)
46558 + val = (val & 0xe0) | ((val & 0x1f) - 1);
46564 + lowflag = 0;
46565 + if ((val & 0x1f) < 0x1f)
46566 + val = (val & 0xe0) | ((val & 0x1f) + 1);
46588 + sys_reg_addr = (void __iomem *)ioremap_nocache(SYS_REG_ADDR, 0x100);
46594 + if ((val >> 30) != 0x3) { /* bit[30 31] */
46630 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
46655 + unsigned int bytes_compl = 0;
46656 + unsigned int pkts_compl = 0;
46701 + WARN(1, "tx err=0x%x, tx_info=0x%x, addr=0x%x\n",
46707 + for (i = 0; i < sizeof(struct tx_desc) / sizeof(int); i++)
46708 + pr_err("%s,%d: sg_desc word[%d]=0x%x\n",
46782 + for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
46786 + addr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
46795 + return 0;
46802 + u32 status = 0;
46958 + u32 rx_pkts_num = 0;
47009 + return 0;
47018 + u32 rx_pkts_num = 0;
47049 + if (hisi_femac_recv_queue(dev, skb, rx_pkt_info) < 0)
47075 + int work_done = 0;
47136 + return 0;
47161 + queue->head = 0;
47162 + queue->tail = 0;
47164 + return 0;
47181 + priv->tx_fifo_used_cnt = 0;
47183 + return 0;
47228 + priv->tx_fifo_used_cnt = 0;
47236 + reg = mac[1] | (mac[0] << 8); /* mac0 is high 8 bits */
47238 + /* addr2 [24 31] addr3 [16 23] addr4 [8 15] addr5 [0 7] */
47242 + return 0;
47258 + return 0;
47278 + priv->link_status = 0;
47286 + return 0;
47317 + return 0;
47427 + return 0;
47452 + /* addr2 [24 31] addr3 [16 23] addr4 [8 15] addr5 [0 7] */
47458 + val |= ((addr[0] << 8) | addr[1]); /* addr0 is high 8 bits */
47514 + int reg = 0;
47675 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
47701 + return 0;
47726 + return 0;
47732 + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
47733 + __ETHTOOL_DECLARE_LINK_MODE_MASK(supported) = { 0, };
47734 + __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising) = { 0, };
47757 + if (*ret < 0) {
47767 + phy = of_phy_connect(priv->ndev, of_node_get(node), &hisi_femac_adjust_link, 0,
47788 + phy_attached_print(phy, "phy_id=0x%.8lx, phy_mode=%s\n",
47853 + return 0;
47863 + ndev->irq = platform_get_irq(pdev, 0);
47864 + if (ndev->irq <= 0) {
47882 + return 0;
47961 + return 0;
47979 + return 0;
47998 + return 0;
48053 @@ -0,0 +1,269 @@
48065 +#define MAC_PORTSEL 0x0200
48066 +#define MAC_PORTSEL_STAT_CPU BIT(0)
48068 +#define MAC_PORTSET 0x0208
48069 +#define MAC_PORTSET_DUPLEX_FULL BIT(0)
48072 +#define MAC_SET 0x0210
48074 +#define MAX_FRAME_SIZE_MASK GENMASK(10, 0)
48076 +#define RX_COALESCE_SET 0x0340
48079 +#define RX_COALESCED_TIMER 0x74
48080 +#define QLEN_SET 0x0344
48085 +#define FC_LEVEL 0x0348
48087 +#define FC_DEACTIVE_THR_MASK GENMASK(5, 0)
48090 +#define IQFRM_DES 0x0354
48091 +#define RX_FRAME_LEN_MASK GENMASK(11, 0)
48093 +#define BITS_PAYLOAD_ERR_MASK 0x1
48095 +#define BITS_HEADER_ERR_MASK 0x1
48097 +#define BITS_PAYLOAD_DONE_MASK 0x1
48099 +#define BITS_HEADER_DONE_MASK 0x1
48100 +#define IQ_ADDR 0x0358
48101 +#define EQ_ADDR 0x0360
48102 +#define EQFRM_LEN 0x0364
48103 +#define ADDRQ_STAT 0x036C
48104 +#define TX_CNT_INUSE_MASK GENMASK(5, 0)
48107 +#define RX_COE_CTRL 0x0380
48114 +#define TSO_DBG_EN 0x03A4
48116 +#define TSO_DBG_STATE 0x03A8
48117 +#define TSO_DBG_ADDR 0x03AC
48118 +#define TSO_DBG_TX_INFO 0x03B0
48119 +#define TSO_DBG_TX_ERR 0x03B4
48121 +#define GLB_HOSTMAC_L32 0x0000
48122 +#define GLB_HOSTMAC_H16 0x0004
48123 +#define GLB_SOFT_RESET 0x0008
48124 +#define SOFT_RESET_ALL BIT(0)
48125 +#define GLB_FWCTRL 0x0010
48126 +#define FWCTRL_VLAN_ENABLE BIT(0)
48129 +#define GLB_MACTCTRL 0x0014
48134 +#define GLB_IRQ_STAT 0x0030
48135 +#define GLB_IRQ_ENA 0x0034
48136 +#define IRQ_ENA_PORT0_MASK GENMASK(7, 0)
48139 +#define GLB_IRQ_RAW 0x0038
48140 +#define IRQ_INT_RX_RDY BIT(0)
48148 +#define GLB_MAC_L32_BASE 0x0100
48149 +#define GLB_MAC_H16_BASE 0x0104
48150 +#define MACFLT_HI16_MASK GENMASK(15, 0)
48153 +#define glb_mac_h16(reg) (GLB_MAC_H16_BASE + ((reg) * 0x8))
48154 +#define glb_mac_l32(reg) (GLB_MAC_L32_BASE + ((reg) * 0x8))
48162 +#define HW_CAP_TSO BIT(0)
48218 +#define SYS_REG_ADDR 0x12028000
48219 +#define FEPHY_TRIM_CACHE 0x3022
48220 +#define FEPHY_TRIM_VALUE 0x20a1
48223 +#define LINK_STATUS 0x4
48224 +#define IS_LINK 0X4
48225 +#define SPEED_STATUS 0x18
48226 +#define SPEED_100M 0x8
48227 +#define LINK_AN_SR 0x11
48228 +#define MISC_CTRL45 0x00B4
48229 +#define MISC_CTRL47 0x00BC
48230 +#define MISC_CTRL48 0x00C0
48231 +#define TSENSOR_RESULT0 0x3ff
48232 +#define TSENSOR_RESULT1 0x3ff0000
48233 +#define TSENSOR_RESULT2 0x3ff
48234 +#define TSENSOR_RESULT3 0x3ff0000
48235 +#define TSENSOR_EN 0xc3200000
48240 +#define TSENSOR_LIMIT 0xfffff
48328 @@ -0,0 +1,109 @@
48362 + for (i = 0; i < count; i += 2) { /* Process 2 data at a time. */
48373 + return 0;
48385 + return 0;
48397 + return 0;
48409 + return 0;
48443 @@ -0,0 +1,22 @@
48454 +#define HISILICON_PHY_ID_FESTAV272 0x20669901
48455 +#define HISILICON_PHY_ID_FESTAV115 0x20669903
48456 +#define HISILICON_PHY_ID_FESTAV202 0x20669906
48457 +#define HISILICON_PHY_MASK 0xffffffff
48459 +#define MII_EXPMD 0x1d
48460 +#define MII_EXPMA 0x1e
48471 @@ -0,0 +1,318 @@
48494 + csum = skb_checksum(skb, offset, skb->len - offset, 0);
48500 + if (udp_csum == 0)
48546 + return 0;
48564 + return 0;
48570 + u32 pkt_info = 0;
48607 + u32 pkt_info = 0;
48610 + return 0;
48724 + int ret = 0;
48726 + if (dev == NULL || pause == NULL || pause->rx_pause == 0) {
48788 + return 0;
48795 @@ -0,0 +1,25 @@
48855 return 0;
48867 return 0;
48881 return 0;
48893 + memset(data + i, 0, ee->len - i);
48894 return 0;
48897 if (ret < 0) {
48937 @@ -0,0 +1,489 @@
48966 +#define MDIO_RWCTRL 0x00
48967 +#define MDIO_RO_DATA 0x04
48973 +#define BIT_MASK_FEPHY_ADDR GENMASK(4, 0)
48977 +#define BIT_OFFSET_LD_SET 0
48983 +#define BIT_OFFSET_R_TUNING 0
48984 +#define DEF_LD_AM 0x9
48985 +#define DEF_LDO_AM 0x3
48986 +#define DEF_R_TUNING 0x16
48992 +#define MII_EXPMD 0x1d
48993 +#define MII_EXPMA 0x1e
48995 +#define REG_LD_AM 0x3050
48996 +#define BIT_MASK_LD_SET GENMASK(4, 0)
48997 +#define REG_LDO_AM 0x3051
48998 +#define BIT_MASK_LDO_SET GENMASK(2, 0)
48999 +#define REG_R_TUNING 0x3052
49000 +#define BIT_MASK_R_TUNING GENMASK(5, 0)
49001 +#define REG_WR_DONE 0x3053
49002 +#define BIT_CFG_DONE BIT(0)
49004 +#define REG_DEF_ATE 0x3057
49005 +#define BIT_AUTOTRIM_DONE BIT(0)
49053 + return readl(data->membase + MDIO_RO_DATA) & 0xFFFF;
49119 + if (addr < 0) {
49252 + pr_err("festa PHY 0x3053 bit CFG_ACK value: 1\n");
49262 + pr_err("festa PHY 0x3053 wait bit CFG_ACK timeout!\n");
49266 + pr_info("FEPHY:addr=%d, la_am=0x%x, ldo_am=0x%x, r_tuning=0x%x\n",
49312 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
49385 + return 0;
49404 + return 0;
49432 @@ -0,0 +1,256 @@
49472 +#define MDIO_SINGLE_CMD 0x00
49473 +#define MDIO_SINGLE_DATA 0x04
49474 +#define MDIO_RDATA_STATUS 0x10
49513 + /* if read data is invalid, we just return 0 instead of -EAGAIN.
49517 + return 0;
49543 + /* write 0 to cancel reset */
49548 + /* RST_BIT, write 0 to reset phy, write 1 to cancel reset */
49556 + /* write 0 to cancel reset */
49563 +#define GPIO_BASE_ETH_PHY_RESET 0x20140000
49571 + val = readl(gpio_base + 0x400);
49573 + writel(val, gpio_base + 0x400);
49576 + writel(0xFF, gpio_base + (4 << GPIO_BIT_ETH_PHY_RESET));
49579 + /* Set to 0 to reset, then sleep 200ms */
49580 + writel(0x0, gpio_base + (4 << GPIO_BIT_ETH_PHY_RESET));
49584 + writel(0xFF, gpio_base + (4 << GPIO_BIT_ETH_PHY_RESET));
49615 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
49648 + return 0;
49666 + return 0;
49694 @@ -0,0 +1,32 @@
49722 + return 0;
49754 + return 0;
49765 #define RTL8211F_PHYCR1 0x18
49766 #define RTL8211F_INSR 0x1d
49786 phy_modify_paged_changed(phydev, 0xa43, RTL8211F_PHYCR1, val, val);
49789 index 0d374a294..9f2151377 100644
49801 index 0c473d75e..cb9f492fd 100644
49827 @@ -0,0 +1,27 @@
49860 @@ -0,0 +1,8 @@
49874 @@ -0,0 +1,96 @@
49976 @@ -0,0 +1,985 @@
50030 + } while (0)
50041 + } while (0)
50046 +#define __256MB__ 0x10000000
50047 +#define __128MB__ 0x8000000
50048 +#define __4KB__ 0x1000
50049 +#define __8KB__ 0x2000
50050 +#define __16KB__ 0x4000
50074 + pcie_controller_0 = 0,
50123 +#define msi_contrl_interrupt 0x830
50124 +#define MSI_CTRL_UPPER_ADDR_OFF 0x824
50125 +#define MSI_CTRL_ADDR_OFF 0x820
50126 +#define MSI_CTRL_INT_EN_OFF0 0x828
50127 +#define MSI_CTRL_INT_EN_OFF1 0x834
50128 +#define MSI_CTRL_INT_EN_OFF2 0x840
50129 +#define MSI_CTRL_INT_EN_OFF3 0x84c
50130 +#define MSI_CTRL_INT_EN_OFF4 0x858
50131 +#define MSI_CTRL_INT_EN_OFF5 0x864
50132 +#define MSI_CTRL_INT_EN_OFF6 0x870
50133 +#define MSI_CTRL_INT_EN_OFF7 0x87c
50135 +#define PCIE0_MODE_SEL (1 << 0)
50153 + for (; i >= 0; i--) {
50163 +#define PCIE_CFG_BUS(busnr) ((busnr & 0xff) << 20)
50164 +#define PCIE_CFG_DEV(devfn) ((devfn & 0xff) << 12)
50165 +#define PCIE_CFG_REG(reg) (reg & 0xffc) /* set dword align */
50171 + unsigned long address = 0;
50189 + for (i = 0; i < 10000; i++) {
50204 + int i = 0;
50221 + i = 0;
50228 + pcie_errorvalue = 0;
50229 + val = 0xffffffff;
50233 + *value = ((val >> (((unsigned int)where & 0x3) << 3)) & 0xff);
50235 + *value = ((val >> (((unsigned int)where & 0x3) << 3)) & 0xffff);
50254 + if (devfn > 0)
50258 + ((unsigned int)where & (~0x3))));
50261 + *value = (val >> (((unsigned int)where & 0x3) << 3)) & 0xff;
50263 + *value = (val >> (((unsigned int)where & 0x3) << 3)) & 0xffff;
50292 + "bus %d, devfn %d, where 0x%x, size 0x%x, value 0x%x",
50293 + bus->number & 0xff, devfn, where, size, *value);
50325 + org &= (~(0xff << (((unsigned int)where & 0x3) << 3)));
50326 + org |= (value << (((unsigned int)where & 0x3) << 3));
50328 + org &= (~(0xffff << (((unsigned int)where & 0x3) << 3)));
50329 + org |= (value << (((unsigned int)where & 0x3) << 3));
50353 + pcie_error("Cannot read from dbi! 0x%x:0x%x:0x%x!",
50354 + 0, devfn, (unsigned int)where);
50359 + org &= (~(0xff << (((unsigned int)where & 0x3) << 3)));
50360 + org |= (value << (((unsigned int)where & 0x3) << 3));
50362 + org &= (~(0xffff << (((unsigned int)where & 0x3) << 3)));
50363 + org |= (value << (((unsigned int)where & 0x3) << 3));
50371 + ((unsigned int)where & (~0x3))));
50384 + "bus %d, devfn %d, where 0x%x, size 0x%x, value 0x%x",
50385 + bus->number & 0xff, devfn, where, size, value);
50409 + unsigned short dev_contrl_reg_val = 0;
50410 + unsigned int max_rd_req_size = 0;
50418 + max_rd_req_size = (dev_contrl_reg_val >> 12) & 0x7;
50419 + if (max_rd_req_size > 0x0) {
50441 + if (msi_irq < 0) {
50469 + if (pcie_contrl == 0)
50470 + bus_start = 0;
50472 + bus_start = 0x2;
50474 + ret = devm_of_pci_get_host_bridge_resources(&pdev->dev, bus_start, 0xff, &res,
50503 + return 0;
50525 + if (pcie_contrl == 0)
50526 + bus_start = 0;
50530 + ret = devm_of_pci_get_host_bridge_resources(&pdev->dev, bus_start, 0xff, &res, &io_addr);
50560 + return 0;
50607 + unsigned int processed = 0;
50611 + for (i = 0; i < 8; i++) {
50612 + unsigned long reg = readl(dbi_base + 0x830 + i * 0xc);
50620 + writel(1 << offset, dbi_base + msi_contrl_interrupt + i * 0xc);
50637 + reg = readl(dbi_base + msi_contrl_interrupt + i * 0xc);
50641 + return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
50652 + if (pdev->bus->number == pcie_info[0].root_bus_nr ||
50654 + return 0;
50657 + if (hwirq < 0)
50668 + desc->msi_attrib.multiple = 0x5;
50676 + return 0;
50684 + irq_hw_number_t hwirq = 0;
50707 + return 0;
50744 + if (err < 0) {
50753 + if (err < 0) {
50759 + msi->pages = __get_free_pages(GFP_KERNEL, 0);
50766 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF0);
50767 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF1);
50768 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF2);
50769 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF3);
50770 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF4);
50771 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF5);
50772 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF6);
50773 + writel(0xffffffff, dbi_base + MSI_CTRL_INT_EN_OFF7);
50775 + return 0;
50790 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF0);
50791 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF1);
50792 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF2);
50793 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF3);
50794 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF4);
50795 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF5);
50796 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF6);
50797 + writel(0x0, dbi_base + MSI_CTRL_INT_EN_OFF7);
50799 + free_pages(msi->pages, 0);
50801 + if (msi->irq > 0)
50804 + for (i = 0; i < HISI_PCI_MSI_NR; i++) {
50806 + if (irq > 0)
50812 + return 0;
50870 + if (err < 0) {
50886 + return 0;
50904 + return 0;
50912 + return 0;
50916 + return 0;
50923 + return 0;
50979 + dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
50981 return 0;
51012 @@ -0,0 +1,23 @@
51023 + int "Hisi sata interworking speed mode(1.5G:0/3G:1/6G:2)"
51041 @@ -0,0 +1,5 @@
51052 @@ -0,0 +1,175 @@
51084 +MODULE_PARM_DESC(phy_mode, "sata phy mode (0:1.5G;1:3G(default);2:6G)");
51105 + unsigned int sata_port_num = 0;
51127 + return 0;
51142 + return 0;
51159 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
51183 + return 0;
51194 + return 0;
51204 + return 0;
51233 @@ -0,0 +1,39 @@
51254 + PHY_CTL0 = 0xA0,
51255 + PHY_CTL1 = 0xA4,
51256 + PHY_RST_BACK_MASK = 0xAC,
51257 + PHY_CTL2 = 0xB0,
51259 +#define PHY_DATA_INVERT (0x1 << 3)
51260 +#define PHY0_RST_MASK (0x1 << 4)
51261 +#define PHY_RST_MASK_ALL (0xF << 4)
51264 + PORT_FIFOTH = 0x44,
51265 + PORT_FIFOTH2 = 0x7C,
51266 + PORT_PHYCTL1 = 0x48,
51267 + PORT_PHYCTL = 0x74,
51269 +#define PHY_MODE_1_5G 0
51278 @@ -0,0 +1,85 @@
51301 + USB3.0 and Compatible with USB2.0. It suppots one
51369 @@ -0,0 +1,17 @@
51392 @@ -0,0 +1,310 @@
51421 +#define CRG_BASE_REG 0x140
51422 +#define USB2_UTMI_PCTRL (0x1 << 15)
51423 +#define USB2_PHY_TEST_SRST_REQ (0x1 << 14)
51424 +#define USB2_UTMI_CKSEL (0x1 << 13)
51425 +#define USB2_UTMI_CKEN (0x1 << 12)
51426 +#define USB2_REF_CKEN (0x1 << 9)
51427 +#define USB2_BUS_CKEN (0x1 << 8)
51428 +#define USB2_VCC_SRST_REQ (0x1 << 3)
51429 +#define USB2_PHY_CKEN (0x1 << 2)
51430 +#define USB2_PHY_PORT_TREQ (0x1 << 1)
51431 +#define USB2_PHY_REQ (0x1 << 0)
51433 +#define CTRL_BASE_REG 0x100e0000
51435 +#define REG_GUSB3PIPECTL0 0xc2c0
51436 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
51437 +#define PORT_DISABLE_SUSPEND (0x1 << 17)
51439 +#define REG_GCTL 0xc110
51440 +#define PORT_CAP_DIR (0x3 << 12)
51441 +#define PORT_SET_HOST (0x1 << 12)
51443 +#define GTXTHRCFG 0xc108
51444 +#define USB2_G_TXTHRCFG 0x23100000
51446 +#define GRXTHRCFG 0xc10c
51447 +#define USB2_G_RXTHRCFG 0x23100000
51449 +#define REG_GUCTL1 0xc11c
51450 +#define PARKMODE_DISABLE_FSLS (0x1 << 15)
51451 +#define PARKMODE_DISABLE_HS (0x1 << 16)
51452 +#define PARKMODE_DISABLE_SS (0x1 << 17)
51454 +#define USB2_INNO_PHY_BASE_REG 0x10110000
51455 +#define USB2_PHY_CLK_OUTPUT_REG 0x18
51456 +#define USB2_PHY_CLK_OUTPUT_VAL 0x0c
51457 +#define USB2_INNO_TRIM_OFFSET 0x0c
51459 +#define USB2_VBUS_IO_BASE_REG 0x10ff0000
51460 +#define USB2_VBUS_IO_OFFSET 0x40
51461 +#define USB2_VBUS_IO_VAL 0x431
51463 +#define USB_TRIM_BASE_REG 0x100a0000
51464 +#define USB_TRIM_OFFSET 0x38
51465 +#define USB_INNO_TRIM_MASK 0x7c
51467 +#define USB_TRIM_VAL_MASK 0x1f
51468 +#define USB_TRIM_VAL_MIN 0xf
51469 +#define USB_TRIM_VAL_MAX 0x1c
51471 +#define HS_HIGH_HEIGHT_TUNING_OFFSET 0x8
51472 +#define HS_HIGH_HEIGHT_TUNING_MASK (0x7 << 4)
51473 +#define HS_HIGH_HEIGHT_TUNING_VAL 0x5 << 4
51475 +#define PRE_EMPHASIS_TUNING_OFFSET 0x0
51476 +#define PRE_EMPHASIS_TUNING_MASK (0x7 << 0)
51477 +#define PRE_EMPHASIS_TUNING_VAL 0x7 << 0
51479 +#define PRE_EMPHASIS_STRENGTH_OFFSET 0x14
51480 +#define PRE_EMPHASIS_STRENGTH_MASK (0x7 << 2)
51481 +#define PRE_EMPHASIS_STRENGTH_VAL 0x3 << 2
51483 +#define HS_SLEW_RATE_TUNING_OFFSET 0x74
51484 +#define HS_SLEW_RATE_TUNING_MASK (0x7 << 1)
51485 +#define HS_SLEW_RATE_TUNING_VAL 0x7 << 1
51487 +#define DISCONNECT_TRIGGER_OFFSET 0x10
51488 +#define DISCONNECT_TRIGGER_MASK (0xf << 4)
51489 +#define DISCONNECT_TRIGGER_VAL 0xd << 4
51708 @@ -0,0 +1,149 @@
51789 + return 0;
51807 + return 0;
51828 + return 0;
51840 + return 0;
51863 @@ -0,0 +1,72 @@
51902 + PCIE_X2 = 0,
51924 +#define __1K__ 0x400
51925 +#define __2K__ 0x800
51926 +#define __4K__ 0x1000
51927 +#define __8K__ 0x2000
51928 +#define __64K__ 0x10000
51930 +#define CRG_NODE_IDX 0
51941 @@ -0,0 +1,803 @@
51975 +#define HIXVP_PHY_TRIM_OFFSET 0x0008
51976 +#define HIXVP_PHY_TRIM_MASK 0x1f00
51979 +#define HIXVP_PHY_SVB_OFFSET 0x0000
51980 +#define HIXVP_PHY_SVB_MASK 0x0f000000
52087 + priv->ana_cfg_0_flag = 0;
52092 + priv->ana_cfg_0_flag = 0;
52097 + priv->ana_cfg_2_flag = 0;
52102 + priv->ana_cfg_2_flag = 0;
52107 + priv->ana_cfg_4_flag = 0;
52112 + priv->ana_cfg_4_flag = 0;
52145 + priv->trim_flag = 0;
52150 + priv->trim_flag = 0;
52155 + priv->trim_flag = 0;
52159 + priv->trim_flag = 0;
52163 + priv->trim_flag = 0;
52209 + priv->svb_flag = 0;
52214 + priv->svb_predev5_flag = 0;
52219 + priv->svb_predev5_flag = 0;
52224 + priv->svb_predev5_flag = 0;
52229 + priv->svb_predev4_flag = 0;
52234 + priv->svb_predev4_flag = 0;
52239 + priv->svb_predev4_flag = 0;
52256 + priv->svb_predev3_flag = 0;
52261 + priv->svb_predev3_flag = 0;
52266 + priv->svb_predev3_flag = 0;
52271 + priv->svb_predev2_flag = 0;
52276 + priv->svb_predev2_flag = 0;
52281 + priv->svb_predev2_flag = 0;
52335 + priv->vbus_flag = 0;
52339 + priv->vbus_flag = 0;
52344 + priv->pwren_flag = 0;
52348 + priv->pwren_flag = 0;
52392 + return 0;
52434 + return 0;
52458 + return 0;
52470 + return 0;
52477 + for (i = 0; i < priv->num_clocks; i++) {
52482 + while (--i >= 0)
52492 + return 0;
52520 + return 0;
52529 + priv->phy_base = of_iomap(np, 0);
52546 + return 0;
52555 + for (i = 0; i < priv->num_clocks; i++) {
52557 + if (ret < 0) {
52558 + while (--i >= 0) {
52592 + return 0;
52600 + for (i = 0; i < priv->num_clocks; i++)
52611 + return 0;
52671 + return 0;
52689 + for (i = 0; i < priv->num_clocks; i++)
52699 + return 0;
52710 + return 0;
52720 + return 0;
52810 @@ -0,0 +1,663 @@
52846 + unsigned int spi_wdata : 8; /* [7:0] */
52865 +#define SPI_CLK_DIV 0x000
52866 +#define SPI_RW 0x004
52868 +#define SPI_WRITE 0
52875 +#define RTC_10MS_COUN 0x00
52876 +#define RTC_S_COUNT 0x04
52877 +#define RTC_M_COUNT 0x08
52878 +#define RTC_H_COUNT 0x0C
52879 +#define RTC_D_COUNT_L 0x10
52880 +#define RTC_D_COUNT_H 0x14
52882 +#define RTC_MR_10MS 0x18
52883 +#define RTC_MR_S 0x1C
52884 +#define RTC_MR_M 0x20
52885 +#define RTC_MR_H 0x24
52886 +#define RTC_MR_D_L 0x28
52887 +#define RTC_MR_D_H 0x2C
52889 +#define RTC_LR_10MS 0x30
52890 +#define RTC_LR_S 0x34
52891 +#define RTC_LR_M 0x38
52892 +#define RTC_LR_H 0x3C
52893 +#define RTC_LR_D_L 0x40
52894 +#define RTC_LR_D_H 0x44
52896 +#define RTC_LORD 0x48
52898 +#define RTC_IMSC 0x4C
52899 +#define RTC_INT_CLR 0x50
52900 +#define RTC_INT 0x54
52901 +#define RTC_INT_RAW 0x58
52903 +#define RTC_CLK 0x5C
52904 +#define RTC_POR_N 0x60
52905 +#define RTC_SAR_CTRL 0x68
52906 +#define RTC_CLK_CFG 0x6C
52908 +#define RTC_FREQ_H 0x144
52909 +#define RTC_FREQ_L 0x148
52911 +#define RTC_REG_LOCK1 0x190
52912 +#define RTC_REG_LOCK2 0x194
52913 +#define RTC_REG_LOCK3 0x198
52914 +#define RTC_REG_LOCK4 0x19C
52929 +#define RTC_10MS_COUN 0x00
52930 +#define RTC_S_COUNT 0x01
52931 +#define RTC_M_COUNT 0x02
52932 +#define RTC_H_COUNT 0x03
52933 +#define RTC_D_COUNT_L 0x04
52934 +#define RTC_D_COUNT_H 0x05
52936 +#define RTC_MR_10MS 0x06
52937 +#define RTC_MR_S 0x07
52938 +#define RTC_MR_M 0x08
52939 +#define RTC_MR_H 0x09
52940 +#define RTC_MR_D_L 0x0A
52941 +#define RTC_MR_D_H 0x0B
52943 +#define RTC_LR_10MS 0x0C
52944 +#define RTC_LR_S 0x0D
52945 +#define RTC_LR_M 0x0E
52946 +#define RTC_LR_H 0x0F
52947 +#define RTC_LR_D_L 0x10
52948 +#define RTC_LR_D_H 0x11
52950 +#define RTC_LORD 0x12
52952 +#define RTC_IMSC 0x13
52953 +#define RTC_INT_CLR 0x14
52954 +#define RTC_INT 0x15
52955 +#define RTC_INT_RAW 0x16
52957 +#define RTC_CLK 0x17
52958 +#define RTC_POR_N 0x18
52959 +#define RTC_SAR_CTRL 0x1A
52960 +#define RTC_CLK_CFG 0x1B
52962 +#define RTC_FREQ_H 0x51
52963 +#define RTC_FREQ_L 0x52
52965 +#define RTC_REG_LOCK1 0x64
52966 +#define RTC_REG_LOCK2 0x65
52967 +#define RTC_REG_LOCK3 0x66
52968 +#define RTC_REG_LOCK4 0x67
52973 +#define PWR_REG_ADDR 0x180C0000
52974 +#define PWR_REG_LENGTH 0x100
52976 +#define FREQ_H_DEFAULT 0x8
52977 +#define FREQ_L_DEFAULT 0x1B
52979 +#define LV_CTL_DEFAULT 0x20
52980 +#define CLK_DIV_DEFAULT 0x4
52981 +#define INT_RST_DEFAULT 0x0
52982 +#define INT_MSK_DEFAULT 0x4
52984 +#define AIE_INT_MASK BIT(0)
52986 +#define REG_LOAD_STAT BIT(0)
53012 + r_data.u32 = 0;
53013 + w_data.u32 = 0;
53018 + w_data.bits.spi_start = 0x1;
53029 + return 0;
53038 + r_data.u32 = 0;
53039 + w_data.u32 = 0;
53042 + w_data.bits.spi_start = 0x1;
53055 + return 0;
53062 + return 0;
53069 + return 0;
53097 + struct hibvt_time_str time_str = {0};
53098 + unsigned long seconds = 0;
53100 + unsigned char raw_value = 0;
53144 + unsigned long seconds = 0;
53146 + unsigned char raw_value = 0;
53152 + hibvt_rtc_write(rtc->regs, RTC_LR_10MS, 0);
53156 + hibvt_rtc_write(rtc->regs, RTC_LR_D_L, (days & 0xFF));
53170 + return 0;
53177 + struct hibvt_time_str time_str = {0};
53178 + unsigned long seconds = 0;
53180 + unsigned char int_state = 0;
53182 + memset(alrm, 0, sizeof(struct rtc_wkalrm));
53200 + return 0;
53207 + unsigned long seconds = 0;
53208 + unsigned char val = 0;
53214 + hibvt_rtc_write(rtc->regs, RTC_MR_10MS, 0);
53218 + hibvt_rtc_write(rtc->regs, RTC_MR_D_L, (days & 0xFF));
53227 + return 0;
53234 + unsigned char val = 0;
53242 + return 0;
53252 + unsigned char val = 0;
53274 + struct rtc_pll_info pll_info = {0};
53289 + /* & 0xff Obtains the lower eight bits of data. */
53290 + freq_l = (char)(pll_info.pll_value & 0xff);
53291 + /* pll_info.pll_value >> 8 & 0xf Obtains the last four bits of the higher eight bits. */
53292 + freq_h = (char)((pll_info.pll_value >> 8) & 0xf);
53297 + return 0;
53300 + char freq_l = 0;
53301 + char freq_h = 0;
53302 + struct rtc_pll_info pll_info = {0};
53312 + /* freq_h & 0xf << 8 :Shifts leftwards by 8 bits and obtains the lower 4 bits. */
53313 + pll_info.pll_value = (((unsigned)freq_h & 0xf) << 8) + freq_l;
53324 + return 0;
53343 + unsigned char val = 0;
53350 + * apb clk = 100MHz, spi_clk = 10MHz,so value= 0x4
53363 + writel(0x5A5AABCD, pwr_reg+0x58);
53367 + hibvt_rtc_write(spi_reg, RTC_REG_LOCK4, 0x5A); /* 0x5A:ctl order */
53368 + hibvt_rtc_write(spi_reg, RTC_REG_LOCK3, 0x5A); /* 0x5A:ctl order */
53369 + hibvt_rtc_write(spi_reg, RTC_REG_LOCK2, 0xAB); /* 0xAB:ctl order */
53370 + hibvt_rtc_write(spi_reg, RTC_REG_LOCK1, 0xCD); /* 0xCD:ctl order */
53380 + hibvt_rtc_write(spi_reg, RTC_CLK_CFG, 0x02);
53385 + hibvt_rtc_write(spi_reg, RTC_CLK_CFG, 0x03);
53388 + hibvt_rtc_write(spi_reg, RTC_CLK_CFG, 0x01);
53401 + return 0;
53414 + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
53421 + rtc->rtc_irq = platform_get_irq(pdev, 0);
53423 + hibvt_rtc_alm_interrupt, 0, pdev->name, rtc);
53444 + return 0;
53449 + return 0;
53519 + return 0;
53534 + hba->cd_gpio = of_get_named_gpio(np, "cd-gpio", 0);
53554 + hba->info_skip = 0;
53639 int err = 0;
53646 + return 0;
53721 + struct uic_command uic_cmd = {0};
53755 + hba->error_count = 0;
53813 + return 0;
53834 + hba->cd_wq = alloc_workqueue("ufshcd_cd_wq", WQ_FREEZABLE, 0);
53860 + UFSCARDHCD, hba) == 0) {
53880 return 0;
53908 + D_NO_DETECT = 0,
53915 + H_REMOVE = 0,
53921 UFSHCD_QUIRK_BROKEN_INTR_AGGR = 1 << 0,
54001 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
54008 +#define SSP_CR1_MASK_BIGEND_HISI (0x1UL << 4)
54009 +#define SSP_CR1_MASK_ALTASENS_HISI (0x1UL << 6)
54011 +#define SSP_TX_FIFO_CR(r) (r + 0x28)
54012 +#define SSP_RX_FIFO_CR(r) (r + 0x2C)
54129 + GEN_MASK_BITS(0x1, SSP_CR1_MASK_ALTASENS_HISI, 6) \
54134 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
54190 + writel(0, SSP_TX_FIFO_CR(pl022->virtbase));
54191 + writel(0, SSP_RX_FIFO_CR(pl022->virtbase));
54217 + SSP_CR0_MASK_DSS, 0);
54227 + SSP_WRITE_BITS(chip->cr1, 0x1, SSP_CR1_MASK_ALTASENS_HISI, 6);
54231 SSP_CR0_MASK_DSS, 0);
54243 int status = 0, i, num_cs;
54247 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
54252 for (i = 0; i < num_cs; i++)
54292 for (i = 0; i < num_cs; i++) {
54306 if (platform_info->autosuspend_delay > 0) {
54332 return 0;
54353 .mask = 0x000fffff,
54362 + .id = 0x00800022,
54363 + .mask = 0xffffffff,
54367 { 0, 0 },
54391 } else if (hub->descriptor->bNbrPorts == 0) {
54393 + dev_info(hub_dev, "hub can't support USB3.0\n");
54447 + * requests is 0x3[11:8], modify the field change to 0x7.
54527 return 0;
54538 +#define DWC3_PIPE_TRANS_LIMIT_MASK (0xf << 8)
54539 +#define DWC3_PIPE_TRANS_LIMIT (0x7 << 8)
54547 +#define DWC3_EVENT_PRAM_MAX_SOFFN 0x3fff
54548 +#define DWC3_EVENT_PRAM_SOFFN_MASK 0x3fff
54550 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
54587 + * NOTICE: eps_directions bitmap[0~31] 0: out ep, 1: in ep
54590 +#define DWC3_EPS_DEFAULT_DIRECTIONS 0xaaaaaaaa
54602 +#define UDC_DISCONNECTED 0
54635 @@ -0,0 +1,446 @@
54677 +#define USB3_CTRL 0x190
54678 +#define REG_SYS_STAT 0x8c
54679 +#define PCIE_USB3_MODE_MASK (0x3 << 12)
54680 +#define USB3_PCLK_OCC_SEL (0x1 << 30)
54682 +#define PERI_USB3_GTXTHRCFG 0x2310000
54684 +#define REG_GUSB3PIPECTL0 0xc2c0
54685 +#define GTXTHRCFG 0xc108
54687 +#define PCS_SSP_SOFT_RESET (0x1 << 31)
54688 +#define SUSPEND_USB3_SS_PHY (0x1 << 17)
54690 +#define GUSB2PHYCFG_OFFSET 0xc200
54691 +#define GCTL_OFFSET 0xc110
54692 +#define GUCTL_OFFSET 0xc12C
54693 +#define GFLADJ_OFFSET 0xc630
54695 +#define U2_FREECLK_EXISTS (0x1 << 30)
54696 +#define SOFITPSYNC (0x1 << 10)
54697 +#define REFCLKPER_MASK 0xffc00000
54698 +#define REFCLKPER_VAL 0x29
54701 +#define PLS1 (0x1 << 31)
54702 +#define DECR_MASK 0x7f000000
54703 +#define DECR_VAL 0xa
54706 +#define LPM_SEL (0x1 << 23)
54707 +#define FLADJ_MASK 0x003fff00
54708 +#define FLADJ_VAL 0x7f0
54712 +#define DOUBLE_PCIE_MODE 0x0
54713 +#define P0_PCIE_ADD_P1_USB3 (0x1 << 12)
54714 +#define DOUBLE_USB3 (0x2 << 12)
54717 +#define PCIE_X1_MODE (0x0 << 12)
54718 +#define USB3_MODE (0x1 << 12)
54744 + if (usb_priv->speed_id == 0)
54861 + return 0;
54883 + for (i = 0; i < hisi->num_clocks; i++) {
54888 + while (--i >= 0)
54896 + if (ret < 0) {
54897 + while (--i >= 0) {
54909 + return 0;
54971 + return 0;
55020 + for (i = 0; i < hisi->num_clocks; i++) {
55027 + return 0;
55044 + for (i = 0; i < hisi->num_clocks; i++) {
55059 + return 0;
55087 @@ -0,0 +1,54 @@
55135 +#define DEV_NODE_FLAG0 0
55147 WARN_ON(ret < 0);
55152 + u32 res = 0;
55156 + return 0;
55158 + for (i = 0; i < dwc->num_eps; i++) {
55244 * endpoint number. So USB endpoint 0x81 is 0x03.
55270 __dwc3_gadget_ep_set_halt(dep, 0, false);
55284 * index is 0, we will wrap backwards, skip the link TRB, and return
55308 + unsigned int chain_skip = 0;
55360 + dwc3_prepare_one_trb(dep, req, trb_length, 1, 0, false,
55402 for (i = 0; i < DWC3_ISOC_MAX_RETRIES; i++) {
55416 return 0;
55432 return 0;
55441 + u8 num_in_eps = 0;
55442 + u8 num_out_eps = 0;
55443 + u8 epnum = 0;
55450 + for (i = 0; i < num_eps; i++) {
55451 + if (direction & 0x1)
55462 + dep->direction = !!(direction & 0x1);
55471 + if (epnum == 0 || epnum == 1) {
55484 + dep->endpoint.caps.dir_in = !!(direction & 0x1);
55485 + dep->endpoint.caps.dir_out = !(direction & 0x1);
55493 + return 0;
55506 for (epnum = 0; epnum < total; epnum++) {
55543 @@ -0,0 +1,138 @@
55578 +static int proc_dwc3_dir_cnt = 0;
55604 + return 0;
55650 + 0, dwc->parent_entry,
55662 + return 0;
55675 + if (proc_dwc3_dir_cnt == 0) {
55680 + return 0;
55692 + usb_ext->bmAttributes = cpu_to_le32(0x0);
55749 + common->actived = 0;
55765 common->running = 0;
55766 + common->actived = 0;
55777 for (i = 0; i < ARRAY_SIZE(common->luns); ++i)
55790 + .bFirstInterface = 0,
55793 + .bFunctionSubClass = 0,
55801 .wLockDelay = 0,
55807 + .bMaxBurst = 0,
55808 + .bmAttributes = 0,
55873 if (status < 0)
55878 uac1->ac_alt = 0;
55909 + static char extension_guid[] = {0x41, 0x76, 0x9E, 0xA2, 0x04, 0xDE, 0xE3, 0x47,
55910 + 0x8B, 0x2B, 0xF4, 0x34, 0x1A, 0xFF, 0x00, 0x3B};
55916 pd->iProcessing = 0;
55917 pd->bmVideoStandards = 0;
55926 + ed->baSourceID[0] = 2;
55929 + ed->bmControls[0] = 1;
55930 + ed->bmControls[1] = 0;
55931 + ed->iExtension = 0;
55937 ctl_cls[0] = NULL; /* assigned elsewhere by configfs */
55957 if (ret < 0) {
56040 + idx = 0;
56042 + i = 0;
56044 + *pg != '\0' && *pg != '\n')
56046 + while ((pg - page < len) && (*pg == '\0' || *pg == '\n'))
56048 + buf[i] = '\0';
56049 + ret = kstrtou8(buf, 0, &pd->bmControls[idx++]);
56050 + if (ret < 0)
56151 + for (result = 0, i = 0; i < ed->bControlSize; ++i) {
56222 + idx = 0;
56224 + i = 0;
56226 + *pg != '\0' && *pg != '\n')
56228 + while ((pg - page < len) && (*pg == '\0' || *pg == '\n'))
56230 + buf[i] = '\0';
56231 + ret = kstrtou8(buf, 0, &cd->bmControls[idx++]);
56232 + if (ret < 0)
56250 UVCG_UNCOMPRESSED = 0,
56326 + ret = kstrtou##bits(page, 0, &num); \
56385 + for (result = 0, i = 0; i < frm->frame.b_frame_interval_type; ++i) {
56404 + int ret = 0, n = 0;
56484 + h->frame.dw_bytes_per_line = cpu_to_le32(0);
56534 'Y', 'U', 'Y', '2', 0x00, 0x00, 0x10, 0x00,
56535 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71
56539 + 'N', 'V', '2', '1', 0x00, 0x00, 0x10, 0x00,
56540 + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71
56556 h->desc.bAspectRatioX = 0;
56557 h->desc.bAspectRatioY = 0;
56648 + ret = kstrtou8(page, 0, &num); \
56715 + 'H', '2', '6', '4', 0x00, 0x00, 0x10, 0x00,
56716 + 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71
56730 + h->desc.bAspectRatioX = 0;
56731 + h->desc.bAspectRatioY = 0;
56732 + h->desc.bmInterfaceFlags = 0;
56733 + h->desc.bCopyProtect = 0;
56786 + return 0;
56822 + return 0;
56840 { 0, V4L2_PIX_FMT_MJPEG },
56841 + { 0, V4L2_PIX_FMT_H264 },
56873 + int ttllen = 0;
56877 + for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++) {
56896 + video->queue.buf_used = 0;
56935 if (ret < 0) {
56945 for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
56948 + for (sg_idx = 0; sg_idx < video->num_sgs; sg_idx++)
56980 + for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
56990 + for (sg_idx = 0 ; sg_idx < num_sgs ; sg_idx++) {
56998 + video->req[i]->length = 0;
57005 for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
57016 return 0;
57160 return 0;
57167 - v9fs_stat2inode(st, d_inode(dentry), dentry->d_sb, 0);
57194 return 0;
57201 - v9fs_stat2inode_dotl(st, d_inode(dentry), 0);
57266 +"block group start=%llu len=%llu flags=0x%llx doesn't match with chunk start=%llu len=%llu flags=0…
57273 + ret = 0;
57290 if (ret > 0)
57298 int fake_offset = 0;
57300 - int short_len = 0, fill_len = 0;
57303 int ret = 0;
57376 + type, de, d_createtime) == 0;
57385 + DT_DIR, de, d_createtime) == 0;
57394 + DT_DIR, de, d_createtime) == 0;
57402 + if (ctx->pos == 0) {
57429 + int fake_offset = 0;
57431 + int short_len = 0, fill_len = 0;
57432 + int ret = 0;
57444 + cpos = 0;
57457 + nr_slots = 0;
57463 + if (de->name[0] == DELETED_FLAG)
57477 + if (status < 0) {
57498 + if (short_len == 0)
57507 + fill_len = 0;
57513 + if (short_len == 0)
57524 + memset(d_createtime, 0, 8);
57551 + fake_offset = 0;
57574 + int reclen = 0;
57576 + int long_len = 0;
57578 + int short_len = 0;
57624 + if (__put_user(0, dirent->d_name + name_len))
57629 + if (__put_user(0, dirent->d_name + long_len))
57637 + u64 u_size = 0;
57653 + return 0;
57673 + buf.error = 0;
57674 + buf.result = 0;
57675 + buf.usecount = 0;
57692 + if (ret >= 0)
57709 + if (put_user(0, &(direntallbuf->direntall.d_reclen)))
57711 + if (put_user(0, &(direntallbuf->d_usecount)))
57713 + short_only = 0;
57743 memset(bhs[n]->b_data, 0, sb->s_blocksize);
57754 de = (struct msdos_dir_entry *)bhs[0]->b_data;
57757 lock_buffer(bhs[0]);
57760 memcpy(de[0].name, MSDOS_DOT, MSDOS_NAME);
57763 de[0].size = de[1].size = 0;
57764 memset(de + 2, 0, sb->s_blocksize - 2 * sizeof(*de));
57765 set_buffer_uptodate(bhs[0]);
57767 unlock_buffer(bhs[0]);
57769 mark_buffer_dirty_inode(bhs[0], dir);
57810 err = 0;
57812 + return 0;
57849 + return 0;
57867 return 0;
57874 + inode->i_ctime = inode->i_mtime = ((struct timespec64) { get_seconds(), 0 });
57935 + int err = 0;
57939 + return 0;
57944 + return 0;
57962 + raw_entry->size = 0;
57964 + if ((raw_entry->start != 0) || (raw_entry->starthi != 0)) {
58039 + month = max(1, (date >> 5) & 0xf);
58040 + day = max(1, date & 0x1f) - 1;
58042 + d_createtime[0] = year;
58046 + d_createtime[4] = ((time >> 5) & 0x3f); /*min*/
58047 + d_createtime[5] = (time & 0x1f); /*second 2s*/
58062 return (struct timespec64){ ts.tv_sec & ~1ULL, 0 };
58091 return 0;
58093 + return 0;
58096 ubifs_assert(c, 0);
58103 @@ -0,0 +1,100 @@
58205 index 31febd3e1..0fa3ac740 100644
58218 BLK_SEG_BOUNDARY_MASK = 0xFFFFFFFFUL,
58254 @@ -0,0 +1,54 @@
58314 @@ -0,0 +1,65 @@
58318 +#define DMAC_ERROR_BASE 0x64
58320 +#define DMAC_CHN_SUCCESS (DMAC_ERROR_BASE + 0x10)
58321 +#define DMAC_CHN_ERROR (DMAC_ERROR_BASE + 0x11)
58322 +#define DMAC_CHN_TIMEOUT (DMAC_ERROR_BASE + 0x12)
58323 +#define DMAC_CHN_ALLOCAT (DMAC_ERROR_BASE + 0x13)
58324 +#define DMAC_CHN_VACANCY (DMAC_ERROR_BASE + 0x14)
58325 +#define DMAC_NOT_FINISHED (DMAC_ERROR_BASE + 0xe)
58413 @@ -0,0 +1,477 @@
58439 +#define _64K (0x10000UL)
58440 +#define _128K (0x20000UL)
58441 +#define _256K (0x40000UL)
58442 +#define _512K (0x80000UL)
58443 +#define _1M (0x100000UL)
58444 +#define _2M (0x200000UL)
58445 +#define _4M (0x400000UL)
58446 +#define _8M (0x800000UL)
58447 +#define _16M (0x1000000UL)
58448 +#define _32M (0x2000000UL)
58449 +#define _64M (0x4000000UL)
58450 +#define _128M (0x8000000UL)
58451 +#define _256M (0x10000000UL)
58452 +#define _512M (0x20000000UL)
58453 +#define _1G (0x40000000ULL)
58454 +#define _2G (0x80000000ULL)
58455 +#define _4G (0x100000000ULL)
58456 +#define _8G (0x200000000ULL)
58457 +#define _16G (0x400000000ULL)
58458 +#define _64G (0x1000000000ULL)
58461 +#define FMC_CFG 0x00
58462 +#define FMC_CFG_SPI_NAND_SEL(_type) (((_size) & 0x3) << 11)
58464 +#define FMC_CFG_OP_MODE_MASK BIT_MASK(0)
58465 +#define FMC_CFG_OP_MODE_BOOT 0
58467 +#define SPI_NOR_ADDR_MODE_3BYTES (0x0 << 10)
58468 +#define SPI_NOR_ADDR_MODE_4BYTES (0x1 << 10)
58470 +#define FMC_CFG_BLOCK_SIZE(_size) (((_size) & 0x3) << 8)
58471 +#define FMC_CFG_ECC_TYPE(_type) (((_type) & 0x7) << 5)
58472 +#define FMC_CFG_PAGE_SIZE(_size) (((_size) & 0x3) << 3)
58473 +#define FMC_CFG_FLASH_SEL(_type) (((_type) & 0x3) << 1)
58474 +#define FMC_CFG_OP_MODE(_mode) ((_mode) & 0x1)
58476 +#define SPI_NAND_MFR_OTHER 0x0
58477 +#define SPI_NAND_MFR_WINBOND 0x1
58478 +#define SPI_NAND_MFR_ESMT 0x2
58479 +#define SPI_NAND_MFR_MICRON 0x3
58482 +#define SPI_NAND_SEL_MASK (0x3 << SPI_NAND_SEL_SHIFT)
58484 +#define SPI_NOR_ADDR_MODE_3_BYTES 0x0
58485 +#define SPI_NOR_ADDR_MODE_4_BYTES 0x1
58488 +#define SPI_NOR_ADDR_MODE_MASK (0x1 << SPI_NOR_ADDR_MODE_SHIFT)
58490 +#define BLOCK_SIZE_64_PAGE 0x0
58491 +#define BLOCK_SIZE_128_PAGE 0x1
58492 +#define BLOCK_SIZE_256_PAGE 0x2
58493 +#define BLOCK_SIZE_512_PAGE 0x3
58495 +#define BLOCK_SIZE_MASK (0x3 << 8)
58497 +#define ECC_TYPE_0BIT 0x0
58498 +#define ECC_TYPE_8BIT 0x1
58499 +#define ECC_TYPE_16BIT 0x2
58500 +#define ECC_TYPE_24BIT 0x3
58501 +#define ECC_TYPE_28BIT 0x4
58502 +#define ECC_TYPE_40BIT 0x5
58503 +#define ECC_TYPE_64BIT 0x6
58506 +#define ECC_TYPE_MASK (0x7 << ECC_TYPE_SHIFT)
58508 +#define PAGE_SIZE_2KB 0x0
58509 +#define PAGE_SIZE_4KB 0x1
58510 +#define PAGE_SIZE_8KB 0x2
58511 +#define PAGE_SIZE_16KB 0x3
58514 +#define PAGE_SIZE_MASK (0x3 << PAGE_SIZE_SHIFT)
58516 +#define FLASH_TYPE_SPI_NOR 0x0
58517 +#define FLASH_TYPE_SPI_NAND 0x1
58518 +#define FLASH_TYPE_NAND 0x2
58519 +#define FLASH_TYPE_UNKNOWN 0x3
58521 +#define FLASH_TYPE_SEL_MASK (0x3 << 1)
58522 +#define GET_SPI_FLASH_TYPE(_reg) (((_reg) >> 1) & 0x3)
58524 +#define FMC_GLOBAL_CFG 0x04
58527 +#define FLASH_TYPE_SEL_MASK (0x3 << 1)
58528 +#define FMC_CFG_FLASH_SEL(_type) (((_type) & 0x3) << 1)
58531 +#define FMC_SPI_TIMING_CFG 0x08
58532 +#define TIMING_CFG_TCSH(nr) (((nr) & 0xf) << 8)
58533 +#define TIMING_CFG_TCSS(nr) (((nr) & 0xf) << 4)
58534 +#define TIMING_CFG_TSHSL(nr) ((nr) & 0xf)
58536 +#define CS_HOLD_TIME 0x6
58537 +#define CS_SETUP_TIME 0x6
58538 +#define CS_DESELECT_TIME 0xf
58540 +#define FMC_PND_PWIDTH_CFG 0x0c
58541 +#define PWIDTH_CFG_RW_HCNT(_n) (((_n) & 0xf) << 8)
58542 +#define PWIDTH_CFG_R_LCNT(_n) (((_n) & 0xf) << 4)
58543 +#define PWIDTH_CFG_W_LCNT(_n) ((_n) & 0xf)
58545 +#define RW_H_WIDTH (0xa)
58546 +#define R_L_WIDTH (0xa)
58547 +#define W_L_WIDTH (0xa)
58549 +#define FMC_INT 0x18
58555 +#define FMC_INT_ERR_INVALID_MASK (0x8)
58557 +#define FMC_INT_ERR_VALID_MASK (0x4)
58559 +#define FMC_INT_OP_DONE BIT(0)
58561 +#define FMC_INT_EN 0x1c
58569 +#define FMC_INT_EN_OP_DONE BIT(0)
58571 +#define FMC_INT_CLR 0x20
58579 +#define FMC_INT_CLR_OP_DONE BIT(0)
58581 +#define FMC_INT_CLR_ALL 0xff
58583 +#define FMC_CMD 0x24
58584 +#define FMC_CMD_CMD2(_cmd) (((_cmd) & 0xff) << 8)
58585 +#define FMC_CMD_CMD1(_cmd) ((_cmd) & 0xff)
58587 +#define FMC_ADDRH 0x28
58588 +#define FMC_ADDRH_SET(_addr) ((_addr) & 0xff)
58590 +#define FMC_ADDRL 0x2c
58591 +#define FMC_ADDRL_BLOCK_MASK(_page) ((_page) & 0xffffffc0)
58592 +#define FMC_ADDRL_BLOCK_H_MASK(_page) (((_page) & 0xffff) << 16)
58593 +#define FMC_ADDRL_BLOCK_L_MASK(_page) ((_page) & 0xffc0)
58595 +#define READ_ID_ADDR 0x00
58596 +#define PROTECT_ADDR 0xa0
58597 +#define FEATURE_ADDR 0xb0
58598 +#define STATUS_ADDR 0xc0
58599 +#define FMC_OP_CFG 0x30
58602 +#define OP_CFG_MEM_IF_TYPE(_type) (((_type) & 0x7) << 7)
58603 +#define OP_CFG_ADDR_NUM(_addr) (((_addr) & 0x7) << 4)
58604 +#define OP_CFG_DUMMY_NUM(_dummy) ((_dummy) & 0xf)
58605 +#define OP_CFG_OEN_EN (0x1 << 13)
58608 +#define IF_TYPE_MASK (0x7 << IF_TYPE_SHIFT)
58614 +#define FMC_SPI_OP_ADDR 0x34
58616 +#define FMC_DATA_NUM 0x38
58617 +#define FMC_DATA_NUM_CNT(_n) ((_n) & 0x3fff)
58641 +#define FEATURE_QE_ENABLE (1 << 0)
58643 +#define FMC_OP 0x3c
58652 +#define FMC_OP_REG_OP_START BIT(0)
58654 +#define FMC_OP_DMA 0x68
58655 +#define FMC_DMA_LEN 0x40
58656 +#define FMC_DMA_LEN_SET(_len) ((_len) & 0x0fffffff)
58658 +#define FMC_DMA_AHB_CTRL 0x48
58662 +#define FMC_DMA_AHB_CTRL_BURST4_EN BIT(0)
58670 +#define FMC_DMA_SADDR_D0 0x4c
58672 +#define FMC_DMA_SADDR_D1 0x50
58674 +#define FMC_DMA_SADDR_D2 0x54
58676 +#define FMC_DMA_SADDR_D3 0x58
58678 +#define FMC_DMA_SADDR_OOB 0x5c
58681 +#define FMC_DMA_SADDRH_D0 0x200
58682 +#define FMC_DMA_SADDRH_SHIFT 0x3LL
58685 +#define FMC_DMA_SADDRH_OOB 0x210
58688 +#define FMC_DMA_BLK_SADDR 0x60
58689 +#define FMC_DMA_BLK_SADDR_SET(_addr) ((_addr) & 0xffffff)
58691 +#define FMC_DMA_BLK_LEN 0x64
58692 +#define FMC_DMA_BLK_LEN_SET(_len) ((_len) & 0xffff)
58694 +#define FMC_OP_CTRL 0x68
58695 +#define OP_CTRL_RD_OPCODE(code) (((code) & 0xff) << 16)
58696 +#define OP_CTRL_WR_OPCODE(code) (((code) & 0xff) << 8)
58697 +#define OP_CTRL_RD_OP_SEL(_op) (((_op) & 0x3) << 4)
58700 +#define OP_CTRL_DMA_OP_READY BIT(0)
58702 +#define RD_OP_READ_ALL_PAGE 0x0
58703 +#define RD_OP_READ_OOB 0x1
58704 +#define RD_OP_BLOCK_READ 0x2
58707 +#define RD_OP_MASK (0x3 << RD_OP_SHIFT)
58709 +#define OP_TYPE_DMA 0x0
58710 +#define OP_TYPE_REG 0x1
58712 +#define FMC_OP_READ 0x0
58713 +#define FMC_OP_WRITE 0x1
58714 +#define RW_OP_READ 0x0
58715 +#define RW_OP_WRITE 0x1
58717 +#define FMC_OP_PARA 0x70
58720 +#define FMC_BOOT_SET 0x74
58724 +#define FMC_STATUS 0xac
58727 +#define FMC_VERSION 0xbc
58732 +#define HIFMC_VER_100 (0x100)
58739 +#define HIFMC_ECC_ERR_NUM0_BUF0 0xc0
58740 +#define GET_ECC_ERR_NUM(_i, _reg) (((_reg) >> ((_i) * 8)) & 0xff)
58742 +#define DISABLE 0
58745 +#define HIFMC_REG_ADDRESS_LEN 0x200
58753 +#define GET_OP 0
58756 +#define STATUS_ECC_MASK (0x3 << 4)
58760 +#define STATUS_OIP_MASK (1 << 0)
58762 +#define FMC_VERSION 0xbc
58765 +#define HIFMC_VER_100 (0x100)
58772 + ((host->addr_value[0] >> 16) | (host->addr_value[1] << 16))
58792 +#define FMC_WAIT_TIMEOUT 0x2000000
58803 + } while (0)
58814 + } while (0)
58825 + } while (0)
58827 +#define BT_DBG 0 /* Boot init debug print */
58828 +#define ER_DBG 0 /* Erase debug print */
58829 +#define WR_DBG 0 /* Write debug print */
58830 +#define RD_DBG 0 /* Read debug print */
58831 +#define QE_DBG 0 /* Quad Enable debug print */
58832 +#define OP_DBG 0 /* OP command debug print */
58833 +#define DMA_DB 0 /* DMA read or write debug print */
58834 +#define AC_DBG 0 /* 3-4byte Address Cycle */
58835 +#define SR_DBG 0 /* Status Register debug print */
58836 +#define CR_DBG 0 /* Config Register debug print */
58837 +#define FT_DBG 0 /* Features debug print */
58838 +#define WE_DBG 0 /* Write Enable debug print */
58839 +#define BP_DBG 0 /* Block Protection debug print */
58840 +#define EC_DBG 0 /* enable/disable ecc0 and randomizer */
58841 +#define PM_DBG 0 /* power management debug */
58847 + } while (0)
58857 + } while (0)
58908 +#define MMC_HOST_TYPE_MMC 0 /* MMC card */
58921 +#define MMC_CARD_UNINIT 0
58936 +#define MTD_ERASE_PENDING 0x01
58937 +#define MTD_ERASING 0x02
58938 +#define MTD_ERASE_SUSPEND 0x04
58939 +#define MTD_ERASE_DONE 0x08
58940 +#define MTD_ERASE_FAILED 0x10
59028 - * @mtd->erasesize. Of course we expect @mtd->erasesize to be != 0.
59071 +#define SNOR_MFR_WINBOND 0xef
59072 +#define SNOR_MFR_ESMT 0x8c
59073 +#define SNOR_MFR_GD 0xc8
59074 +#define SNOR_MFR_XTX 0x0b
59075 +#define SNOR_MFR_PUYA 0x85
59084 +#define _2M (0x200000UL)
59085 +#define _4M (0x400000UL)
59086 +#define _8M (0x800000UL)
59087 +#define _16M (0x1000000UL)
59088 +#define _32M (0x2000000UL)
59093 +#define DEBUG_SPI_NOR_BP 0
59096 +#define SPI_NOR_SR_BP_WIDTH_4 0xf
59099 +#define SPI_NOR_SR_BP_WIDTH_3 0x7
59102 +#define LOCK_LEVEL_MAX(bp_num) (((0x01) << bp_num) - 1)
59113 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
59116 +#define SPINOR_OP_RDSR3 0x15 /* Read Status Register-3 */
59117 +#define SPINOR_OP_WRSR3 0x11 /* Write Status Register-3 1 byte*/
59119 +#define SPINOR_OP_WRCR 0x31 /* Config register write */
59121 +#define CR_DUMMY_CYCLE (0x03 << 6) /* Macronix dummy cycle bits */
59125 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
59170 * Return: 0 for success, others for failure.
59265 #define USB_DEVICE_REMOVE 0x0002
59266 #define USB_BUS_ADD 0x0003
59267 #define USB_BUS_REMOVE 0x0004
59268 +#define USB_GADGET_ADD 0x0005
59269 +#define USB_GADGET_REMOVE 0x0006
59281 #define I2C_PEC 0x0708 /* != 0 to use PEC with SMBus */
59282 #define I2C_SMBUS 0x0720 /* SMBus transfer */
59284 +#define I2C_CONFIG_MUL_REG 0x070c
59285 +#define I2C_CONFIG_FLAGS 0x070d
59303 #define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
59304 #define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_NOSTART */
59305 #define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
59306 +#define I2C_M_16BIT_REG 0x0002 /* indicate reg bit-width is 16bit */
59307 +#define I2C_M_16BIT_DATA 0x0008 /* indicate data bit-width is 16bit */
59308 +#define I2C_M_DMA 0x0004 /* indicate use dma mode */
59346 #define FAT_IOCTL_SET_ATTRIBUTES _IOW('r', 0x11, __u32)
59347 /*Android kernel has used 0x12, so we use 0x13*/
59348 #define FAT_IOCTL_GET_VOLUME_ID _IOR('r', 0x13, __u32)
59351 +#define VFAT_IOCTL_READDIR_ALL _IOR('r', 0x14, struct fat_direntall_buf)
59365 #define UVC_EVENT_FIRST (V4L2_EVENT_PRIVATE_START + 0)
59366 #define UVC_EVENT_CONNECT (V4L2_EVENT_PRIVATE_START + 0)
59467 + if (hi3516_usb_mode != NULL && strcmp(hi3516_usb_mode, "host") == 0) {
59486 NULL, 0, -1, -1, NULL, set_init_arg);
59518 rwsem_acquire(&cpu_hotplug_lock.dep_map, 0, 0, _THIS_IP_);
59534 phys_addr_t selected_size = 0;
59574 int len = 0;
59621 return 0;
59632 - unsigned char present = 0;
59660 - for (i = 0; i < nr; i++, pgoff++)
59663 - for (i = 0; i < nr; i++)
59664 - vec[i] = 0;
59678 + memset(vec, 0, nr);
59680 return 0;
59700 + *vec = 0;
59789 for (i = 0; i < gm->gm_pf_num; i++) {
59809 struct kvec *argv = &rqstp->rq_arg.head[0];
59810 struct kvec *resv = &rqstp->rq_res.head[0];
59845 return 0;
59850 + return svc_find_xprt(serv, "rdma-bc", net, AF_UNSPEC, 0);
59878 int ret = 0;
59904 $(DTC) -O $(patsubst .%,%,$(suffix $@)) -o $@ -b 0 \
59932 if (count == 0)
59948 + $IP -6 rule add table main suppress_prefixlength 0
59950 + $IP -6 rule del table main suppress_prefixlength 0
59954 + return 0