Lines Matching +full:0 +full:xf6c

68  	return 0;
201 index 0dc478a19..55416812b 100644
217 +	u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]);
221 +	clksel0 >>= reg_data->div_core_shift[0];
222 +	clksel0 &= reg_data->div_core_mask[0];
230 +	int i = 0;
248 +		if (alt_div > reg_data->div_core_mask[0]) {
252 +				__func__, alt_div, reg_data->div_core_mask[0]);
253 +			alt_div = reg_data->div_core_mask[0];
273 +		for (i = 0; i < reg_data->num_cores; i++) {
286 +	       cpuclk->reg_base + reg_data->core_reg[0]);
289  	return 0;
295 +	int i = 0;
303 -	writel(HIWORD_UPDATE(0, reg_data->div_core_mask,
312 +	       cpuclk->reg_base + reg_data->core_reg[0]);
315 +	for (i = 0; i < reg_data->num_cores; i++) {
316 +		writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
327  	return 0;
469  	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0,
471  		      0, 0, 0, 0, &res);
476 +		return 0;
492 +	u32 lcdc_type = 0;
502 +		ret = 0;
504 +		ddr_clk_cached = 0;
548 +	res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
564 +	res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
569 +		return 0;
583 +	res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
588 +		return 0;
658  	unsigned int i, bestdiv = 0;
659  	unsigned long parent_rate, best = 0, now, maxdiv;
667  			bestdiv = 0;
677  	for (i = 0; i <= maxdiv; i++) {
754  #define PLL_MODE_MASK		0x3
823 +	return 0;
842 +	for (i = 0; i < pll->rate_count; i++) {
866 +	for (i = 0; i < pll->rate_count; i++) {
894 +					return 0;
904 +	return 0;
917 +	unsigned long clk_gcd = 0;
919 +	if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
934 +		rate_table->frac = 0;
953 +		rate_table->frac = 0;
961 +		if (rate_table->frac > 0)
962 +			rate_table->dsmpd = 0;
979 +	unsigned long clk_gcd = 0;
982 +	no_out = 0;
983 +	nf_out = 0;
985 +	if (fin_hz == 0 || fout_hz == 0 || fout_hz == fin_hz)
1033 +	if ((nr_out <= PLL_NR_MAX) && (no_out > 0)) {
1050  	for (i = 0; i < pll->rate_count; i++) {
1057 +			pll->scaling = 0;
1061 +	pll->scaling = 0;
1078 -	for (i = 0; i < pll->rate_count; i++) {
1134  	if (cur.dsmpd == 0) {
1188 +		pll->scaling = 0;
1210 +			     RK3399_PLLCON3_PWRDOWN, 0),
1221 +	writel(HIWORD_UPDATE(0,
1222 +			     RK3399_PLLCON3_PWRDOWN, 0),
1249 +		pll->scaling = 0;
1282 +		pllcon0 = RK3036_PLLCON(0);
1291 +		pllcon0 = RK3399_PLLCON(0);
1328 +	return  0;
1347  	init.parent_names = &parent_names[0];
1378 +	return 0;
1390 +	np = of_parse_phandle(pll->ctx->cru_node, "rockchip,boost", 0);
1403 +		pr_debug("boost-low-con=0x%x 0x%x\n", con0, con1);
1404 +		regmap_write(pll->boost, BOOST_PLL_L_CON(0),
1405 +			     HIWORD_UPDATE(con0, BOOST_PLL_CON_MASK, 0));
1407 +			     HIWORD_UPDATE(con1, BOOST_PLL_CON_MASK, 0));
1414 +		pr_debug("boost-high-con=0x%x 0x%x\n", con0, con1);
1415 +		regmap_write(pll->boost, BOOST_PLL_H_CON(0),
1416 +			     HIWORD_UPDATE(con0, BOOST_PLL_CON_MASK, 0));
1418 +			     HIWORD_UPDATE(con1, BOOST_PLL_CON_MASK, 0));
1424 +		pr_debug("boost-backup-pll=0x%x\n", value);
1431 +		pr_debug("boost-backup-pll-usage=0x%x\n",
1440 +		pr_debug("boost-switch-threshold=0x%x\n", value);
1445 +		pr_debug("boost-statis-threshold=0x%x\n", value);
1450 +		pr_debug("boost-statis-enable=0x%x\n", value);
1456 +		pr_debug("boost-enable=0x%x\n", value);
1503 +		     HIWORD_UPDATE(0, BOOST_LOW_FREQ_EN_MASK,
1518 +		     HIWORD_UPDATE(0, BOOST_RECOVERY_MASK,
1521 +		     HIWORD_UPDATE(0, BOOST_SW_CTRL_MASK,
1559 +	u32 boost_count = 0;
1560 +	u32 freq_cnt0 = 0, freq_cnt1 = 0;
1561 +	u64 freq_cnt = 0, high_freq_time = 0;
1562 +	u32 short_count = 0, short_threshold = 0;
1563 +	u32 interval_time = 0;
1585 +	return 0;
1608 +	return 0;
1649 +	return 0;
1670 +	return 0;
1698 +	RK3036_PLL_RATE( 594000000, 1, 123, 5, 1, 0, 12582912),  /* vco = 2970000000 */
1699 +	RK3036_PLL_RATE( 593406593, 1, 123, 5, 1, 0, 10508804),  /* vco = 2967032965 */
1700 +	RK3036_PLL_RATE( 297000000, 1, 123, 5, 2, 0, 12582912),  /* vco = 2970000000 */
1701 +	RK3036_PLL_RATE( 296703297, 1, 123, 5, 2, 0, 10508807),  /* vco = 2967032970 */
1702 +	RK3036_PLL_RATE( 148500000, 1, 129, 7, 3, 0, 15728640),  /* vco = 3118500000 */
1703 +	RK3036_PLL_RATE( 148351648, 1, 123, 5, 4, 0, 10508800),  /* vco = 2967032960 */
1704 +	RK3036_PLL_RATE( 106500000, 1, 124, 7, 4, 0,  4194304),  /* vco = 2982000000 */
1705 +	RK3036_PLL_RATE(  74250000, 1, 129, 7, 6, 0, 15728640),  /* vco = 3118500000 */
1706 +	RK3036_PLL_RATE(  74175824, 1, 129, 7, 6, 0, 13550823),  /* vco = 3115384608 */
1707 +	RK3036_PLL_RATE(  65000000, 1, 113, 7, 6, 0, 12582912),  /* vco = 2730000000 */
1708 +	RK3036_PLL_RATE(  59340659, 1, 121, 7, 7, 0,  2581098),  /* vco = 2907692291 */
1709 +	RK3036_PLL_RATE(  54000000, 1, 110, 7, 7, 0,  4194304),  /* vco = 2646000000 */
1710 +	RK3036_PLL_RATE(  27000000, 1,  55, 7, 7, 0,  2097152),  /* vco = 1323000000 */
1711 +	RK3036_PLL_RATE(  26973027, 1,  55, 7, 7, 0,  1173232),  /* vco = 1321678323 */
1885 +static u32 uart_mux_idx[]	= { 2, 0, 1 };
1888  	[lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
1889  		     RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
1891  		     RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
1892  	[dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
1893  		     RK3399_PLL_CON(19), 8, 31, 0, NULL),
1895 +	[cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
1896 +		     RK3399_PLL_CON(27), 8, 31, 0, rk3399_pll_rates),
1898  	[cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
1901  	[gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
1903 +		     RK3399_PLL_CON(35), 8, 31, 0, rk3399_pll_rates),
1904  	[npll] = PLL(pll_rk3399, PLL_NPLL, "npll",  mux_pll_p, 0, RK3399_PLL_CON(40),
1906  	[vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll",  mux_pll_p, 0, RK3399_PLL_CON(48),
1908 +		     RK3399_PLL_CON(51), 8, 31, 0, rk3399_vpll_rates),
1912 -	[ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll",  mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
1913 +	[ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll",  mux_pll_p, CLK_IS_CRITICAL, RK3399_PMU_PLL_CON(0),
1956 -	.core_reg = RK3399_CLKSEL_CON(0),
1957 -	.div_core_shift = 0,
1958 -	.div_core_mask = 0x1f,
1959 +	.core_reg[0] = RK3399_CLKSEL_CON(0),
1960 +	.div_core_shift[0] = 0,
1961 +	.div_core_mask[0] = 0x1f,
1964  	.mux_core_main = 0,
1971 -	.div_core_shift = 0,
1972 -	.div_core_mask = 0x1f,
1973 +	.core_reg[0] = RK3399_CLKSEL_CON(2),
1974 +	.div_core_shift[0] = 0,
1975 +	.div_core_mask[0] = 0x1f,
1984 -	GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
1987 -	GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
1990  	MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
1993  	COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
1994  			RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
1995  			RK3399_CLKGATE_CON(12), 0, GFLAGS),
1998  			RK3399_CLKGATE_CON(30), 0, GFLAGS),
1999  	GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
2003  	GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
2004  			RK3399_CLKGATE_CON(32), 0, GFLAGS),
2008  	GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
2012  	GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
2018  	COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
2023 -	COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
2024 +	COMPOSITE(SCLK_SPDIF_DIV, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
2025  			RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
2027 -	COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
2028 +	COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", CLK_SET_RATE_PARENT,
2029  			RK3399_CLKSEL_CON(99), 0,
2040 -	COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
2041 +	COMPOSITE(SCLK_I2S0_DIV, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
2042  			RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
2044 -	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
2045 +	COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", CLK_SET_RATE_PARENT,
2046  			RK3399_CLKSEL_CON(96), 0,
2053 -	COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
2054 +	COMPOSITE(SCLK_I2S1_DIV, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
2055  			RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
2057 -	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
2058 +	COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", CLK_SET_RATE_PARENT,
2059  			RK3399_CLKSEL_CON(97), 0,
2066 -	COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
2067 +	COMPOSITE(SCLK_I2S2_DIV, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
2068  			RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
2070 -	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
2071 +	COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", CLK_SET_RATE_PARENT,
2072  			RK3399_CLKSEL_CON(98), 0,
2079 -	MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
2081  			RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
2087 -	MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
2088 +	MUX(SCLK_UART0_SRC, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
2090  	COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
2091  			RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
2092  			RK3399_CLKGATE_CON(9), 0, GFLAGS),
2093 -	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
2094 +	COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", CLK_SET_RATE_PARENT,
2095  			RK3399_CLKSEL_CON(100), 0,
2100 -	MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
2101 +	MUX(SCLK_UART_SRC, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
2103  	COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
2104  			RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
2106 -	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
2107 +	COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", CLK_SET_RATE_PARENT,
2108  			RK3399_CLKSEL_CON(101), 0,
2113  	COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
2114  			RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
2116 -	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
2117 +	COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", CLK_SET_RATE_PARENT,
2118  			RK3399_CLKSEL_CON(102), 0,
2123  	COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
2124  			RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
2126 -	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0,
2127 +	COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", CLK_SET_RATE_PARENT,
2128  			RK3399_CLKSEL_CON(103), 0,
2141  	GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
2147 -	GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
2148 +	GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IS_CRITICAL,
2149  			RK3399_CLKGATE_CON(2), 0, GFLAGS),
2150 -	GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
2151 +	GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IS_CRITICAL,
2153 -	GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
2154 +	GATE(0, "npll_aclk_cci_src", "npll", CLK_IS_CRITICAL,
2156 -	GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
2157 +	GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IS_CRITICAL,
2160 -	COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
2161 +	COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IS_CRITICAL,
2162  			RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
2167  			RK3399_CLKGATE_CON(15), 0, GFLAGS),
2184  	GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
2186  	GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
2193 -	GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
2194 +	GATE(0, "cpll_cs", "cpll", CLK_IS_CRITICAL,
2196 -	GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
2197 +	GATE(0, "gpll_cs", "gpll", CLK_IS_CRITICAL,
2199 -	GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
2200 +	GATE(0, "npll_cs", "npll", CLK_IS_CRITICAL,
2202 -	COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
2204  			RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
2205  	GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
2207 -	GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
2208 +	GATE(0, "clk_dbg_noc", "clk_cs", CLK_IS_CRITICAL,
2214  	GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
2216 -	GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
2217 +	GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IS_CRITICAL,
2220  	GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
2221  			RK3399_CLKGATE_CON(17), 0, GFLAGS),
2222 -	GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
2223 +	GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IS_CRITICAL,
2229  	GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
2235  	GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
2244  	GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
2250  	GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
2251  			RK3399_CLKGATE_CON(16), 0, GFLAGS),
2259  	GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
2265  	GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
2272 -	COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
2278  			RK3399_CLKGATE_CON(19), 0, GFLAGS),
2288 -	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
2289 +	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IS_CRITICAL,
2291 -	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
2292 +	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IS_CRITICAL,
2293  			RK3399_CLKGATE_CON(5), 0, GFLAGS),
2296  			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
2308  	GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
2310  	GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
2312 -	GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
2313 +	GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IS_CRITICAL,
2316  	GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
2319  	GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
2321 -	GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
2322 +	GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IS_CRITICAL,
2324  	GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
2330  	GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
2332 -	GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
2333 +	GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IS_CRITICAL,
2335  	GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
2339  	GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
2341 -	GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
2342 +	GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IS_CRITICAL,
2345  	COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
2347  			RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
2357 -	GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
2358 +	GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IS_CRITICAL,
2360 -	GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
2361 +	GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IS_CRITICAL,
2362  			RK3399_CLKGATE_CON(7), 0, GFLAGS),
2365  			RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
2371 -	COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
2378  	GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
2379 …GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
2380 -	GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS…
2388  	GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
2389  	GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
2390  	GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
2395  	GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
2397  	GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
2398  	GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
2399  	GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
2404 -	GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
2405 +	GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IS_CRITICAL,
2407 -	GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
2408 +	GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IS_CRITICAL,
2409  			RK3399_CLKGATE_CON(8), 0, GFLAGS),
2412  			RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
2419 -	GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
2420 -	GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
2421 +	GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 9, GFLAGS),
2422 +	GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 12, GFLAGS),
2423  	GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
2424  	GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
2425  	GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
2426  	GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
2427  	GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
2428  	GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
2429 -	GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAG…
2430 +	GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(34), 6, GFLAGS),
2433  	GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
2435  	GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
2436  	GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
2437  	GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
2438 -	GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
2439 +	GATE(0, "pclk_perilp1_noc", "pclk_perilp1", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(25), 10, GFLAGS),
2442  	COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
2445  			RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
2446  			RK3399_CLKGATE_CON(11), 0, GFLAGS),
2447 -	COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
2449  			RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
2454  			RK3399_CLKGATE_CON(29), 0, GFLAGS),
2456  	GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
2458  	GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
2465 -	COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
2468 +	COMPOSITE_NOGATE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
2470  	COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
2480  	GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
2486  	GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
2492  	GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
2495  	COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
2501  	GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
2507 -	COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
2508 +	COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
2509  			RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
2511  	COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
2514  	GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
2520  	GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
2524  			RK3399_CLKGATE_CON(28), 0, GFLAGS),
2526 -	COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
2529 +			RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
2533  			RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
2537 -	COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
2539 +	COMPOSITE_FRACMUX_NOGATE(0, "dclk_vop0_frac", "dclk_vop0_div", CLK_SET_RATE_PARENT,
2540  			RK3399_CLKSEL_CON(106), 0,
2544 -	COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
2545 +	COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
2546  			RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
2550 -	COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
2551 +	COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_dmyvpll_cpll_gpll_npll_p, 0,
2552  			RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
2554  	COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
2557  	GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
2563  	GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
2569 -	COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
2573  			RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
2576 +	COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_dmyvpll_cpll_gpll_p, 0,
2577 +			RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
2581  	COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
2582  			RK3399_CLKSEL_CON(107), 0,
2587 +	COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_dmyvpll_cpll_gpll_gpll_p, 0,
2588  			RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
2598  	GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
2600 -	GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
2605  			RK3399_CLKGATE_CON(27), 0, GFLAGS),
2606  	GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
2615 +	GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "aclk_isp1", 0,
2621 -	GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
2623 +	GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "hclk_isp1", 0,
2626  	COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
2632 -	COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
2633 +	COMPOSITE_NODIV(SCLK_CIF_OUT_SRC, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
2638  			 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
2646 -	GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
2648 +	GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(33), 0, GFLAGS),
2656  	GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
2657 …PHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
2658 +	GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", 0, RK3399_CLKGATE_CON(21), 0, GFLAGS),
2660  	GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
2664 +	GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 1, GFL…
2665 +	GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), …
2666 +	GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", 0, RK3399_CLKGATE_CON(21), 3, GFL…
2669  	MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
2671  	COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
2672  			RK3399_CLKSEL_CON(105), 0,
2674 +			RK3399_CLKGATE_CON(13), 9, GFLAGS, 0),
2676  	DIV(0, "clk_test_24m", "xin24m", 0,
2682 -	GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
2683 +	GATE(0, "clk_ddrc_lpll_src", "lpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
2684  	     0, GFLAGS),
2685 -	GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
2686 +	GATE(0, "clk_ddrc_bpll_src", "bpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
2688 -	GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
2689 +	GATE(0, "clk_ddrc_dpll_src", "dpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
2691 -	GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
2692 +	GATE(0, "clk_ddrc_gpll_src", "gpll", CLK_IS_CRITICAL, RK3399_CLKGATE_CON(3),
2694  	COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0,
2695  		       RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
2700 -	GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
2701 +	GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", CLK_IS_CRITICAL,
2702  			RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
2704 -	COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
2706  			RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
2708  	COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
2711  			RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
2713 -	COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0,
2714 +	COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", CLK_SET_RATE_PARENT,
2715  			RK3399_PMU_CLKSEL_CON(7), 0,
2719  	MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
2722  	MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
2725 -	COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
2726 -			RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
2730 +	COMPOSITE_NOMUX(0, "clk_uart4_div", "clk_uart4_src", CLK_SET_RATE_PARENT,
2731 +			RK3399_PMU_CLKSEL_CON(5), 0, 7, DFLAGS,
2732  			RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
2734 -	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,
2735 +	COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", CLK_SET_RATE_PARENT,
2736  			RK3399_PMU_CLKSEL_CON(6), 0,
2737  			RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
2743  			RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
2746 …GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFL…
2747 …GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFL…
2749 -	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GF…
2750 +	GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", 0, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
2752 …GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS…
2755  	GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
2756  	GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
2760  	GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
2761  	GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
2762  	GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
2763 -	GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
2765  	GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
2766  	GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
2767 …GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAG…
2768  	GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
2769 …GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
2771 …MU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
2776 +	GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS…
2777 +	GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS…
2778 +	GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS…
2779 +	GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", 0, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS…
2823 +			       0x594, false);
2829 +			       0x134, false);
2857  	reg_base = of_iomap(np, 0);
2910  	rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
2947 -	if ((rate * 20 > p_rate) && (p_rate % rate != 0)) {
2948 +	if (((rate * 20 > p_rate) && (p_rate % rate != 0)) ||
2979 +				*m = 0;
2997  	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
3226 -	for (i = 0; i < nclocks; i++) {
3262  #define BOOST_SWITCH_THRESHOLD		0x0024
3263  #define BOOST_FSM_STATUS		0x0028
3264  #define BOOST_PLL_L_CON(x)		((x) * 0x4 + 0x2c)
3265 +#define BOOST_PLL_CON_MASK		0xffff
3266 +#define BOOST_CORE_DIV_MASK		0x1f
3267 +#define BOOST_CORE_DIV_SHIFT		0
3268 +#define BOOST_BACKUP_PLL_MASK		0x3
3270 +#define BOOST_BACKUP_PLL_USAGE_MASK	0x1
3272 +#define BOOST_BACKUP_PLL_USAGE_BORROW	0
3274 +#define BOOST_ENABLE_MASK		0x1
3275 +#define BOOST_ENABLE_SHIFT		0
3276  #define BOOST_RECOVERY_MASK		0x1
3278  #define BOOST_SW_CTRL_MASK		0x1
3280  #define BOOST_LOW_FREQ_EN_MASK		0x1
3282 +#define BOOST_STATIS_ENABLE_MASK	0x1
3286  #define PX30_PLL_CON(x)			((x) * 0x4)
3288  #define RV1108_EMMC_CON0		0x1e8
3289  #define RV1108_EMMC_CON1		0x1ec
3291 +#define RV1126_PMU_MODE			0x0
3292 +#define RV1126_PMU_PLL_CON(x)		((x) * 0x4 + 0x10)
3293 +#define RV1126_PMU_CLKSEL_CON(x)	((x) * 0x4 + 0x100)
3294 +#define RV1126_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x180)
3295 +#define RV1126_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x200)
3296 +#define RV1126_PLL_CON(x)		((x) * 0x4)
3297 +#define RV1126_MODE_CON			0x90
3298 +#define RV1126_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
3299 +#define RV1126_CLKGATE_CON(x)		((x) * 0x4 + 0x280)
3300 +#define RV1126_SOFTRST_CON(x)		((x) * 0x4 + 0x300)
3301 +#define RV1126_GLB_SRST_FST		0x408
3302 +#define RV1126_GLB_SRST_SND		0x40c
3303 +#define RV1126_SDMMC_CON0		0x440
3304 +#define RV1126_SDMMC_CON1		0x444
3305 +#define RV1126_SDIO_CON0		0x448
3306 +#define RV1126_SDIO_CON1		0x44c
3307 +#define RV1126_EMMC_CON0		0x450
3308 +#define RV1126_EMMC_CON1		0x454
3315 +#define RK1808_PLL_CON(x)		((x) * 0x4)
3316 +#define RK1808_MODE_CON			0xa0
3317 +#define RK1808_MISC_CON			0xa4
3318 +#define RK1808_MISC1_CON		0xa8
3319 +#define RK1808_GLB_SRST_FST		0xb8
3320 +#define RK1808_GLB_SRST_SND		0xbc
3321 +#define RK1808_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
3322 +#define RK1808_CLKGATE_CON(x)		((x) * 0x4 + 0x230)
3323 +#define RK1808_SOFTRST_CON(x)		((x) * 0x4 + 0x300)
3324 +#define RK1808_SDMMC_CON0		0x380
3325 +#define RK1808_SDMMC_CON1		0x384
3326 +#define RK1808_SDIO_CON0		0x388
3327 +#define RK1808_SDIO_CON1		0x38c
3328 +#define RK1808_EMMC_CON0		0x390
3329 +#define RK1808_EMMC_CON1		0x394
3331 +#define RK1808_PMU_PLL_CON(x)		((x) * 0x4 + 0x4000)
3332 +#define RK1808_PMU_MODE_CON		0x4020
3333 +#define RK1808_PMU_CLKSEL_CON(x)	((x) * 0x4 + 0x4040)
3334 +#define RK1808_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x4080)
3336  #define RK2928_PLL_CON(x)		((x) * 0x4)
3337  #define RK2928_MODE_CON		0x40
3338  #define RK2928_CLKSEL_CON(x)	((x) * 0x4 + 0x44)
3340  #define RK3399_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x100)
3341  #define RK3399_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x110)
3344 +#define RK3568_MODE_CON0		0xc0
3345 +#define RK3568_MISC_CON0		0xc4
3346 +#define RK3568_MISC_CON1		0xc8
3347 +#define RK3568_MISC_CON2		0xcc
3348 +#define RK3568_GLB_CNT_TH		0xd0
3349 +#define RK3568_GLB_SRST_FST		0xd4
3350 +#define RK3568_GLB_SRST_SND		0xd8
3351 +#define RK3568_GLB_RST_CON		0xdc
3352 +#define RK3568_GLB_RST_ST		0xe0
3353 +#define RK3568_CLKSEL_CON(x)		((x) * 0x4 + 0x100)
3354 +#define RK3568_CLKGATE_CON(x)		((x) * 0x4 + 0x300)
3355 +#define RK3568_SOFTRST_CON(x)		((x) * 0x4 + 0x400)
3356 +#define RK3568_SDMMC0_CON0		0x580
3357 +#define RK3568_SDMMC0_CON1		0x584
3358 +#define RK3568_SDMMC1_CON0		0x588
3359 +#define RK3568_SDMMC1_CON1		0x58c
3360 +#define RK3568_SDMMC2_CON0		0x590
3361 +#define RK3568_SDMMC2_CON1		0x594
3362 +#define RK3568_EMMC_CON0		0x598
3363 +#define RK3568_EMMC_CON1		0x59c
3366 +#define RK3568_PMU_MODE_CON0		0x80
3367 +#define RK3568_PMU_CLKSEL_CON(x)	((x) * 0x4 + 0x100)
3368 +#define RK3568_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x180)
3369 +#define RK3568_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x200)
3487  #define ROCKCHIP_DDRCLK_SIP		BIT(0)
3488 +#define ROCKCHIP_DDRCLK_SCPI		0x02
3489 +#define ROCKCHIP_DDRCLK_SIP_V2		0x03
3503  #define ROCKCHIP_INVERTER_HIWORD_MASK	BIT(0)
3761  		FACTOR(_id, cname, pname, 0, 1, 1)
3936 index 1f73fa75b..0faef5fc6 100644
3978 index a3734014d..0b91e3616 100644
4107 -	if (ret <= 0) {
4151  	return 0;
4172  	return 0;
4267 +	if (ret <= 0) {
4292  	return 0;
4360  	return 0;
4370  	per_cpu(cpu_is_managed, policy->cpu) = 0;
4371 -	*setspeed = 0;
4385 index 29acaf48e..0e51ed256 100644
4476 +		return 0;
4536 +#define PX30_PMUGRF_OS_REG2		0x208
4537 +#define PX30_PMUGRF_OS_REG3		0x20c
4539 +#define RK3128_GRF_SOC_CON0		0x140
4540 +#define RK3128_GRF_OS_REG1		0x1cc
4541 +#define RK3128_GRF_DFI_WRNUM		0x220
4542 +#define RK3128_GRF_DFI_RDNUM		0x224
4543 +#define RK3128_GRF_DFI_TIMERVAL		0x22c
4545 +#define RK3128_DDR_MONITOR_DISB		((1 << (16 + 6)) + (0 << 6))
4547 +#define RK3288_PMU_SYS_REG2		0x9c
4548 +#define RK3288_GRF_SOC_CON4		0x254
4549 +#define RK3288_GRF_SOC_STATUS(n)	(0x280 + (n) * 4)
4550 +#define RK3288_DFI_EN			(0x30003 << 14)
4551 +#define RK3288_DFI_DIS			(0x30000 << 14)
4552 +#define RK3288_LPDDR_SEL		(0x10001 << 13)
4553 +#define RK3288_DDR3_SEL			(0x10000 << 13)
4555 +#define RK3328_GRF_OS_REG2		0x5d0
4557 +#define RK3368_GRF_DDRC0_CON0		0x600
4558 +#define RK3368_GRF_SOC_STATUS5		0x494
4559 +#define RK3368_GRF_SOC_STATUS6		0x498
4560 +#define RK3368_GRF_SOC_STATUS8		0x4a0
4561 +#define RK3368_GRF_SOC_STATUS9		0x4a4
4562 +#define RK3368_GRF_SOC_STATUS10		0x4a8
4563 +#define RK3368_DFI_EN			(0x30003 << 5)
4564 +#define RK3368_DFI_DIS			(0x30000 << 5)
4567 +#define READ_DRAMTYPE_INFO(n)		(((n) >> 13) & 0x7)
4568 +#define READ_CH_INFO(n)			(((n) >> 28) & 0x3)
4569 +#define READ_DRAMTYPE_INFO_V3(n, m)	((((n) >> 13) & 0x7) | ((((m) >> 12) & 0x3) << 3))
4570 +#define READ_SYSREG_VERSION(m)		(((m) >> 28) & 0xf)
4572 -#define DDRMON_CTRL	0x04
4573 -#define CLR_DDRMON_CTRL	(0x1f0000 << 0)
4574 -#define LPDDR4_EN	(0x10001 << 4)
4575 -#define HARDWARE_EN	(0x10001 << 3)
4576 -#define LPDDR3_EN	(0x10001 << 2)
4577 -#define SOFTWARE_EN	(0x10001 << 1)
4578 -#define SOFTWARE_DIS	(0x10000 << 1)
4579 -#define TIME_CNT_EN	(0x10001 << 0)
4580 +#define DDRMON_CTRL			0x04
4581 +#define CLR_DDRMON_CTRL			(0x3f0000 << 0)
4582 +#define DDR4_EN				(0x10001 << 5)
4583 +#define LPDDR4_EN			(0x10001 << 4)
4584 +#define HARDWARE_EN			(0x10001 << 3)
4585 +#define LPDDR2_3_EN			(0x10001 << 2)
4586 +#define SOFTWARE_EN			(0x10001 << 1)
4587 +#define SOFTWARE_DIS			(0x10000 << 1)
4588 +#define TIME_CNT_EN			(0x10001 << 0)
4590  #define DDRMON_CH0_COUNT_NUM		0x28
4591  #define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
4592  #define DDRMON_CH1_COUNT_NUM		0x3c
4593  #define DDRMON_CH1_DFI_ACCESS_NUM	0x40
4596 +#define PMUGRF_OS_REG2			0x308
4599 +	DDR4 = 0,
4605 +	UNUSED = 0xFF
4625 +	 * available mask, 1: available, 0: not available
4653 +	return 0;
4660 +	return 0;
4665 +	return 0;
4690 +	return 0;
4718 +	return 0;
4725 +	return 0;
4730 +	return 0;
4736 +	u32 tmp, max = 0;
4737 +	u32 i, busier_ch = 0;
4743 +	for (i = 0; i < MAX_DMC_NUM_CH; i++) {
4779 +	return 0;
4807 +	return 0;
4814 +	return 0;
4819 +	return 0;
4846 +	return 0;
4888 -	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
4891 +	for (i = 0; i < MAX_DMC_NUM_CH; i++) {
4919  	return 0;
4969 +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4974 +	node = of_parse_phandle(np, "rockchip,pmugrf", 0);
4983 +	if (READ_SYSREG_VERSION(val_3) >= 0x3)
4992 +	return 0;
5007 +	node = of_parse_phandle(np, "rockchip,grf", 0);
5016 +	return 0;
5026 +	node = of_parse_phandle(np, "rockchip,pmu", 0);
5033 +	node = of_parse_phandle(np, "rockchip,grf", 0);
5053 +	return 0;
5071 +	return 0;
5082  	data->regs = devm_platform_ioremap_resource(pdev, 0);
5096 +	return 0;
5107 +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5112 +	node = of_parse_phandle(np, "rockchip,grf", 0);
5126 +	return 0;
5168 +			return 0;
5171 +		return 0;
5242  	return 0;
5247 +	return 0;
5256 +	return 0;
5389 +	int ret = 0;
5402 +	if (ret == 0)
5420 +	int ret = 0;
5440 +	int ret = 0;
5493   * Returns 0 on success and a negative error value when @fence has been
5513  	return 0;
5529 + * Returns 0 on success and a negative error value when @fence has been
5561 + * Returns 0 on success and a negative error value when @fence has been
5667 +	if (fd < 0) {
5694  	if (fd < 0)
5832 +	u64 total_pool_size = 0;
5870 +	return 0;
5882 -	ret = alloc_chrdev_region(&dma_heap_devt, 0, NUM_HEAP_MINORS, DEVNAME);
5887 +	ret = alloc_chrdev_region(&dma_heap_devt, 0, NUM_HEAP_MINORS, DEVNAME);
5900  	return 0;
6024 +					buffer->pagecount, 0,
6042 +	return 0;
6069 +	ret = dma_map_sgtable(attachment->dev, table, direction, 0);
6083 +	dma_unmap_sgtable(attachment->dev, table, direction, 0);
6103 +	return 0;
6123 +	return 0;
6137 +	return 0;
6148 +	if ((vma->vm_flags & (VM_SHARED | VM_MAYSHARE)) == 0)
6154 +	return 0;
6209 +	if (buffer->vmap_cnt > 0) {
6290  		while (nr_clear_pages > 0) {
6300  		memset(page_address(cma_pages), 0, size);
6314 -	for (pg = 0; pg < helper_buffer->pagecount; pg++)
6316 +	for (pg = 0; pg < pagecount; pg++)
6340 -	if (ret < 0) {
6366 index 0bf688e3c..15796bc4c 100644
6428 + * of order 0 pages can significantly improve the performance of many IOMMUs
6431 +static const unsigned int orders[] = {8, 4, 0};
6443 -	for (pg = 0; pg < buffer->pagecount; pg++)
6504 +	return 0;
6530 +	int attr = 0;
6549 +	int attr = 0;
6584 +	return 0;
6607 +	return 0;
6630 +			return 0;
6632 +	return 0;
6651 +	for_each_sgtable_page(table, &piter, 0) {
6686 -	for (pg = 0; pg < helper_buffer->pagecount; pg++) {
6708 +	int ret = 0;
6710 +	for_each_sgtable_page(sgt, &piter, 0) {
6713 +		memset(vaddr, 0, PAGE_SIZE);
6741 +			for (j = 0; j < NUM_ORDERS; j++) {
6779 +	for (i = 0; i < NUM_ORDERS; i++) {
6801 +	unsigned int max_order = orders[0];
6820 +	i = 0;
6821 +	while (size_remaining > 0) {
6850 +		sg_set_page(sg, page, page_size(page), 0);
6876 +		dma_map_sgtable(dma_heap_get_dev(heap), table, DMA_BIDIRECTIONAL, 0);
6877 +		dma_unmap_sgtable(dma_heap_get_dev(heap), table, DMA_BIDIRECTIONAL, 0);
6884 -	if (ret < 0) {
6905 -	while (pg > 0)
6922 +	long num_pages = 0;
6926 +	for (i = 0; i < NUM_ORDERS; i++, pool++) {
6964 -	int ret = 0;
6967 +	for (i = 0; i < NUM_ORDERS; i++) {
6974 +			for (j = 0; j < i; j++)
7002 +	return 0;
7046  	return 0;
7190  	tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)"
7380  	return 0;
7400 +	return 0;
7420 +	return 0;
7425  	int timeout_loop = 0;
7431 +		return 0;
7437  	if (ret < 0)
7448 +		if (ret < 0)
7458  	return 0;
7462  	return ret < 0 ? ret : 0;
7470 -	case 0:
7497  	if (retval < 0)
7501 +	buf[0] = analogix_dp_ssc_supported(dp) ? DP_SPREAD_AMP_0_5 : 0;
7504 +	if (retval < 0)
7509  	if (retval < 0) {
7516  	for (lane = 0; lane < lane_count; lane++)
7521 -	pll_tries = 0;
7539  	return ((link_value >> shift) & 0xc) >> 2;
7546 -	case 0:
7570 -	case 0:
7584 -		return 0;
7600 +	u8 dpcd = 0;
7625  	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
7639  		if (retval < 0)
7647 -	for (lane = 0; lane < lane_count; lane++)
7672 -	for (lane = 0; lane < lane_count; lane++)
7680  	return 0;
7695  	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
7699 +	if (ret < 0)
7704 +	return 0;
7717  	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
7721 +	if (ret < 0)
7726 +	return 0;
7733  	int retval = 0;
7770 -	for (i = 0; i < dp->link_train.lane_count; i++) {
7796  	return ret < 0 ? ret : 0;
7840  	return 0;
7848 +	if (dp->dpcd[DP_DPCD_REV] < 0x11)
7849 +		return 0;
7852 +	if (ret < 0)
7859 +	if (ret < 0)
7864 +	return 0;
7872 +	if (dp->dpcd[DP_DPCD_REV] < 0x11)
7873 +		return 0;
7876 +	if (ret < 0)
7883 +	if (ret < 0)
7886 +	return 0;
7899 +	if (ret < 0) {
7953 +			union phy_configure_opts phy_cfg = {0};
7955 +			phy_cfg.dp.lanes = 0;
7986 -	int ret = 0;
7989 -		return 0;
8020  	int ret, num_modes = 0;
8033  			return 0;
8058 +	if (num_modes > 0 && dp->plat_data->split_mode) {
8159  	int ret = 0;
8166 +		return 0;
8180  	return 0;
8230 -	if (ret < 0) {
8250 +	if (ret < 0) {
8262  	return 0;
8470 +		ret = drm_bridge_attach(dp->encoder, bridge, NULL, 0);
8484 -	ret = drm_bridge_attach(dp->encoder, bridge, NULL, 0);
8494  	return 0;
8509  		video_info->max_link_rate = 0x0A;
8510  		video_info->max_lane_count = 0x04;
8513 +		video_info->max_link_rate = 0x14;
8514 +		video_info->max_lane_count = 0x04;
8528 +		video_info->lane_map[0] = 0;
8533 +		return 0;
8552  	return 0;
8579 +	return 0;
8593 +	return 0;
8601 +	return 0;
8619 +	for (lane = 0; lane < 4; lane++)
8653 +	return 0;
8688 +	if (ret < 0) {
8696  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8728 -		dp->irq = platform_get_irq(pdev, 0);
8729 -		irq_flags = 0;
8744 +	dp->irq = platform_get_irq(pdev, 0);
8806  	return 0;
8845  	return 0;
8854 -	if (ret < 0) {
8861  	return 0;
8870 +	return 0;
8912 -	DP_IRQ_TYPE_HP_CABLE_IN  = BIT(0),
9051 -#define COMMON_INT_MASK_1	0
9052 -#define COMMON_INT_MASK_2	0
9053 -#define COMMON_INT_MASK_3	0
9109 +	u32 i, reg = 0;
9117 +	for (i = 0; i < video_info->max_lane_count; i++)
9142 -		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
9143 -		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
9144 -		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
9145 -		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
9147 +		analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_2, 0x99);
9148 +		analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_3, 0x40);
9149 +		analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_4, 0x58);
9150 +		analogix_dp_write(dp, ANALOGIX_DP_PLL_REG_5, 0x22);
9151 +		analogix_dp_write(dp, ANALOGIX_DP_BIAS, 0x44);
9176 -	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
9177 -	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
9178 -	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
9179 -	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
9180 -	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
9181 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_1, 0xff);
9182 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_2, 0x4f);
9183 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_3, 0xe0);
9184 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_STA_4, 0xe7);
9185 +	analogix_dp_write(dp, ANALOGIX_DP_INT_STA, 0x63);
9187  	/* 0:mask,1: unmask */
9188 -	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
9189 -	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
9190 -	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
9191 -	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
9192 -	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
9193 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0x00);
9194 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0x00);
9195 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0x00);
9196 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_4, 0x00);
9197 +	analogix_dp_write(dp, ANALOGIX_DP_INT_STA_MASK, 0x00);
9216 -	analogix_dp_lane_swap(dp, 0);
9218 -	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
9219 -	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
9220 -	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
9221 -	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
9224 -	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
9225 -	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
9226 +	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_1, 0x0);
9227 +	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_2, 0x40);
9228 +	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_3, 0x0);
9229 +	analogix_dp_write(dp, ANALOGIX_DP_SYS_CTL_4, 0x0);
9231 -	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
9232 -	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
9233 +	analogix_dp_write(dp, ANALOGIX_DP_PKT_SEND_CTL, 0x0);
9234 +	analogix_dp_write(dp, ANALOGIX_DP_HDCP_CTL, 0x0);
9236 -	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
9237 +	analogix_dp_write(dp, ANALOGIX_DP_LINK_DEBUG_CTL, 0x10);
9239 -	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
9240 +	analogix_dp_write(dp, ANALOGIX_DP_PHY_TEST, 0x0);
9242 -	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
9243 -	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
9244 +	analogix_dp_write(dp, ANALOGIX_DP_VIDEO_FIFO_THRD, 0x0);
9245 +	analogix_dp_write(dp, ANALOGIX_DP_AUDIO_MARGIN, 0x20);
9247 -	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
9248 -	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
9249 +	analogix_dp_write(dp, ANALOGIX_DP_M_VID_GEN_FILTER_TH, 0x4);
9250 +	analogix_dp_write(dp, ANALOGIX_DP_M_AUD_GEN_FILTER_TH, 0x2);
9252 -	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
9253 +	analogix_dp_write(dp, ANALOGIX_DP_SOC_GENERAL_CTL, 0x00000101);
9266  	/* 0: mask, 1: unmask */
9275 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_1, 0);
9276 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_2, 0);
9277 +	analogix_dp_write(dp, ANALOGIX_DP_COMMON_INT_MASK_3, 0);
9294  	/* 0: mask, 1: unmask */
9314  	/* 0: mask, 1: unmask */
9450 -			writel(0x00, dp->reg_base + phy_pd_addr);
9451 +			analogix_dp_write(dp, phy_pd_addr, 0x00);
9459 -	int timeout_loop = 0;
9461  	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
9475 -		analogix_dp_set_pll_power_down(dp, 0);
9486 +	analogix_dp_set_pll_power_down(dp, 0);
9495  	return 0;
9516 +	analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_H, 0xbb);
9517 +	analogix_dp_write(dp, ANALOGIX_DP_HPD_DEGLITCH_L, 0x80);
9606  	reg |= AUX_HW_RETRY_COUNT_SEL(0) |
9629  			return 0;
9634  			return 0;
9651 -	int retval = 0;
9652 -	int timeout_loop = 0;
9683 -	if ((reg & AUX_STATUS_MASK) != 0) {
9692 +	writel(0x19, dp->reg_base + ANALOIGX_DP_SSC_REG);
9713 -	for (i = 0; i < 3; i++) {
9733 -		 * If Bit 3 is 0, I2C transaction.
9740 -		if (retval == 0)
9769 +		union phy_configure_opts phy_cfg = {0};
9819 +		union phy_configure_opts phy_cfg = {0};
9848 +	for (lane = 0; lane < dp->link_train.lane_count; lane++)
9854 +		union phy_configure_opts phy_cfg = {0};
9856 +		for (lane = 0; lane < dp->link_train.lane_count; lane++) {
10085  	reg = 0x0;
10093  	reg = 0x0;
10097  	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
10158  		reg = m_value & 0xff;
10161  		reg = (m_value >> 8) & 0xff;
10164  		reg = (m_value >> 16) & 0xff;
10168  		reg = n_value & 0xff;
10171  		reg = (n_value >> 8) & 0xff;
10174  		reg = (n_value >> 16) & 0xff;
10184 -		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
10185 -		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
10186 -		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
10187 +		analogix_dp_write(dp, ANALOGIX_DP_N_VID_0, 0x00);
10188 +		analogix_dp_write(dp, ANALOGIX_DP_N_VID_1, 0x80);
10189 +		analogix_dp_write(dp, ANALOGIX_DP_N_VID_2, 0x00);
10288  	reg |= (dp->video_info.h_sync_polarity << 0);
10378 -	writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0);
10379 -	writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1);
10380 -	writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2);
10381 -	writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3);
10382 +	analogix_dp_write(dp, ANALOGIX_DP_SPD_PB0, 0x00);
10383 +	analogix_dp_write(dp, ANALOGIX_DP_SPD_PB1, 0x16);
10384 +	analogix_dp_write(dp, ANALOGIX_DP_SPD_PB2, 0xCE);
10385 +	analogix_dp_write(dp, ANALOGIX_DP_SPD_PB3, 0x5D);
10388 -	writel(vsc->db[0], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0);
10390 +	analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_DB0, vsc->db[0]);
10395 +			  vsc->db[1] ? 0x8d : 0x00);
10396 +	analogix_dp_write(dp, ANALOGIX_DP_VSC_SHADOW_PB1, 0x00);
10419  		return 0;
10421  	return 0;
10467  	int num_transferred = 0;
10496  		for (i = 0; i < msg->size; i++) {
10544  		for (i = 0; i < msg->size; i++) {
10564 -	return num_transferred > 0 ? num_transferred : -EBUSY;
10632 +	 * Note that if BIST_EN is set to 1, F_SEL must be cleared to 0
10683 +	analogix_dp_write(dp, ANALOGIX_DP_AUD_CTL, 0);
10702  #define ANALOGIX_DP_VIDEO_CTL_1			0x20
10703  #define ANALOGIX_DP_VIDEO_CTL_2			0x24
10704  #define ANALOGIX_DP_VIDEO_CTL_3			0x28
10705 +#define ANALOGIX_DP_VIDEO_CTL_4			0x2C
10707  #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
10708  #define ANALOGIX_DP_VIDEO_CTL_10		0x44
10709 +#define ANALOGIX_DP_TOTAL_LINE_CFG_L		0x48
10710 +#define ANALOGIX_DP_TOTAL_LINE_CFG_H		0x4C
10711 +#define ANALOGIX_DP_ACTIVE_LINE_CFG_L		0x50
10712 +#define ANALOGIX_DP_ACTIVE_LINE_CFG_H		0x54
10713 +#define ANALOGIX_DP_V_F_PORCH_CFG		0x58
10714 +#define ANALOGIX_DP_V_SYNC_WIDTH_CFG		0x5C
10715 +#define ANALOGIX_DP_V_B_PORCH_CFG		0x60
10716 +#define ANALOGIX_DP_TOTAL_PIXEL_CFG_L		0x64
10717 +#define ANALOGIX_DP_TOTAL_PIXEL_CFG_H		0x68
10718 +#define ANALOGIX_DP_ACTIVE_PIXEL_CFG_L		0x6C
10719 +#define ANALOGIX_DP_ACTIVE_PIXEL_CFG_H		0x70
10720 +#define ANALOGIX_DP_H_F_PORCH_CFG_L		0x74
10721 +#define ANALOGIX_DP_H_F_PORCH_CFG_H		0x78
10722 +#define ANALOGIX_DP_H_SYNC_CFG_L		0x7C
10723 +#define ANALOGIX_DP_H_SYNC_CFG_H		0x80
10724 +#define ANALOGIX_DP_H_B_PORCH_CFG_L		0x84
10725 +#define ANALOGIX_DP_H_B_PORCH_CFG_H		0x88
10727  #define ANALOGIX_DP_SPDIF_AUDIO_CTL_0		0xD8
10730  #define ANALOGIX_DP_PLL_REG_4			0x9ec
10731  #define ANALOGIX_DP_PLL_REG_5			0xa00
10733 +#define ANALOIGX_DP_SSC_REG			0x104
10734 +#define ANALOGIX_DP_BIAS			0x124
10735  #define ANALOGIX_DP_PD				0x12c
10737  #define ANALOGIX_DP_IF_TYPE			0x244
10739  #define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL	0x318
10740  #define ANALOGIX_DP_VSC_SHADOW_DB0		0x31C
10741  #define ANALOGIX_DP_VSC_SHADOW_DB1		0x320
10742 +#define ANALOGIX_DP_VSC_SHADOW_PB0		0x33C
10743 +#define ANALOGIX_DP_VSC_SHADOW_PB1		0x340
10745  #define ANALOGIX_DP_LANE_MAP			0x35C
10748  #define ANALOGIX_DP_SYS_CTL_2			0x604
10749  #define ANALOGIX_DP_SYS_CTL_3			0x608
10750  #define ANALOGIX_DP_SYS_CTL_4			0x60C
10752 +#define ANALOGIX_DP_AUD_CTL			0x618
10753  #define ANALOGIX_DP_PKT_SEND_CTL		0x640
10754  #define ANALOGIX_DP_HDCP_CTL			0x648
10757  #define ANALOGIX_DP_BUF_DATA_0			0x7C0
10759  #define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
10761 +#define ANALOGIX_DP_AUD_CHANNEL_CTL		0x834
10762  #define ANALOGIX_DP_CRC_CON			0x890
10763 +#define ANALOGIX_DP_I2S_CTRL			0x9C8
10766  #define RESET_DP_TX				(0x1 << 0)
10768  #define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
10769  #define REUSE_SPD_EN				(0x1 << 3)
10772 +#define BIST_EN					(0x1 << 3)
10773 +#define BIST_WIDTH(x)				(((x) & 0x1) << 2)
10774 +#define BIST_TYPE(x)				(((x) & 0x3) << 0)
10777  #define VID_HRES_TH(x)				(((x) & 0xf) << 4)
10778  #define VID_VRES_TH(x)				(((x) & 0xf) << 0)
10780  #define VSYNC_POLARITY_CFG			(0x1 << 1)
10781  #define HSYNC_POLARITY_CFG			(0x1 << 0)
10784 +#define TOTAL_LINE_CFG_L(x)			(((x) & 0xff) << 0)
10787 +#define TOTAL_LINE_CFG_H(x)			(((x) & 0xf) << 0)
10790 +#define ACTIVE_LINE_CFG_L(x)			(((x) & 0xff) << 0)
10793 +#define ACTIVE_LINE_CFG_H(x)			(((x) & 0xf) << 0)
10796 +#define V_F_PORCH_CFG(x)			(((x) & 0xff) << 0)
10799 +#define V_SYNC_WIDTH_CFG(x)			(((x) & 0xff) << 0)
10802 +#define V_B_PORCH_CFG(x)			(((x) & 0xff) << 0)
10805 +#define TOTAL_PIXEL_CFG_L(x)			(((x) & 0xff) << 0)
10808 +#define TOTAL_PIXEL_CFG_H(x)			(((x) & 0x3f) << 0)
10811 +#define ACTIVE_PIXEL_CFG_L(x)			(((x) & 0xff) << 0)
10814 +#define ACTIVE_PIXEL_CFG_H(x)			(((x) & 0x3f) << 0)
10817 +#define H_F_PORCH_CFG_L(x)			(((x) & 0xff) << 0)
10820 +#define H_F_PORCH_CFG_H(x)			(((x) & 0xf) << 0)
10823 +#define H_SYNC_CFG_L(x)				(((x) & 0xff) << 0)
10826 +#define H_SYNC_CFG_H(x)				(((x) & 0xf) << 0)
10829 +#define H_B_PORCH_CFG_L(x)			(((x) & 0xff) << 0)
10832 +#define H_B_PORCH_CFG_H(x)			(((x) & 0xf) << 0)
10835 +#define AUD_SPDIF_EN				(0x1 << 7)
10838  #define REF_CLK_24M				(0x1 << 0)
10839  #define REF_CLK_27M				(0x0 << 0)
10841  #define FIX_M_VID				(0x1 << 2)
10842  #define M_VID_UPDATE_CTRL			(0x3 << 0)
10845 +#define MISC_CTRL_RESET				(0x1 << 4)
10846 +#define DP_AUDIO_EN				(0x1 << 0)
10849  #define SCRAMBLER_TYPE				(0x1 << 9)
10850  #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
10852  #define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
10853  #define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
10854  #define SW_TRAINING_PATTERN_SET_MASK		(0x3 << 0)
10855 +#define SW_TRAINING_PATTERN_SET_PTN3		(0x3 << 0)
10856  #define SW_TRAINING_PATTERN_SET_PTN2		(0x2 << 0)
10857  #define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
10858  #define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
10860  #define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
10861  #define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
10864 +#define AUD_CHANNEL_COUNT_6			(0x5 << 0)
10865 +#define AUD_CHANNEL_COUNT_4			(0x3 << 0)
10866 +#define AUD_CHANNEL_COUNT_2			(0x1 << 0)
10869  #define IF_UP					(0x1 << 4)
10870  #define IF_EN					(0x1 << 0)
10872  #define PSR_VID_CRC_FLUSH			(0x1 << 2)
10873  #define PSR_VID_CRC_ENABLE			(0x1 << 0)
10876 +#define I2S_EN					(0x1 << 4)
10933 +			out_bus_fmts[0] = conn->display_info.bus_formats[0];
10935 +			out_bus_fmts[0] = MEDIA_BUS_FMT_FIXED;
10973 +		in_bus_fmts[0] = MEDIA_BUS_FMT_FIXED;
11120  #define SII902X_TPI_VIDEO_DATA			0x0
11123  #define SII902X_HOTPLUG_EVENT			BIT(0)
11126 +#define SII902X_TPI_SYNC_GEN_CTRL		0x60
11127 +#define SII902X_TPI_SYNC_POLAR_DETECT		0x61
11128 +#define SII902X_TPI_HBIT_TO_HSYNC		0x62
11129 +#define SII902X_EMBEDDED_SYNC_EXTRACTION_REG	0x63
11132  #define SII902X_REG_TPI_RQB			0xc7
11165 +		   1430, 1650, 0, 720, 725, 730, 750, 0,
11170 +		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
11175 +		   2052, 2200, 0, 1080, 1084, 1094, 1125, 0,
11181 +		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
11186 +		   1760, 1980, 0, 720, 725, 730, 750, 0,
11189 +	/* 0x10 - 1024x768@60Hz */
11191 +		   1184, 1344, 0,  768, 771, 777, 806, 0,
11195 +		   796, 864, 0, 576, 581, 586, 625, 0,
11200 +		   798, 858, 0, 480, 489, 495, 525, 0,
11211 -	int num = 0, ret;
11212 +	int num = 0, ret = 0, i;
11222 +		for (i = 0; i < ARRAY_SIZE(sii902x_default_modes); i++) {
11290 +					     0x20, 0x20);
11297 +				     0x80,  0x00);
11299 +		     SII902X_EMBEDDED_SYNC_EXTRACTION_REG, 0x00);
11301 +				     0x80,  0x80);
11304 +	data[0] = vm.hfront_porch & 0xff;
11305 +	data[1] = (vm.hfront_porch >> 8) & 0x03;
11306 +	data[2] = 0;
11307 +	data[3] = 0;
11308 +	data[4] = vm.hsync_len & 0xff;
11309 +	data[5] = (vm.hsync_len >> 8) & 0x03;
11315 +				     0x80, 0x80);
11318 +				     0x40, 0x40);
11371  	buf[0] = pixel_clock_10kHz & 0xff;
11374 -	buf[3] = 0x00;
11379 +	buf[2] = vrefresh & 0xff;
11448  	ret = regmap_write(sii902x->regmap, SII902X_REG_TPI_RQB, 0x0);
11455  	ret = regmap_bulk_read(sii902x->regmap, SII902X_REG_CHIPID(0),
11489 +	if (ret < 0) {
11510  	sii902x->supplies[0].supply = "iovcc";
11514  	if (ret < 0) {
11584  #define DDC_CI_ADDR		0x37
11595  	RGB444_8B = 0x01,
11596  	RGB444_10B = 0x03,
11598  	YCbCr422_12B = 0x12,
11653 +	{ .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
11657  	{ 0x2000, 0x0000, 0x0000, 0x0000 },
11658  	{ 0x0000, 0x2000, 0x0000, 0x0000 },
11660  	{ 0x0000, 0x0000, 0x1b7c, 0x0020 }
11666 +		   1430, 1650, 0, 720, 725, 730, 750, 0,
11671 +		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
11676 +		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
11681 +		   1760, 1980, 0, 720, 725, 730, 750, 0,
11686 +		   796, 864, 0, 576, 581, 586, 625, 0,
11691 +		   798, 858, 0, 480, 489, 495, 525, 0,
11896 +	/* Maximum divider supported by hw is 0xffff */
11897 +	if (div_low > 0xffff)
11898 +		div_low = 0xffff;
11900 +	if (div_high > 0xffff)
11901 +		div_high = 0xffff;
11903 +	hdmi_writeb(hdmi, div_high & 0xff, HDMI_I2CM_SS_SCL_HCNT_0_ADDR);
11904 +	hdmi_writeb(hdmi, (div_high >> 8) & 0xff,
11906 +	hdmi_writeb(hdmi, div_low & 0xff, HDMI_I2CM_SS_SCL_LCNT_0_ADDR);
11907 +	hdmi_writeb(hdmi, (div_low >> 8) & 0xff,
11915  	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ);
11918 -	hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV);
11930 +	hdmi_writeb(hdmi, 0x48, HDMI_I2CM_SDA_HOLD);
11937  	hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0);
11940 +	if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
11946  	hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1);
11961 +		for (i = 0; plat_data->tmds_n_table[i].tmds != 0; i++) {
11973 +		for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
12060 +	unsigned int best_n = 0;
12065 +	if (hdmi_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
12082 +		if ((best_diff == 0) && (abs(n - ideal_n) > best_n_distance))
12096 +	if (n > 0)
12133  		csc_scale = 0;
12154 +			color_depth = 0;
12176 +	if (hdmi_data->pix_repet_factor > 0) {
12188 +		hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
12204 +	hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0);
12206 +	hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_1_ADDR);
12207 +	hdmi_writeb(hdmi, 0, HDMI_PHY_I2CM_DATAI_0_ADDR);
12212 +	val = (val & 0xff) << 8;
12213 +	val += hdmi_readb(hdmi, HDMI_PHY_I2CM_DATAI_0_ADDR) & 0xff;
12218   * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates:
12237  	for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++)
12242  	for (; phy_config->mpixelclock != ~0UL; phy_config++)
12247  	if (mpll_config->mpixelclock == ~0UL ||
12249  	    phy_config->mpixelclock == ~0UL)
12252 -	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce,
12256 +		depth = 0;
12262 -	dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp,
12265 -	dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0],
12269  	dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL);
12278  	return 0;
12404 +	if (hdmi->version < 0x211a) {
12436  	if (err < 0)
12540  			 * HDMI2.0 Specifies the following procedure:
12544  			drm_scdc_set_scrambling(hdmi->ddc, 0);
12547 +		hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL);
12591 -	hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
12592 -	hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
12597 +		hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0;
12598 +		hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0;
12643 -	hdmi->hdmi_data.pix_repet_factor = 0;
12644 -	hdmi->hdmi_data.hdcp_enable = 0;
12650 +	 * vp_pr_cd[3:0]:
12655 +		(mode->flags & DRM_MODE_FLAG_DBLCLK) ? 1 : 0;
12793 +	int i,  ret = 0;
12795 +	memset(metedata, 0, sizeof(*metedata));
12798 -		return 0;
12812 +		for (i = 0; i < ARRAY_SIZE(dw_hdmi_default_modes); i++) {
12827 +		info->edid_hdmi_dc_modes = 0;
12828 +		info->hdmi.y420_dc_modes = 0;
12829 +		info->color_formats = 0;
12877  		return 0;
12920  	return 0;
13057 +		case 0x01:
13060 +		case 0x03:
13063 +		case 0x09:
13071 +		case 0x0b:
13079 +		case 0x14:
13082 +		case 0x16:
13087 +			dev_err(hdmi->dev, "unexpected mapping: 0x%x\n",
13167 -	dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
13170 +		dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n",
13175  	return 0;
13184  		return 0;
13194 +		return 0;
13252 +		hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK);
13308 +		hdmi_writeb(hdmi, 0x00, HDMI_A_APIINTMSK);
13333 +		return 0;
13377 +	if (hdmi->version < 0x211a) {
13379 +		return 0;
13385 +		return 0;
13403 +		return 0;
13442 +	return 0;
13475 +	{HDMI_AUD_CONF0, 0x3624},
13478 +	{HDMI_A_HDCPCFG0, 0x52bb},
13479 +	{0x7800, 0x7818},
13480 +	{0x7900, 0x790e},
13482 +	{HDMI_I2CM_SLAVE, 0x7e31},
13488 +	u32 i = 0, j = 0, val = 0;
13491 +	for (i = 0; i < 16; i++)
13495 +	for (i = 0; i < ARRAY_SIZE(hdmi_reg_table); i++) {
13499 +			if ((j - hdmi_reg_table[i].reg_base) % 16 == 0)
13506 +	return 0;
13552 +	for (i = 0; i < 0x28; i++)
13555 +	return 0;
13576 +	if (reg > 0x28) {
13625 +		.num_res = 0,
13672 +	return 0;
13690 +	bool hdcp1x_enable = 0;
13724  	irq = platform_get_irq(pdev, 0);
13725  	if (irq < 0) {
13783  	memset(&pdevinfo, 0, sizeof(pdevinfo));
13862  	hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0);
13903 +		hdmi_writeb(hdmi, 0x68, HDMI_IH_MUTE_CEC_STAT0);
13967 +	 * At this time, cat /sys/class/drm/card 0-HDMI-A-1/status is connected.
13988  #define HDMI_A_PRESETUP                         0x501A
13989  #define HDMI_A_SRM_BASE                         0x5020
13992 +#define HDMI_CEC_CTRL                           0x7D00
13993 +#define HDMI_CEC_STAT                           0x7D01
13994 +#define HDMI_CEC_MASK                           0x7D02
13995 +#define HDMI_CEC_POLARITY                       0x7D03
13996 +#define HDMI_CEC_INT                            0x7D04
13997 +#define HDMI_CEC_ADDR_L                         0x7D05
13998 +#define HDMI_CEC_ADDR_H                         0x7D06
13999 +#define HDMI_CEC_TX_CNT                         0x7D07
14000 +#define HDMI_CEC_RX_CNT                         0x7D08
14001 +#define HDMI_CEC_TX_DATA0                       0x7D10
14002 +#define HDMI_CEC_TX_DATA1                       0x7D11
14003 +#define HDMI_CEC_TX_DATA2                       0x7D12
14004 +#define HDMI_CEC_TX_DATA3                       0x7D13
14005 +#define HDMI_CEC_TX_DATA4                       0x7D14
14006 +#define HDMI_CEC_TX_DATA5                       0x7D15
14007 +#define HDMI_CEC_TX_DATA6                       0x7D16
14008 +#define HDMI_CEC_TX_DATA7                       0x7D17
14009 +#define HDMI_CEC_TX_DATA8                       0x7D18
14010 +#define HDMI_CEC_TX_DATA9                       0x7D19
14011 +#define HDMI_CEC_TX_DATA10                      0x7D1a
14012 +#define HDMI_CEC_TX_DATA11                      0x7D1b
14013 +#define HDMI_CEC_TX_DATA12                      0x7D1c
14014 +#define HDMI_CEC_TX_DATA13                      0x7D1d
14015 +#define HDMI_CEC_TX_DATA14                      0x7D1e
14016 +#define HDMI_CEC_TX_DATA15                      0x7D1f
14017 +#define HDMI_CEC_RX_DATA0                       0x7D20
14018 +#define HDMI_CEC_RX_DATA1                       0x7D21
14019 +#define HDMI_CEC_RX_DATA2                       0x7D22
14020 +#define HDMI_CEC_RX_DATA3                       0x7D23
14021 +#define HDMI_CEC_RX_DATA4                       0x7D24
14022 +#define HDMI_CEC_RX_DATA5                       0x7D25
14023 +#define HDMI_CEC_RX_DATA6                       0x7D26
14024 +#define HDMI_CEC_RX_DATA7                       0x7D27
14025 +#define HDMI_CEC_RX_DATA8                       0x7D28
14026 +#define HDMI_CEC_RX_DATA9                       0x7D29
14027 +#define HDMI_CEC_RX_DATA10                      0x7D2a
14028 +#define HDMI_CEC_RX_DATA11                      0x7D2b
14029 +#define HDMI_CEC_RX_DATA12                      0x7D2c
14030 +#define HDMI_CEC_RX_DATA13                      0x7D2d
14031 +#define HDMI_CEC_RX_DATA14                      0x7D2e
14032 +#define HDMI_CEC_RX_DATA15                      0x7D2f
14033 +#define HDMI_CEC_LOCK                           0x7D30
14034 +#define HDMI_CEC_WKUPCTRL                       0x7D31
14037  #define HDMI_I2CM_SLAVE                         0x7E00
14038  #define HDMI_I2CM_ADDRESS                       0x7E01
14040  #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR            0x7E10
14041  #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR            0x7E11
14042  #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR            0x7E12
14043 +#define HDMI_I2CM_SDA_HOLD                      0x7E13
14048  	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
14049  	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
14052 +	HDMI_FC_GCP_SET_AVMUTE = 0x2,
14053 +	HDMI_FC_GCP_CLEAR_AVMUTE = 0x1,
14056  	HDMI_FC_DBGFORCE_FORCEAUDIO = 0x10,
14057  	HDMI_FC_DBGFORCE_FORCEVIDEO = 0x1,
14059  	HDMI_I2CM_CTLINT_NAC_MASK = 0x40,
14060  	HDMI_I2CM_CTLINT_ARB_POL = 0x8,
14061  	HDMI_I2CM_CTLINT_ARB_MASK = 0x4,
14064 +	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
14065 +	HDMI_I2CM_DIV_FAST_MODE = 0x8,
14066 +	HDMI_I2CM_DIV_STD_MODE = 0,
14129 +	if (mode->clock == 0) {
14130 +		DRM_ERROR("dsi mode clock is 0!\n");
14131 +		return 0;
14166  	dw_mipi_dsi_set_mode(dsi, 0);
14168 +		dw_mipi_dsi_set_mode(dsi->slave, 0);
14218  	dw_mipi_dsi_set_mode(dsi, 0);
14248 +		dw_mipi_dsi_set_mode(dsi, 0);
14250 +			dw_mipi_dsi_set_mode(dsi->slave, 0);
14409  		*val = (state->ctm) ? state->ctm->base.id : 0;
14411  		*val = (state->gamma_lut) ? state->gamma_lut->base.id : 0;
14414 +		*val = (state->cubic_lut) ? state->cubic_lut->base.id : 0;
14417  		*val = 0;
14515   *	Setting this to NULL (blob property value set to 0) means a
14536 + *	Setting this to NULL (blob property value set to 0) means the output
14553 - *	choose to interpolate between LUT[0] and LUT[4]).
14558 + *	interpolate between LUT[0] and LUT[4]).
14560   *	Setting this to NULL (blob property value set to 0) means a
14587 +	return 0;
14593 +	return 0;
14628 -	 * 0x7e in the EDID is the number of extension blocks. The EDID
14630 -	 * of 0x7e in the EDID of the _index_ of the last block in the
14633 -	last_block = edid[0x7e];
14634 +	u8 num_of_ext = edid[0x7e];
14678 +	case 0:
14680 +		*max_lanes = 0;
14681 +		*max_rate_per_lane = 0;
14717 +				hdmi_dsc->bpc_supported = 0;
14754 +			case 0:
14756 +				hdmi_dsc->max_slices = 0;
14757 +				hdmi_dsc->clk_per_slice = 0;
14864 +	drm_send_event_helper(dev, e, 0);
14874 +	drm_send_event_helper(dev, e, 0);
14883  		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
14884  		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
14887 +		{ .format = DRM_FORMAT_NV20,		.depth = 0,
14888 +		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
14889 +		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 2,
14891 +		{ .format = DRM_FORMAT_NV30,		.depth = 0,
14892 +		  .num_planes = 2, .char_per_block = { 5, 5, 0 },
14893 +		  .block_w = { 4, 2, 0 }, .block_h = { 1, 1, 0 }, .hsub = 1,
14896  		{ .format = DRM_FORMAT_Q410,		.depth = 0,
14898  		  .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 }, .hsub = 0,
14917  	return 0;
14920  	DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb_ioctl, 0),
14923 -	DRM_IOCTL_DEF(DRM_IOCTL_MODE_CREATE_DUMB, drm_mode_create_dumb_ioctl, 0),
14924 -	DRM_IOCTL_DEF(DRM_IOCTL_MODE_MAP_DUMB, drm_mode_mmap_dumb_ioctl, 0),
14925 -	DRM_IOCTL_DEF(DRM_IOCTL_MODE_DESTROY_DUMB, drm_mode_destroy_dumb_ioctl, 0),
14929  	DRM_IOCTL_DEF(DRM_IOCTL_MODE_OBJ_GETPROPERTIES, drm_mode_obj_get_properties_ioctl, 0),
14985  	uint32_t crtcs_out = 0;
15001  	count_in = count_out = 0;
15014  	int ret = 0;
15032  	if (cl->object_count == 0) {
15069  	if (fd < 0) {
15083  	return 0;
15101  	int ret = 0;
15151  	int ret = 0;
15192 +			"CUBIC_LUT", 0);
15199 +			"CUBIC_LUT_SIZE", 0, UINT_MAX);
15207  				   "IN_FORMATS", 0);
15209 index 0f99e5453..d42c7310b 100644
15214  	out->name[DRM_DISPLAY_MODE_LEN-1] = 0;
15222  	return 0;
15244 + * Returns 0 on success or a negative error code on failure.
15434 +	cnt = 0;
15459 +	for (i = 0; i < cnt; i++) {
15472 +	return 0;
15488 +	for (i = 0; i < seq->cmd_cnt; i++) {
15493 +			err = mipi_dsi_compression_mode(dsi, cmd->payload[0]);
15524 +		if (err < 0)
15531 +	return 0;
15538  	if (num == 0)
15565 +		if (regulator_is_enabled(p->supply) > 0)
15569 +		if (err < 0)
15573 +	return 0;
15583 +			if (err < 0)
15590 +	return 0;
15599 +	if (err < 0) {
15607 +	return 0;
15616  		return 0;
15618 -	gpiod_set_value_cansleep(p->enable_gpio, 0);
15624 +	gpiod_direction_output(p->enable_gpio, 0);
15633  		return 0;
15637  	if (err < 0) {
15653 +	gpiod_direction_output(p->reset_gpio, 0);
15670  	return 0;
15682 +		return 0;
15687 +	if (ret < 0)
15692 +	return 0;
15703 +		return 0;
15708 +	if (ret < 0)
15713 +	return brightness & 0xff;
15761  	ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
15779  	case 0:
15856 +			bus_flags = 0;
15907 +	return 0;
15973 +	return 0;
16005  	if (err < 0)
16014 +		memset(&props, 0, sizeof(props));
16076  	return 0;
16091 +		if ((*start & PFN_4G_MASK) == 0)
16094 +		if ((*end & PFN_4G_MASK) == 0)
16130  	return 0;
16193  		align = size >= SZ_2M ? SZ_2M >> PAGE_SHIFT : 0;
16201  					 size >> PAGE_SHIFT, align, color, 0);
16227  	job_write(pfdev, JS_HEAD_NEXT_LO(js), jc_head & 0xFFFFFFFF);
16290  	if (as_nr < 0)
16291  		return 0;
16305 -	mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
16306 +	mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0UL, AS_COMMAND_FLUSH_MEM);
16308  	mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), transtab & 0xffffffffUL);
16314 -	mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0ULL, AS_COMMAND_FLUSH_MEM);
16315 +	mmu_hw_do_operation_locked(pfdev, as_nr, 0, ~0UL, AS_COMMAND_FLUSH_MEM);
16317  	mmu_write(pfdev, AS_TRANSTAB_LO(as_nr), 0);
16318  	mmu_write(pfdev, AS_TRANSTAB_HI(as_nr), 0);
16326  	if (mmu->as < 0)
16363 +		.ias		= FIELD_GET(0xff, pfdev->features.mmu_features),
16364 +		.oas		= FIELD_GET(0xff00, pfdev->features.mmu_features),
16375 +	return 0;
16384 +	if (mmu->as >= 0) {
16441 -	if (mmu->as >= 0) {
16482 -		if ((*start & PFN_4G_MASK) == 0)
16485 -		if ((*end & PFN_4G_MASK) == 0)
16516 -		.ias		= FIELD_GET(0xff, pfdev->features.mmu_features),
16517 -		.oas		= FIELD_GET(0xff00, pfdev->features.mmu_features),
16558  #define AS_FAULTSTATUS_ACCESS_TYPE_READ		(0x2 << 8)
16559  #define AS_FAULTSTATUS_ACCESS_TYPE_WRITE	(0x3 << 8)
16596 +	  debug node: /d/dri/0/ff900000.vop/vop_dump/dump
16597 +	  cat /d/dri/0/ff900000.vop/vop_dump/dump get more help
16699  # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
16748 -#define RK3288_GRF_SOC_CON6		0x25c
16750 -#define RK3399_GRF_SOC_CON20		0x6250
16834 +		return 0;
16862 +	rockchip_grf_field_write(dp->grf, &dp->data->spdif_sel, 0);
16863 +	rockchip_grf_field_write(dp->grf, &dp->data->i2s_sel, 0);
16918  	return 0;
16926 -	if (ret < 0) {
16932  	if (ret < 0) {
16948 -	return 0;
16949 +	return rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 0);
16954  	return 0;
16993 +					DRM_BRIDGE_ATTACH_NO_CONNECTOR : 0);
17007 +	return 0;
17032  	if (ret < 0)
17043 -	if (ret < 0) {
17050  	if (ret != 0)
17066 +		s->bus_format = di->bus_formats[0];
17079 +		s->output_flags |= dp->id ? ROCKCHIP_OUTPUT_DATA_SWAP : 0;
17090  	return 0;
17135  	return 0;
17146  	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
17192  	return 0;
17222 -	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, NULL);
17223 -	if (ret < 0)
17224 +	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge);
17225 +	if (ret < 0 && ret != -ENODEV)
17233 +	if (id < 0)
17234 +		id = 0;
17236 +	i = 0;
17264  	if (ret < 0)
17285  	return 0;
17314 +		return 0;
17324 +		return 0;
17341 -	.lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
17347 +		.lcdc_sel = GRF_REG_FIELD(0x6250, 5, 5),
17355 -	.lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
17361 +		.lcdc_sel = GRF_REG_FIELD(0x025c, 5, 5),
17390 -	if (dptx > 0) {
17398 -		lanes = 0;
17411  	u8 sink_count = 0;
17413  	if (dp->active_port < 0 || dp->active_port >= dp->ports) {
17468 +	ret = cdn_dp_set_host_cap(dp, port->lanes, 0);
17477 +		schedule_delayed_work(&dp->event_work, 0);
17487  	return 0;
17530  	if (ret < 0)
17544  	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
17551 -	for (i = 0; i < dp->ports; i++) {
17572 +	schedule_delayed_work(&dp->event_work, 0);
17574  	return 0;
17598 +		schedule_delayed_work(&dp->event_work, 0);
17601  	return 0;
17613  	for (i = 0; i < dp_data->max_phy; i++) {
17684  #define DW_MIPI_NEEDS_PHY_CFG_CLK	BIT(0)
17688  #define PX30_GRF_PD_VO_CON1		0x0438
17689  #define PX30_DSI_FORCETXSTOPMODE	(0xf << 7)
17694 +#define RK3568_GRF_VO_CON2		0x0368
17695 +#define RK3568_GRF_VO_CON3		0x036c
17696 +#define RK3568_DSI_FORCETXSTOPMODE	(0xf << 4)
17697 +#define RK3568_DSI_TURNDISABLE		(0x1 << 2)
17698 +#define RK3568_DSI_FORCERXMODE		(0x1 << 0)
17805  		return 0;
17844 +	return 0;
17886  	unsigned long best_freq = 0;
17899  	if (bpp < 0) {
17951  		return 0;
18009 +	.clk_lp2hs = 0x40,
18010 +	.clk_hs2lp = 0x40,
18011 +	.data_lp2hs = 0x10,
18012 +	.data_hs2lp = 0x14,
18021 -	for (i = 0; i < ARRAY_SIZE(hstt_table); i++)
18031  	return 0;
18050 +	if (mux < 0)
18089 +		s->bus_format = info->bus_formats[0];
18122 +		s->dsc_sink_cap.native_420 = 0;
18127  	return 0;
18137 -	if (mux < 0)
18218 -	local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0);
18229 +	node = of_parse_phandle(dsi->dev->of_node, "rockchip,dual-channel", 0);
18247 -		remote = of_graph_get_remote_node(node, 1, 0);
18339 +	return 0;
18373 -			return 0;
18384 +		return 0;
18417 +	ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0,
18431  	return 0;
18486 +	if (dsi->devcnt == 0)
18491  	return 0;
18503 +	return 0;
18515 +	return 0;
18525  		.reg = 0xff450000,
18543  		.reg = 0xff964000,
18561  		.reg = 0xff968000,
18574 +		.reg = 0xfe060000,
18577 +		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI_TURNDISABLE |
18587 +		.reg = 0xfe070000,
18590 +		.lanecfg1 = HIWORD_UPDATE(0, RK3568_DSI_TURNDISABLE |
18652  #define RK3228_GRF_SOC_CON2		0x0408
18657  #define RK3288_GRF_SOC_CON6		0x025C
18659 -#define RK3328_GRF_SOC_CON2		0x0408
18660 +#define RK3288_GRF_SOC_CON16		0x03a8
18664 +#define RK3328_GRF_SOC_CON2		0x0408
18669  #define RK3399_GRF_SOC_CON20		0x6250
18673 +#define RK3568_GRF_VO_CON1		0x0364
18677 +#define RK3588_GRF_SOC_CON2		0x0308
18682 +#define RK3588_GRF_SOC_CON7		0x031c
18683 +#define RK3588_SET_HPD_PATH_MASK	(0x3 << 12)
18684 +#define RK3588_GRF_SOC_STATUS1		0x0384
18690 +#define RK3588_HDMI0_INTR_CHANGE_CNT	(0x7 << 13)
18696 +#define RK3588_HDMI1_INTR_CHANGE_CNT	(0x7 << 21)
18698 +#define RK3588_GRF_VO1_CON3		0x000c
18699 +#define RK3588_COLOR_FORMAT_MASK	0xf
18700 +#define RK3588_YUV444			0x2
18701 +#define RK3588_YUV420			0x3
18702 +#define RK3588_COMPRESSED_DATA		0xb
18703 +#define RK3588_COLOR_DEPTH_MASK		(0xf << 4)
18704 +#define RK3588_8BPC			(0x5 << 4)
18705 +#define RK3588_10BPC			(0x6 << 4)
18713 +#define RK3588_GRF_VO1_CON4		0x0010
18714 +#define RK3588_HDMI21_MASK		BIT(0)
18715 +#define RK3588_GRF_VO1_CON9		0x0024
18720 +#define RK3588_GRF_VO1_CON6		0x0018
18721 +#define RK3588_GRF_VO1_CON7		0x001c
18851 +	{ .tmds = 0,         .n_32k = 0,    .n_44k1 = 0,    .n_48k = 0, },
18857 -			{ 0x00b3, 0x0000},
18858 -			{ 0x2153, 0x0000},
18859 -			{ 0x40f3, 0x0000}
18863 -			{ 0x00b3, 0x0000},
18864 -			{ 0x2153, 0x0000},
18865 -			{ 0x40f3, 0x0000}
18869 -			{ 0x00b3, 0x0000},
18870 -			{ 0x2153, 0x0000},
18871 -			{ 0x40f3, 0x0000}
18875 -			{ 0x0072, 0x0001},
18876 -			{ 0x2142, 0x0001},
18877 -			{ 0x40a2, 0x0001},
18881 -			{ 0x0072, 0x0001},
18882 -			{ 0x2142, 0x0001},
18883 -			{ 0x40a2, 0x0001},
18887 -			{ 0x013e, 0x0003},
18888 -			{ 0x217e, 0x0002},
18889 -			{ 0x4061, 0x0002}
18893 -			{ 0x0072, 0x0001},
18894 -			{ 0x2145, 0x0002},
18895 -			{ 0x4061, 0x0002}
18899 -			{ 0x0072, 0x0001},
18903 -			{ 0x0051, 0x0002},
18904 -			{ 0x2145, 0x0002},
18905 -			{ 0x4061, 0x0002}
18909 -			{ 0x0051, 0x0002},
18910 -			{ 0x2145, 0x0002},
18911 -			{ 0x4061, 0x0002}
18915 -			{ 0x0051, 0x0002},
18916 -			{ 0x2145, 0x0002},
18917 -			{ 0x4061, 0x0002}
18921 -			{ 0x0051, 0x0003},
18922 -			{ 0x214c, 0x0003},
18923 -			{ 0x4064, 0x0003}
18927 +			{ 0x00b3, 0x0000 },
18928 +			{ 0x2153, 0x0000 },
18929 +			{ 0x40f3, 0x0000 },
18933 +			{ 0x00b3, 0x0000 },
18934 +			{ 0x2153, 0x0000 },
18935 +			{ 0x40a2, 0x0001 },
18939 +			{ 0x00b3, 0x0000 },
18940 +			{ 0x2142, 0x0001 },
18941 +			{ 0x40a2, 0x0001 },
18945 +			{ 0x0072, 0x0001 },
18946 +			{ 0x2142, 0x0001 },
18947 +			{ 0x40a2, 0x0001 },
18951 +			{ 0x0072, 0x0001 },
18952 +			{ 0x2142, 0x0001 },
18953 +			{ 0x4061, 0x0002 },
18957 +			{ 0x0072, 0x0001 },
18958 +			{ 0x2145, 0x0002 },
18959 +			{ 0x4061, 0x0002 },
18963 +			{ 0x0051, 0x0002 },
18964 +			{ 0x2145, 0x0002 },
18965 +			{ 0x4061, 0x0002 },
18969 +			{ 0x0051, 0x0002 },
18970 +			{ 0x2145, 0x0002 },
18971 +			{ 0x4064, 0x0003 },
18975 +			{ 0x0051, 0x0002 },
18976 +			{ 0x214c, 0x0003 },
18977 +			{ 0x4064, 0x0003 },
18981 +			{ 0x0040, 0x0003 },
18982 +			{ 0x214c, 0x0003 },
18983 +			{ 0x4064, 0x0003 },
18987 +			{ 0x0040, 0x0003 },
18988 +			{ 0x214c, 0x0003 },
18989 +			{ 0x5a64, 0x0003 },
18993 +			{ 0x0040, 0x0003 },
18994 +			{ 0x3b4c, 0x0003 },
18995 +			{ 0x5a64, 0x0003 },
18999 +			{ 0x1a40, 0x0003 },
19000 +			{ 0x3b4c, 0x0003 },
19001 +			{ 0x5a64, 0x0003 },
19004 +		~0UL, {
19005 +			{ 0x0000, 0x0000 },
19006 +			{ 0x0000, 0x0000 },
19007 +			{ 0x0000, 0x0000 },
19015 +			{ 0x00b7, 0x0000 },
19016 +			{ 0x2157, 0x0000 },
19017 +			{ 0x40f7, 0x0000 },
19021 +			{ 0x00b7, 0x0000 },
19022 +			{ 0x2143, 0x0001 },
19023 +			{ 0x40a3, 0x0001 },
19027 +			{ 0x0073, 0x0001 },
19028 +			{ 0x2146, 0x0002 },
19029 +			{ 0x4062, 0x0002 },
19033 +			{ 0x0052, 0x0003 },
19034 +			{ 0x214d, 0x0003 },
19035 +			{ 0x4065, 0x0003 },
19039 +			{ 0x0041, 0x0003 },
19040 +			{ 0x3b4d, 0x0003 },
19041 +			{ 0x5a65, 0x0003 },
19044 +		~0UL, {
19045 +			{ 0x0000, 0x0000 },
19046 +			{ 0x0000, 0x0000 },
19047 +			{ 0x0000, 0x0000 },
19055 +			{ 0x00b7, 0x0000 },
19056 +			{ 0x2157, 0x0000 },
19057 +			{ 0x40f7, 0x0000 },
19061 +			{ 0x00b7, 0x0000 },
19062 +			{ 0x2143, 0x0001 },
19063 +			{ 0x40a3, 0x0001 },
19067 +			{ 0x0073, 0x0001 },
19068 +			{ 0x2146, 0x0002 },
19069 +			{ 0x4062, 0x0002 },
19073 +			{ 0x0052, 0x0003 },
19074 +			{ 0x214d, 0x0003 },
19075 +			{ 0x4065, 0x0003 },
19079 +			{ 0x0040, 0x0003 },
19080 +			{ 0x3b4c, 0x0003 },
19081 +			{ 0x5a65, 0x0003 },
19084  		~0UL, {
19085 -			{ 0x00a0, 0x000a },
19086 -			{ 0x2001, 0x000f },
19087 -			{ 0x4002, 0x000f },
19088 +			{ 0x0000, 0x0000 },
19089 +			{ 0x0000, 0x0000 },
19090 +			{ 0x0000, 0x0000 },
19098 -		40000000,  { 0x0018, 0x0018, 0x0018 },
19100 -		65000000,  { 0x0028, 0x0028, 0x0028 },
19102 -		66000000,  { 0x0038, 0x0038, 0x0038 },
19104 -		74250000,  { 0x0028, 0x0038, 0x0038 },
19106 -		83500000,  { 0x0028, 0x0038, 0x0038 },
19108 -		146250000, { 0x0038, 0x0038, 0x0038 },
19110 -		148500000, { 0x0000, 0x0038, 0x0038 },
19112 +		600000000, { 0x0000, 0x0000, 0x0000 },
19114  		~0UL,      { 0x0000, 0x0000, 0x0000},
19121  	{ 74250000,  0x8009, 0x0004, 0x0272},
19122 -	{ 148500000, 0x802b, 0x0004, 0x028d},
19123 +	{ 165000000, 0x802b, 0x0004, 0x0209},
19124  	{ 297000000, 0x8039, 0x0005, 0x028d},
19125 -	{ ~0UL,	     0x0000, 0x0000, 0x0000}
19126 +	{ 594000000, 0x8039, 0x0000, 0x019d},
19127 +	{ ~0UL,	     0x0000, 0x0000, 0x0000},
19128 +	{ ~0UL,      0x0000, 0x0000, 0x0000},
19133 +	ROW_INDEX_6BPP = 0,
19142 +	COLUMN_INDEX_8BPC = 0,
19174 +			0x12, 0x00, 0x00, 0x8d, 0x30, 0xc0, 0x10, 0xe0,
19175 +			0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0xa0,
19176 +			0x01, 0x55, 0x03, 0x90, 0x00, 0x0a, 0x05, 0xc9,
19177 +			0x00, 0xa0, 0x00, 0x0f, 0x01, 0x44, 0x01, 0xaa,
19178 +			0x08, 0x00, 0x10, 0xf4, 0x03, 0x0c, 0x20, 0x00,
19179 +			0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38,
19180 +			0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b,
19181 +			0x7d, 0x7e, 0x00, 0x82, 0x00, 0xc0, 0x09, 0x00,
19182 +			0x09, 0x7e, 0x19, 0xbc, 0x19, 0xba, 0x19, 0xf8,
19183 +			0x1a, 0x38, 0x1a, 0x38, 0x1a, 0x76, 0x2a, 0x76,
19184 +			0x2a, 0x76, 0x2a, 0x74, 0x3a, 0xb4, 0x52, 0xf4,
19185 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19186 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19187 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19188 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19189 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
19196 +			0x12, 0x00, 0x00, 0x8d, 0x30, 0xb0, 0x10, 0xe0,
19197 +			0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0x28,
19198 +			0x01, 0x74, 0x03, 0x40, 0x00, 0x0f, 0x06, 0xe0,
19199 +			0x00, 0x2d, 0x00, 0x0f, 0x01, 0x44, 0x01, 0x33,
19200 +			0x0f, 0x00, 0x10, 0xf4, 0x03, 0x0c, 0x20, 0x00,
19201 +			0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38,
19202 +			0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b,
19203 +			0x7d, 0x7e, 0x00, 0x82, 0x01, 0x00, 0x09, 0x40,
19204 +			0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8,
19205 +			0x1a, 0x38, 0x1a, 0x38, 0x1a, 0x76, 0x2a, 0x76,
19206 +			0x2a, 0x76, 0x2a, 0xb4, 0x3a, 0xb4, 0x52, 0xf4,
19207 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19208 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19209 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19210 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19211 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
19218 +			0x12, 0x00, 0x00, 0x8d, 0x30, 0xa0, 0x10, 0xe0,
19219 +			0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0xb0,
19220 +			0x01, 0x9a, 0x02, 0xe0, 0x00, 0x19, 0x09, 0xb0,
19221 +			0x00, 0x12, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xbb,
19222 +			0x16, 0x00, 0x10, 0xec, 0x03, 0x0c, 0x20, 0x00,
19223 +			0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38,
19224 +			0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b,
19225 +			0x7d, 0x7e, 0x00, 0xc2, 0x01, 0x00, 0x09, 0x40,
19226 +			0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8,
19227 +			0x1a, 0x38, 0x1a, 0x78, 0x1a, 0x76, 0x2a, 0xb6,
19228 +			0x2a, 0xb6, 0x2a, 0xf4, 0x3a, 0xf4, 0x5b, 0x34,
19229 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19230 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19231 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19232 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19233 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
19240 +			0x12, 0x00, 0x00, 0x8d, 0x30, 0x90, 0x10, 0xe0,
19241 +			0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0x38,
19242 +			0x01, 0xc7, 0x03, 0x16, 0x00, 0x1c, 0x08, 0xc7,
19243 +			0x00, 0x10, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xaa,
19244 +			0x17, 0x00, 0x10, 0xf1, 0x03, 0x0c, 0x20, 0x00,
19245 +			0x06, 0x0b, 0x0b, 0x33, 0x0e, 0x1c, 0x2a, 0x38,
19246 +			0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b,
19247 +			0x7d, 0x7e, 0x00, 0xc2, 0x01, 0x00, 0x09, 0x40,
19248 +			0x09, 0xbe, 0x19, 0xfc, 0x19, 0xfa, 0x19, 0xf8,
19249 +			0x1a, 0x38, 0x1a, 0x78, 0x1a, 0x76, 0x2a, 0xb6,
19250 +			0x2a, 0xb6, 0x2a, 0xf4, 0x3a, 0xf4, 0x63, 0x74,
19251 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19252 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19253 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19254 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19255 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
19262 +			0x12, 0x00, 0x00, 0xad, 0x30, 0xc0, 0x10, 0xe0,
19263 +			0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0xa0,
19264 +			0x01, 0x55, 0x03, 0x90, 0x00, 0x0a, 0x05, 0xc9,
19265 +			0x00, 0xa0, 0x00, 0x0f, 0x01, 0x44, 0x01, 0xaa,
19266 +			0x08, 0x00, 0x10, 0xf4, 0x07, 0x10, 0x20, 0x00,
19267 +			0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38,
19268 +			0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b,
19269 +			0x7d, 0x7e, 0x01, 0x02, 0x11, 0x80, 0x22, 0x00,
19270 +			0x22, 0x7e, 0x32, 0xbc, 0x32, 0xba, 0x3a, 0xf8,
19271 +			0x3b, 0x38, 0x3b, 0x38, 0x3b, 0x76, 0x4b, 0x76,
19272 +			0x4b, 0x76, 0x4b, 0x74, 0x5b, 0xb4, 0x73, 0xf4,
19273 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19274 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19275 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19276 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19277 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
19284 +			0x12, 0x00, 0x00, 0xad, 0x30, 0xb0, 0x10, 0xe0,
19285 +			0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x05, 0x28,
19286 +			0x01, 0x74, 0x03, 0x40, 0x00, 0x0f, 0x06, 0xe0,
19287 +			0x00, 0x2d, 0x00, 0x0f, 0x01, 0x44, 0x01, 0x33,
19288 +			0x0f, 0x00, 0x10, 0xf4, 0x07, 0x10, 0x20, 0x00,
19289 +			0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38,
19290 +			0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b,
19291 +			0x7d, 0x7e, 0x01, 0x42, 0x19, 0xc0, 0x2a, 0x40,
19292 +			0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8,
19293 +			0x3b, 0x38, 0x3b, 0x38, 0x3b, 0x76, 0x4b, 0x76,
19294 +			0x4b, 0x76, 0x4b, 0xb4, 0x5b, 0xb4, 0x73, 0xf4,
19295 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19296 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19297 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19298 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19299 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
19306 +			0x12, 0x00, 0x00, 0xad, 0x30, 0xa0, 0x10, 0xe0,
19307 +			0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0xb0,
19308 +			0x01, 0x9a, 0x02, 0xe0, 0x00, 0x19, 0x09, 0xb0,
19309 +			0x00, 0x12, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xbb,
19310 +			0x16, 0x00, 0x10, 0xec, 0x07, 0x10, 0x20, 0x00,
19311 +			0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38,
19312 +			0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b,
19313 +			0x7d, 0x7e, 0x01, 0xc2, 0x22, 0x00, 0x2a, 0x40,
19314 +			0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8,
19315 +			0x3b, 0x38, 0x3b, 0x78, 0x3b, 0x76, 0x4b, 0xb6,
19316 +			0x4b, 0xb6, 0x4b, 0xf4, 0x63, 0xf4, 0x7c, 0x34,
19317 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19318 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19319 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19320 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19321 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
19328 +			0x12, 0x00, 0x00, 0xad, 0x30, 0x90, 0x10, 0xe0,
19329 +			0x1e, 0x00, 0x00, 0x60, 0x03, 0xc0, 0x04, 0x38,
19330 +			0x01, 0xc7, 0x03, 0x16, 0x00, 0x1c, 0x08, 0xc7,
19331 +			0x00, 0x10, 0x00, 0x0f, 0x01, 0x44, 0x00, 0xaa,
19332 +			0x17, 0x00, 0x10, 0xf1, 0x07, 0x10, 0x20, 0x00,
19333 +			0x06, 0x0f, 0x0f, 0x33, 0x0e, 0x1c, 0x2a, 0x38,
19334 +			0x46, 0x54, 0x62, 0x69, 0x70, 0x77, 0x79, 0x7b,
19335 +			0x7d, 0x7e, 0x01, 0xc2, 0x22, 0x00, 0x2a, 0x40,
19336 +			0x2a, 0xbe, 0x3a, 0xfc, 0x3a, 0xfa, 0x3a, 0xf8,
19337 +			0x3b, 0x38, 0x3b, 0x78, 0x3b, 0x76, 0x4b, 0xb6,
19338 +			0x4b, 0xb6, 0x4b, 0xf4, 0x63, 0xf4, 0x84, 0x74,
19339 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19340 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19341 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19342 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
19343 +			0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
19451 +		return 0;
19564 +		if (vactive % slice_height == 0)
19567 +	return 0;
19596 +		return 0;
19600 +	 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
19656 +			return 0;
19751 +	return 0;
19759 +	int fractional_bpp = 0;
19774 +	for (i = 0; i < PPS_TABLE_LEN; i++)
19793 +	return 0;
19846 +	s->dsc_sink_cap.native_420 = 0;
19863 +	for (i = 0; i < phy_table_size; i++) {
19864 +		if (config[i * 4] != 0)
19867 +			rockchip_phy_config[i].mpixelclock = ~0UL;
19873 +	return 0;
19953 +		      HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK);
19957 +		      HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK);
20109 +	return 0;
20237 +	if (hdmi->chip_data->lcdsel_grf_reg < 0)
20247 +	if (ret < 0) {
20253 +	if (ret != 0)
20265 +			val = HIWORD_UPDATE(0, mode_mask);
20286 +		val = HIWORD_UPDATE(0, RK3588_HDMI21_MASK);
20292 +		val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK);
20315 +		val = HIWORD_UPDATE(0, RK3588_COMPRESS_MODE_MASK | RK3588_COLOR_FORMAT_MASK);
20326 +	u32 val = 0;
20331 +		val = HIWORD_UPDATE(0, RK3588_COLOR_FORMAT_MASK);
20522 +	/* XXX: max_tmds_clock of some sink is 0, we think it is 340MHz. */
20649 +			gpiod_set_value(hdmi->enable_gpio, 0);
20712 +	return 0;
20780 +	hdmi->color_changed = 0;
20855 +		if (ret < 0)
20862 +	return 0;
20866 +	{ 0, "Automatic" }, /* Prefer highest color depth */
20888 +	{ 0, "auto" },
20894 +	{ 0, "DVI" },
20956 +		prop = drm_property_create_enum(connector->dev, 0,
20962 +			drm_object_attach_property(&connector->base, prop, 0);
20966 +	prop = drm_property_create_enum(connector->dev, 0, RK_IF_PROP_COLOR_FORMAT,
20971 +		drm_object_attach_property(&connector->base, prop, 0);
20974 +	prop = drm_property_create_range(connector->dev, 0,
20976 +					 0, 0xff);
20979 +		drm_object_attach_property(&connector->base, prop, 0);
20982 +	prop = drm_property_create_range(connector->dev, 0,
20984 +					 0, 0xf);
20987 +		drm_object_attach_property(&connector->base, prop, 0);
20993 +				   "HDR_PANEL_METADATA", 0);
20996 +		drm_object_attach_property(&connector->base, prop, 0);
21002 +				   "NEXT_HDR_SINK_DATA", 0);
21005 +		drm_object_attach_property(&connector->base, prop, 0);
21013 +					   hdmi->user_split_mode ? 1 : 0);
21017 +		prop = drm_property_create_enum(connector->dev, 0,
21023 +			drm_object_attach_property(&connector->base, prop, 0);
21026 +		prop = drm_property_create_enum(connector->dev, 0,
21032 +			drm_object_attach_property(&connector->base, prop, 0);
21035 +		prop = drm_property_create_enum(connector->dev, 0,
21041 +			drm_object_attach_property(&connector->base, prop, 0);
21046 +	if (version >= 0x211a || hdmi->is_hdmi_qp)
21047 +		drm_object_attach_property(&connector->base, prop, 0);
21051 +					   connector->colorspace_property, 0);
21115 -	return 0;
21139 -	for (i = 0; mpll_cfg[i].mpixelclock != (~0UL); i++) {
21151 +			return 0;
21154 +		return 0;
21158 +			return 0;
21161 +		return 0;
21168 +		return 0;
21170 +		return 0;
21176 +		return 0;
21178 +		return 0;
21180 +		return 0;
21182 +		return 0;
21214 +		return 0;
21217 +		return 0;
21222 +			return 0;
21235 +		return 0;
21245 +		return 0;
21248 +		return 0;
21251 +			state->hdr_output_metadata->base.id : 0;
21252 +		return 0;
21255 +		return 0;
21258 +		return 0;
21261 +		return 0;
21294 -	if (hdmi->chip_data->lcdsel_grf_reg < 0)
21306 -	if (ret < 0) {
21314 -	if (ret != 0)
21331 +		s->dsc_enable = 0;
21340 -	return 0;
21362 +	while (hdmi->phy->power_count > 0)
21390 +	while (hdmi->phy->power_count > 0)
21442 +		      HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK);
21446 +		      HIWORD_UPDATE(0, RK3588_HDMI1_HPD_INT_MSK);
21685 -	if (encoder->possible_crtcs == 0)
21703 +		if (encoder->possible_crtcs == 0)
21834 +		if (hdmi->hpd_irq < 0)
21967 +	if (id < 0)
21968 +		id = 0;
22012 +	return 0;
22025  	return 0;
22073  	return 0;
22116 index 0f3eb392f..9d7c160b6 100644
22157  #define DRIVER_MINOR	0
22180 +	int pipe, ret = 0;
22185 +	if (mstimeout <= 0)
22262 +	if (info->cpp[0])
22263 +		return info->cpp[0] * 8;
22277 +	return 0;
22297 +	uint32_t possible_crtcs = 0;
22306 +			return 0;
22386 +		   1430, 1650, 0, 720, 725, 730, 750, 0,
22391 +		   2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
22396 +		   2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
22401 +		   1760, 1980, 0, 720, 725, 730, 750, 0,
22404 +	/* 0x10 - 1024x768@60Hz */
22406 +		   1184, 1344, 0,  768, 771, 777, 806, 0,
22410 +		   796, 864, 0, 576, 581, 586, 625, 0,
22415 +		   798, 858, 0, 480, 489, 495, 525, 0,
22424 +	int i, count, num_modes = 0;
22429 +	for (i = 0; i < count; i++) {
22449 +	return db[0] >> 5;
22455 +	return db[0] & 0x1f;
22463 +#define HDMI_NEXT_HDR_VSDB_OUI 0xd04601
22469 +	if (cea_db_tag(db) != 0x07)
22484 +	if (cea_db_tag(db) != 0x03)
22515 +	if (cea[0] == 0x81) {
22522 +	} else if (cea[0] == 0x02) {
22526 +		if (*end == 0)
22534 +	return 0;
22544 +	if (edid == NULL || edid->extensions == 0)
22550 +		if (edid_ext[0] == ext_id)
22565 +	u8 csum = 0;
22570 +	DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n",
22578 +	for (i = 0; i < dispid_length; i++)
22585 +	return 0;
22592 +	u8 *displayid = find_edid_extension(edid, 0x70, ext_index);
22623 +	ext_index = 0;
22624 +	cea = find_edid_extension(edid, 0x02, &ext_index);
22629 +	ext_index = 0;
22638 +			if (block->tag == 0x81)
22666 +	return 0;
22698 +	case 0:
22700 +		*max_lanes = 0;
22701 +		*max_rate_per_lane = 0;
22705 +#define EDID_DSC_10BPC			(1 << 0)
22711 +#define EDID_DSC_MAX_FRL_RATE_MASK	0xf0
22712 +#define EDID_DSC_MAX_SLICES		0xf
22713 +#define EDID_DSC_TOTAL_CHUNK_KBYTES	0x3f
22714 +#define EDID_MAX_FRL_RATE_MASK		0xf0
22751 +		dsc_cap->bpc_supported = 0;
22788 +	case 0:
22790 +		dsc_cap->max_slices = 0;
22791 +		dsc_cap->clk_per_slice = 0;
22806 +	ver = (next_hdr_db[5] & 0xf0) << 8 | next_hdr_db[0];
22809 +	case 0x00f9:
22811 +	case 0x20ee:
22813 +	case 0x20eb:
22815 +	case 0x40eb:
22824 +	hdr->yuv422_12bit = data[5] & BIT(0);
22828 +	hdr->dm_major_ver = (data[21] & 0xf0) >> 4;
22829 +	hdr->dm_minor_ver = data[21] & 0xf;
22831 +	hdr->t_min_pq = (data[19] << 4) | ((data[18] & 0xf0) >> 4);
22832 +	hdr->t_max_pq = (data[20] << 4) | (data[18] & 0xf);
22834 +	hdr->rx = (data[7] << 4) | ((data[6] & 0xf0) >> 4);
22835 +	hdr->ry = (data[8] << 4) | (data[6] & 0xf);
22836 +	hdr->gx = (data[10] << 4) | ((data[9] & 0xf0) >> 4);
22837 +	hdr->gy = (data[11] << 4) | (data[9] & 0xf);
22838 +	hdr->bx = (data[13] << 4) | ((data[12] & 0xf0) >> 4);
22839 +	hdr->by = (data[14] << 4) | (data[12] & 0xf);
22840 +	hdr->wx = (data[16] << 4) | ((data[15] & 0xf0) >> 4);
22841 +	hdr->wy = (data[17] << 4) | (data[15] & 0xf);
22846 +	hdr->yuv422_12bit = data[5] & BIT(0);
22848 +	hdr->global_dimming = data[6] & BIT(0);
22850 +	hdr->dm_version = (data[5] & 0x1c) >> 2;
22852 +	hdr->colorimetry = data[7] & BIT(0);
22854 +	hdr->t_max_lum = (data[6] & 0xfe) >> 1;
22855 +	hdr->t_min_lum = (data[7] & 0xfe) >> 1;
22867 +	hdr->yuv422_12bit = data[5] & BIT(0);
22869 +	hdr->global_dimming = data[6] & BIT(0);
22871 +	hdr->dm_version = (data[5] & 0x1c) >> 2;
22873 +	hdr->colorimetry = data[7] & BIT(0);
22875 +	hdr->t_max_lum = (data[6] & 0xfe) >> 1;
22876 +	hdr->t_min_lum = (data[7] & 0xfe) >> 1;
22878 +	hdr->low_latency = data[8] & 0x3;
22880 +	hdr->unique_rx = (data[11] & 0xf8) >> 3;
22881 +	hdr->unique_ry = (data[11] & 0x7) << 2 | (data[10] & BIT(0)) << 1 |
22882 +		(data[9] & BIT(0));
22883 +	hdr->unique_gx = (data[9] & 0xfe) >> 1;
22884 +	hdr->unique_gy = (data[10] & 0xfe) >> 1;
22885 +	hdr->unique_bx = (data[8] & 0xe0) >> 5;
22886 +	hdr->unique_by = (data[8] & 0x1c) >> 2;
22891 +	hdr->yuv422_12bit = data[5] & BIT(0);
22895 +	hdr->dm_version = (data[5] & 0x1c) >> 2;
22896 +	hdr->backlt_min_luma = data[6] & 0x3;
22897 +	hdr->interface = data[7] & 0x3;
22898 +	hdr->yuv444_10b_12b = (data[8] & BIT(0)) << 1 | (data[9] & BIT(0));
22900 +	hdr->t_min_pq_v2 = (data[6] & 0xf8) >> 3;
22901 +	hdr->t_max_pq_v2 = (data[7] & 0xf8) >> 3;
22903 +	hdr->unique_rx = (data[10] & 0xf8) >> 3;
22904 +	hdr->unique_ry = (data[11] & 0xf8) >> 3;
22905 +	hdr->unique_gx = (data[8] & 0xfe) >> 1;
22906 +	hdr->unique_gy = (data[9] & 0xfe) >> 1;
22907 +	hdr->unique_bx = data[10] & 0x7;
22908 +	hdr->unique_by = data[11] & 0x7;
22918 +	if (version < 0)
22966 +	return 0;
22979 +	memset(sink_data, 0, sizeof(struct next_hdr_sink_data));
22995 +	return 0;
23028 +	return 0;
23050 +	DRM_ERROR("iommu fault handler flags: 0x%x\n", flags);
23063 +	return 0;
23076  	return 0;
23093 +		return 0;
23098 +	return 0;
23117 +	return 0;
23121 +	{ "summary", rockchip_drm_summary_show, 0, NULL },
23122 +	{ "mm_dump", rockchip_drm_mm_dump, 0, NULL },
23151 +					 "EOTF", 0, 5);
23157 +					 "COLOR_SPACE", 0, 12);
23163 +					 "ASYNC_COMMIT", 0, 1);
23169 +					 "SHARE_ID", 0, UINT_MAX);
23175 +					 "CONNECTOR_ID", 0, 0xf);
23190 +	private->aclk_prop = drm_property_create_range(dev, 0, "ACLK", 0, UINT_MAX);
23191 +	private->bg_prop = drm_property_create_range(dev, 0, "BACKGROUND", 0, UINT_MAX);
23192 +	private->line_flag_prop = drm_property_create_range(dev, 0, "LINE_FLAG1", 0, UINT_MAX);
23194 +	return drm_mode_create_tv_properties(dev, 0, NULL);
23275 +	node = of_parse_phandle(np, "secure-memory-region", 0);
23279 +	ret = of_address_to_resource(node, 0, &res);
23293 +	return 0;
23386  	ret = drm_dev_register(drm_dev, 0);
23390  	return 0;
23443 +	return 0;
23502 +		pipe = flags & _DRM_VBLANK_SECONDARY ? 1 : 0;
23511 +	return 0;
23695  		iommu = of_parse_phandle(port->parent, "iommus", 0);
23720  	return 0;
23726  	num_rockchip_sub_drivers = 0;
23759  	return 0;
23798 +#define VOP_OUTPUT_IF_RGB	BIT(0)
23813 +#define DRM_FORMAT_NV20		fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
23817 +#define DRM_FORMAT_NV30		fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
23906 +	 * @native_420: Does sink support DSC with 4:2:0 compression
24284 +	int i = 0;
24296 +		for (i = 0; i < 4; i++) {
24325 +	int ret = 0;
24347 +	rockchip_logo_fb->fb.obj[0] = &rockchip_logo_fb->rk_obj.base;
24365 +	vop_bw_info->line_bw_mbyte = 0;
24366 +	vop_bw_info->frame_bw_mbyte = 0;
24367 +	vop_bw_info->plane_num = 0;
24376 +	return 0;
24425  	if (drm_is_afbc(mode_cmd->modifier[0])) {
24452  	dev->mode_config.min_height = 0;
24529  	struct drm_mode_fb_cmd2 mode_cmd = { 0 };
24534  	size = mode_cmd.pitches[0] * mode_cmd.height;
24537 +	rk_obj = rockchip_gem_create_object(dev, size, true, 0);
24593 +static u32 bank_bit_mask = 0x7;
24613  	return 0;
24615  	return 0;
24623 +	for (i = 0; i < PG_ROUND; i++) {
24659 +	int end = 0;
24661 +	unsigned int block_index[PG_ROUND] = {0};
24665 +	for (i = 0; i < PG_ROUND; i++)
24685 +	DRM_DEBUG_KMS("bank_bit_first = 0x%x, bank_bit_mask = 0x%x\n",
24688 +	cur_page = 0;
24700 +			for (i = 0; i < chunk_pages; i++)
24704 +			for (i = 0; i < chunk_pages; i++) {
24724 +	maximum = block_index[0];
24728 +	for (i = 0; i < maximum; i++) {
24729 +		for (j = 0; j < PG_ROUND; j++) {
24764  	return 0;
24792 -	if (ret < 0)
24797 -	if (ret < 0)
24854  	return 0;
24877 +	if (size != 0 && nmemb > SIZE_MAX / size)
24899 +	int ret = 0, i;
24932 +	i = 0;
24946  	return 0;
24974 +	int ret = 0;
24997 +		if (ret < 0)
25014 +		if (ret < 0)
25021 +	return 0;
25180  					  DMA_BIDIRECTIONAL, 0);
25239 +	if (ret < 0) {
25279 +	int ret = 0;
25294 +	args->phy_addr = page_to_phys(rk_obj->pages[0]);
25309 +		return 0;
25313 +	return 0;
25323 +		return 0;
25327 +	return 0;
25337 +	unsigned int len = 0;
25341 +		unsigned int sg_offset, sg_left, size = 0;
25362 +		if (length == 0)
25366 +	return 0;
25378 +		return 0;
25384 +	return 0;
25396 +		return 0;
25402 +	return 0;
25531 -		vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
25533 -		vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
25536 -			    win->base, ~0, v, #name)
25547 -			vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
25548 -	} while (0)
25569 -			vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
25575  	} while (0)
25585 +		REG_SET(x, name, 0, win->ext->name, v, true)
25592 +		REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
25595 +		vop_read_reg(vop, 0, &vop->data->ctrl->name)
25598 +		REG_SET(vop, name, 0, vop->data->intr->name, \
25601 -		vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
25602 +		REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
25607  		    vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
25615 +		vop_read_reg(x, 0, &vop->data->ctrl->name)
25635 -				    0, ~0, v, #name); \
25639  	} while (0)
25645 -#define AFBC_FMT_RGB565		0x0
25646 -#define AFBC_FMT_U8U8U8U8	0x5
25647 -#define AFBC_FMT_U8U8U8		0x4
25664 -	0x4A8, 0x0,    0x662,
25665 -	0x4A8, 0x1E6F, 0x1CBF,
25666 -	0x4A8, 0x812,  0x0,
25667 -	0x321168, 0x0877CF, 0x2EB127
25870 +	u32 val = 0;
25908 -		v = ((v << shift) & 0xffff) | (mask << (shift + 16));
25947 +	for (i = 0; i < 33; i++)
25952 +		   hdr2sdr_eetf_oetf_yn[0]);
25959 +		   table->hdr2sdr_sat_yn[0]);
25979 +	for (i = 0; i < 65; i++) {
25994 +		   sdr2hdr_eotf_oetf_yn[0]);
25999 +	for (i = 0; i < 64; i++) {
26006 +	for (i = 0; i < 63; i++)
26016 +	 * so far the csc offset is not 0 and in the feature the csc offset
26017 +	 * impossible be 0, so when the offset is 0, should return here.
26019 +	if (!table || offset == 0)
26022 +	for (i = 0; i < 8; i++)
26036 +	for (i = 0; i < vop->num_wins; i++) {
26039 +		if (VOP_WIN_GET(vop, win, enable) != 0)
26059 +	VOP_WIN_SET(vop, win, enable, 0);
26060 +	if (win->area_id == 0)
26061 +		VOP_WIN_SET(vop, win, gate, 0);
26068 +	for (i = 0; i < vop->num_wins; i++) {
26247 +	for (i = 0 ; i < plane->modifier_count; i++)
26331 +	int pre_sdr2hdr_state = 0, post_sdr2hdr_state = 0;
26332 +	int pre_sdr2hdr_mode = 0, post_sdr2hdr_mode = 0, sdr2hdr_func = 0;
26334 +	int hdr2sdr_en = 0, plane_id = 0;
26339 +		return 0;
26378 +	plane_id = 0;
26380 +	pre_sdr2hdr_mode = 0;
26381 +	post_sdr2hdr_mode = 0;
26382 +	pre_sdr2hdr_state = 0;
26383 +	post_sdr2hdr_state = 0;
26433 +		s->yuv_overlay = 0;
26435 -	VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
26448 +	return 0;
26480 +					0, 500 * 1000);
26537 +		return 0;
26543 +					return 0;
26569 +			return 0;
26597 +	return 0;
26685 +	return 0;
26724 +	VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
26751 +	int i, dle, lut_idx = 0;
26766 +		VOP_CTRL_SET(vop, dsp_lut_en, 0);
26777 -	VOP_WIN_SET(vop, win, enable, 0);
26779 +	for (i = 0; i < vop->lut_len; i++)
26795 +		 * update_gamma value auto clean to 0 by HW, should not
26798 +		VOP_CTRL_SET(vop, update_gamma_lut, 0);
26813 -	if (ret < 0) {
26821 -	if (WARN_ON(ret < 0))
26823 +	r = red * (lut_len - 1) / 0xffff;
26824 +	g = green * (lut_len - 1) / 0xffff;
26825 +	b = blue * (lut_len - 1) / 0xffff;
26830 -	if (WARN_ON(ret < 0))
26855 -	for (i = 0; i < vop->len; i += 4)
26860 +	*red = r * 0xffff / (lut_len - 1);
26861 +	*green = g * 0xffff / (lut_len - 1);
26862 +	*blue = b * 0xffff / (lut_len - 1);
26875 -		for (i = 0; i < vop->data->win_size; i++) {
26896 -		VOP_AFBC_SET(vop, enable, 0);
26899 +	for (i = 0; i < len; i++)
26904 +	return 0;
26914 +	for (i = 0; i < vop->lut_len; i++)
26919 +	return 0;
26928 +	if (ret < 0) {
26935 +	if (ret < 0) {
26942 +	if (ret < 0) {
26952 +	if (ret < 0) {
26968 +		if (version && version == 0x0a05)
26975 -	return 0;
27001 +	VOP_CTRL_SET(vop, dsp_blank, 0);
27012 +	for (i = 0; i < vop->num_wins; i++) {
27016 -        for (i = 0; i < vop->data->win_size; i++) {
27021 +	VOP_CTRL_SET(vop, afbdc_en, 0);
27062 +	VOP_CTRL_SET(vop, dsp_interlace, 0);
27068 +	VOP_CTRL_SET(vop, afbdc_en, 0);
27131 +	return 0;
27153  		DRM_DEBUG_KMS("Unsupported format modifier 0x%llx\n", modifier);
27182  		return 0;
27205  		return 0;
27208 -	if (ret < 0)
27211 +	if (vop_plane_state->format < 0)
27256 +	offset = (src->x1 >> 16) * fb->format->cpp[0];
27257 +	vop_plane_state->offset = offset + fb->offsets[0];
27259 +		offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
27261 +		offset += (src->y1 >> 16) * fb->pitches[0];
27267 +	obj = fb->obj[0];
27269 +	vop_plane_state->yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
27275 -		if (ret < 0)
27281 …port offset display, xpos=%d, ypos=%d, offset=%d\n", state->src.x1, state->src.y1, fb->offsets[0]);
27296  	return 0;
27324 +		VOP_WIN_SET(vop, win, yrgb_mst, 0);
27378 +	num_pages = 0;
27380 +	obj = fb->obj[0];
27398 -	obj = fb->obj[0];
27404 -	act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
27407 -	dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
27411 -	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
27431 -	offset = (src->x1 >> 16) * fb->format->cpp[0];
27432 -	offset += (src->y1 >> 16) * fb->pitches[0];
27433 -	dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
27434 +	act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
27441 -		dma_addr += (actual_h - 1) * fb->pitches[0];
27443 +	dsp_info |= (dsp_w - 1) & 0xffff;
27448 +	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
27457 -		VOP_AFBC_SET(vop, hreg_block_split, 0);
27465  	VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
27472  		    (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
27475  		    (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
27492 -		for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
27524 -	if (fb->format->has_alpha && win_index > 0) {
27530 +	global_alpha_en = (vop_plane_state->global_alpha == 0xff) ? 0 : 1;
27532 +	    (s->dsp_layer_sel & 0x3) != win->win_id) {
27558 +			    vop_plane_state->blend_mode == DRM_MODE_BLEND_PREMULTI ? 1 : 0);
27562  		VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
27563  		VOP_WIN_SET(vop, win, alpha_en, 0);
27601 +		planlist->dump_info.pitches = fb->pitches[0];
27611 +	    vop->rockchip_crtc.vop_dump_times > 0) {
27669 +	int ret = 0;
27691 +	if (ret != 0)
27731 +	int ret = 0;
27758 +	if (ret != 0)
27805 +	vop_plane_state->global_alpha = 0xff;
27818 -			WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
27864 +		return 0;
27869 +		return 0;
27874 +		return 0;
27879 +		return 0;
27907 +		return 0;
27912 +		return 0;
27917 +		return 0;
27924 +		for (i = 0; i < obj->properties->count; i++) {
27927 +				return 0;
27934 +		return 0;
27983 +	return 0;
27997 +		VOP_INTR_SET_TYPE(vop, enable, FS_FIELD_INTR, 0);
27999 +		VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
28031 +		return 0;
28062 +	return 0;
28071 +		} while (0)
28091 +		return 0;
28112 +	for (i = 0; i < fb->format->num_planes; i++) {
28113 +		obj = fb->obj[0];
28115 +		fb_addr = rk_obj->dma_addr + fb->offsets[0];
28121 +	return 0;
28152 +		return 0;
28171 +	for (i = 0; i < vop->num_wins; i++) {
28184 +	return 0;
28191 +	int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
28197 +	for (i = 0; i < dump_len; i += 16) {
28198 +		DEBUG_PRINT("0x%08x: %08x %08x %08x %08x\n", i,
28211 +		return 0;
28213 +	for (i = 0; i < vop->lut_len; i++) {
28214 +		if (i % 8 == 0)
28216 +		DEBUG_PRINT("0x%08x ", vop->lut[i]);
28220 +	return 0;
28226 +	{ "gamma_lut", vop_gamma_show, 0, NULL },
28250 +	for (i = 0; i < ARRAY_SIZE(vop_debugfs_files); i++)
28256 +	return 0;
28318 +	int bpp = fb->format->cpp[0] << 3;
28326 +	if (src_width <= 0 || src_height <= 0 || dest_width <= 0 ||
28327 +	    dest_height <= 0)
28328 +		return 0;
28346 +	u64 max_bandwidth = 0;
28350 +		u64 bandwidth = 0;
28377 +	u64 line_bw_mbyte = 0;
28378 +	int cnt = 0, plane_num = 0;
28386 +		return 0;
28397 +	    vop->rockchip_crtc.vop_dump_times > 0) {
28428 +		cpp = pstate->fb->format->cpp[0];
28434 +	sort(pbandwidth, cnt, sizeof(pbandwidth[0]), vop_bandwidth_cmp, NULL);
28436 +	vop_bw_info->line_bw_mbyte = vop_calc_max_bandwidth(pbandwidth, 0, cnt, vdisplay);
28482 +		dev_err(vop->dev, "wait mode 0x%x timeout\n", mode);
28506 +			VOP_CTRL_SET(vop, mcu_rs, 0);
28515 +			VOP_CTRL_SET(vop, mcu_bypass, value ? 1 : 0);
28534 +	int ret = 0;
28553 +	if (jiffies_left == 0) {
28626 +		VOP_CTRL_SET(vop, dither_down_en, 0);
28631 +		VOP_CTRL_SET(vop, dither_down_en, 0);
28632 +		VOP_CTRL_SET(vop, pre_dither_down_en, 0);
28640 +		VOP_CTRL_SET(vop, dither_down_en, 0);
28641 +		VOP_CTRL_SET(vop, pre_dither_down_en, 0);
28646 +		     s->output_mode == ROCKCHIP_OUT_MODE_AAAA ? 0 : 1);
28666 +		VOP_CTRL_SET(vop, dsp_data_swap, 0);
28672 +		     s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
28674 +		     s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
28683 +		val = 0;
28686 +		val = 0;
28688 +		val = 0x20010200;
28690 +		val = 0x801080;
28767 +	int for_ddr_freq = 0;
28786 +	VOP_CTRL_SET(vop, standby, 0);
28799 +	dclk_inv = (s->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
28803 +		   0 : BIT(HSYNC_POSITIVE);
28805 +		   0 : BIT(VSYNC_POSITIVE);
28854 +		VOP_CTRL_SET(vop, dp_dclk_pol, 0);
28862 +			VOP_CTRL_SET(vop, tve_sw_mode, 0);
28902 +		VOP_CTRL_SET(vop, dsp_interlace, 0);
28903 +		VOP_CTRL_SET(vop, p2i_en, 0);
28910 +	VOP_INTR_SET(vop, line_flag_num[0], act_end);
28953 +	s->afbdc_en = 0;
29001 +			DRM_ERROR("win[%d] feature:0x%llx, not support afbdc\n",
29017 +			obj = fb->obj[0];
29019 +			fb_addr = rk_obj->dma_addr + fb->offsets[0];
29050 +		if (src->x1 || src->y1 || fb->offsets[0]) {
29054 +				  src->x1, src->y1, fb->offsets[0]);
29065 +	return 0;
29114 +	int dsp_layer_sel = 0;
29115 +	int i, j, cnt = 0, ret = 0;
29121 +	s->yuv_overlay = 0;
29137 +	for (i = 0; i < vop_data->win_size; i++) {
29147 +		for (j = 0; j < vop->num_wins; j++) {
29150 -	return 0;
29184 +	sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
29186 -	VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
29187 +	for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
29254 -	return vop_read_reg(vop, 0, &vop->data->common->dsp_lut_en);
29285 +#define POST_HORIZONTAL_SCALEDOWN_EN(x)		((x) << 0)
29310 -	for (i = 0; i < crtc->gamma_size; i++) {
29325 +		VOP_CTRL_SET(vop, hdr2sdr_en_win0_csc, 0);
29378 -	VOP_REG_SET(vop, common, dsp_lut_en, 0);
29405 +	s->post_r2y_en = 0;
29406 +	s->post_y2r_en = 0;
29407 +	s->bcsh_en = 0;
29445 +		brightness = interpolate(0, -128, 100, 127, s->tv_state->brightness);
29447 +		brightness = interpolate(0, -64, 100, 63, s->tv_state->brightness);
29449 +		brightness = interpolate(0, -32, 100, 31, s->tv_state->brightness);
29457 +		contrast = interpolate(0, 0, 100, 511, s->tv_state->contrast);
29458 +		saturation = interpolate(0, 0, 100, 511, s->tv_state->saturation);
29460 +		 *  a:[-30~0]:
29461 +		 *    sin_hue = 0x100 - sin(a)*256;
29463 +		 *  a:[0~30]
29467 +		hue = interpolate(0, -30, 100, 30, s->tv_state->hue);
29470 +		VOP_CTRL_SET(vop, bcsh_sat_con, saturation * contrast / 0x100);
29480 +		contrast = interpolate(0, 0, 100, 255, s->tv_state->contrast);
29481 +		saturation = interpolate(0, 0, 100, 255, s->tv_state->saturation);
29483 +		 *  a:[-30~0]:
29484 +		 *    sin_hue = 0x100 - sin(a)*128;
29486 +		 *  a:[0~30]
29490 +		hue = interpolate(0, -30, 100, 30, s->tv_state->hue);
29493 +		VOP_CTRL_SET(vop, bcsh_sat_con, saturation * contrast / 0x80);
29501 +	if (VOP_MAJOR(vop->version) == 3 && VOP_MINOR(vop->version) == 0)
29502 +		VOP_CTRL_SET(vop, auto_gate_en, 0);
29557 -		   BIT(HSYNC_POSITIVE) : 0;
29559 -		   BIT(VSYNC_POSITIVE) : 0;
29561 -	VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
29588 -		VOP_REG_SET(vop, output, dp_dclk_pol, 0);
29610 -		VOP_REG_SET(vop, common, pre_dither_down, 0);
29612 +		VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
29615 +		pic_size = (s->afbdc_win_width & 0xffff);
29624 -		VOP_REG_SET(vop, common, dither_down_en, 0);
29626 +		pic_offset = (s->afbdc_win_xoffset & 0xffff);
29646 -	VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
29653 -	VOP_REG_SET(vop, common, standby, 0);
29683 -	int afbc_planes = 0;
29725 +			VOP_CTRL_SET(vop, dma_stop, 0);
29742 -	s->enable_afbc = afbc_planes > 0;
29744 -	return 0;
29776 +			VOP_CTRL_SET(vop, reg_done_frm, 0);
29778 +		VOP_CTRL_SET(vop, reg_done_frm, 0);
29781 +		VOP_CTRL_SET(vop, mcu_hold_mode, 0);
29888 +		return 0;
29893 +		return 0;
29898 +		return 0;
29903 +		return 0;
29909 +		return 0;
29914 +		return 0;
29919 +		return 0;
29939 +		return 0;
29944 +		return 0;
29949 +		return 0;
29954 +		return 0;
29959 +		return 0;
29964 +		return 0;
30073 +	} while (0)
30101  	unsigned int flags = 0;
30103 -	flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
30104 -	flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
30105 +	flags |= (VOP_WIN_SUPPORT(vop, win, xmirror)) ? DRM_MODE_REFLECT_X : 0;
30106 +	flags |= (VOP_WIN_SUPPORT(vop, win, ymirror)) ? DRM_MODE_REFLECT_Y : 0;
30130 +	return 0;
30140 +	uint64_t feature = 0;
30166 +	drm_object_attach_property(&win->base.base, private->eotf_prop, 0);
30168 +				   private->color_space_prop, 0);
30172 +				   private->async_commit_prop, 0);
30182 +	drm_plane_create_zpos_property(&win->base, win->win_id, 0, vop->num_wins - 1);
30187 +							  "INPUT_WIDTH", 0, vop_data->max_input.width);
30189 +							   "INPUT_HEIGHT", 0, vop_data->max_input.height);
30192 +							   "OUTPUT_WIDTH", 0, vop_data->max_input.width);
30194 +							    "OUTPUT_HEIGHT", 0, vop_data->max_input.height);
30200 +	 * Bit 31 is used as a flag to disable (0) or enable
30203 +	win->color_key_prop = drm_property_create_range(vop->drm_dev, 0,
30204 +							"colorkey", 0, 0x80ffffff);
30211 +	drm_object_attach_property(&win->base.base, win->input_width_prop, 0);
30212 +	drm_object_attach_property(&win->base.base, win->input_height_prop, 0);
30213 +	drm_object_attach_property(&win->base.base, win->output_width_prop, 0);
30214 +	drm_object_attach_property(&win->base.base, win->output_height_prop, 0);
30215 +	drm_object_attach_property(&win->base.base, win->scale_prop, 0);
30216 +	drm_object_attach_property(&win->base.base, win->color_key_prop, 0);
30218 +	return 0;
30233 +	dsp_lut = of_parse_phandle(node, "dsp-lut", 0);
30259 +		for (i = 0; i < lut_len; i++) {
30275 +	return 0;
30292 +					   0xffffffff);
30301 +	return 0;
30309 +	u64 feature = 0;
30327 +					   0xffffffff);
30336 +	return 0;
30349 +	int ret = 0;
30357 -	for (i = 0; i < vop_data->win_size; i++) {
30360 +	for (i = 0; i < vop->num_wins; i++) {
30370 -					       0, &vop_plane_funcs,
30378 +		if (vop_plane_init(vop, win, 0)) {
30396 -		drm_crtc_enable_color_mgmt(crtc, 0, false, vop_data->lut_size);
30403 -	for (i = 0; i < vop_data->win_size; i++) {
30406 +	for (i = 0; i < vop->num_wins; i++) {
30443 +	drm_object_attach_property(&crtc->base, private->aclk_prop, 0);
30444 +	drm_object_attach_property(&crtc->base, private->bg_prop, 0);
30445 +	drm_object_attach_property(&crtc->base, private->line_flag_prop, 0);
30475 +			for (i = 0; i < lut_len; i++) {
30485 +		drm_crtc_enable_color_mgmt(crtc, 0, false, lut_len);
30490 +		for (i = 0; i < lut_len; i++) {
30496  	return 0;
30546 -	if (ret < 0) {
30552 -	if (ret < 0) {
30559 -	if (ret < 0) {
30565 -	if (ret < 0) {
30584 -	VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
30586 -	for (i = 0; i < vop->len; i += sizeof(u32))
30590 -	VOP_REG_SET(vop, common, dsp_blank, 0);
30592 -	for (i = 0; i < vop->data->win_size; i++) {
30614 +		return 0;
30631  	return 0;
30653 +	unsigned int num_wins = 0;
30655 +	uint8_t plane_id = 0;
30665  	for (i = 0; i < vop_data->win_size; i++) {
30689 +		vop_win->area_id = 0;
30710 -	int ret = 0;
30719 -	if (mstimeout <= 0) {
30722 +		for (j = 0; j < win_data->area_size; j++) {
30775 +	for (i = 0; i < vop->num_wins; i++) {
30778 -	if (jiffies_left == 0) {
30791 +	return 0;
30804 +	int num_wins = 0;
30812 +	for (i = 0; i < vop_data->win_size; i++) {
30841 -	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
30845 +		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
30905  	irq = platform_get_irq(pdev, 0);
30906  	if (irq < 0) {
30923 -	if (ret < 0) {
30961 -	return 0;
30970 +	return 0;
31005  #define VOP_MINOR(version)		((version) & 0xff)
31008 +#define VOP_VERSION_RK3568	VOP_VERSION(0x40, 0x15)
31009 +#define VOP_VERSION_RK3588	VOP_VERSION(0x40, 0x17)
31020 +#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE	BIT(0)
31026 +#define AFBDC_FMT_RGB565	0x0
31027 +#define AFBDC_FMT_U8U8U8U8	0x5
31028 +#define AFBDC_FMT_U8U8U8	0x4
31030 +#define VOP_FEATURE_OUTPUT_RGB10	BIT(0)
31042 +#define WIN_FEATURE_HDR2SDR		BIT(0)
31066 +	ROCKCHIP_VOP_WIN0 = 0,
31081 +	LAST_FRAME_PWM_VAL	= 0x0,
31082 +	CUR_FRAME_PWM_VAL	= 0x1,
31083 +	STAGE_BY_STAGE		= 0x2
31104 +#define ROCKCHIP_VOP2_DSC_8K	0
31109 + * should be all none zero, 0 will be
31117 +#define VOP2_PD_CLUSTER0	BIT(0)
31127 + * should be all none zero, 0 will be
31130 +#define VOP2_MEM_PG_VP0		BIT(0)
31139 +#define DSP_BG_SWAP		0x1
31140 +#define DSP_RB_SWAP		0x2
31141 +#define DSP_RG_SWAP		0x4
31142 +#define DSP_DELTA_SWAP		0x8
31157  	VOP_FMT_ARGB8888 = 0,
31168 +	VOP_DSC_IF_DISABLE = 0,
31519 +	MCU_WRCMD = 0,
31981 -#define VOP_FEATURE_OUTPUT_RGB10	BIT(0)
32144 -#define DSP_HOLD_VALID_INTR		(1 << 0)
32148 +#define DSP_HOLD_VALID_INTR		BIT(0)
32187 -#define ROCKCHIP_OUT_MODE_P888	0
32190 +#define ROCKCHIP_OUT_MODE_P888		0
32191 +#define ROCKCHIP_OUT_MODE_BT1120	0
32203 -#define ROCKCHIP_OUTPUT_DSI_DUAL	BIT(0)
32205 +#define ROCKCHIP_OUT_MODE(x)		((x) & 0xffff)
32236  	SCALE_DOWN_AVG = 0x1
32252  	RGB888_TO_RGB565 = 0x0,
32253  	RGB888_TO_RGB666 = 0x1
32256  	HSYNC_POSITIVE = 0,
32327 -#define DISPLAY_OUTPUT_RGB		0
32332 +#define PX30_GRF_PD_VO_CON1		0x0438
32339 +#define RK3126_GRF_LVDS_CON0		0x0150
32345 +#define RK3288_GRF_SOC_CON6		0x025c
32347 +#define RK3288_GRF_SOC_CON7		0x0260
32359 +#define RK3288_LVDS_CON_SELECT(x)	HIWORD_UPDATE(x,  2,  0)
32361 +#define RK3368_GRF_SOC_CON7		0x041c
32367 +#define RK3568_GRF_VO_CON0		0x0360
32372 +#define RK3568_GRF_VO_CON2		0x0368
32376 +#define RK3568_LVDS0_P2S_EN(x)		HIWORD_UPDATE(x,  0,  0)
32377 +#define RK3568_GRF_VO_CON3		0x036c
32381 +#define RK3568_LVDS1_P2S_EN(x)		HIWORD_UPDATE(x,  0,  0)
32458 -	if (strncmp(s, "jeida-18", 8) == 0)
32460 -	else if (strncmp(s, "jeida-24", 8) == 0)
32462 -	else if (strncmp(s, "vesa-24", 7) == 0)
32476 -	if (strncmp(s, "rgb", 3) == 0)
32478 -	else if (strncmp(s, "lvds", 4) == 0)
32480 -	else if (strncmp(s, "duallvds", 8) == 0)
32487 +		return 0;
32516 -	return 0;
32529 -	if (ret < 0) {
32534 -	if (ret < 0) {
32547 -			      RK3288_LVDS_PLL_FBDIV_REG2(0x46));
32581 -			      RK3288_LVDS_PLL_FBDIV_REG2(0x46));
32582 -		rk3288_writel(lvds, RK3288_LVDS_CH0_REG4, 0x00);
32583 -		rk3288_writel(lvds, RK3288_LVDS_CH0_REG5, 0x00);
32590 +		bus_format = info->bus_formats[0];
32611 -		      RK3288_LVDS_PLL_FBDIV_REG3(0x46));
32613 -		      RK3288_LVDS_PLL_PREDIV_REGD(0x0a));
32622 -	return 0;
32639 -	if (ret != 0)
32656 -	u8 pin_hsync = (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0;
32657 -	u8 pin_dclk = (mode->flags & DRM_MODE_FLAG_PCSYNC) ? 1 : 0;
32672 -	if ((mode->htotal - mode->hsync_start) & 0x01)
32676 -	val |= (0xffff << 16);
32692 +		s->bus_format = info->bus_formats[0];
32697 -	if (ret < 0)
32709 -	if (ret < 0)
32730 +#if 0
32749  	return 0;
32762 -	if (ret < 0) {
32807 -	if (ret < 0) {
32824 -			   PX30_LVDS_MODE_EN(0) | PX30_LVDS_P2S_EN(0));
32856 -	if (vop < 0)
32946 -	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
32978 -	if (ret < 0) {
32985 -	return 0;
33056 -	int ret = 0, child_count = 0;
33058 -	u32 endpoint_id = 0;
33096 -	if (lvds->output < 0) {
33114 +		return 0;
33116 -	if (lvds->format < 0) {
33135  	if (ret < 0) {
33157  		if (ret < 0) {
33168 +		drm_object_attach_property(&connector->base, private->connector_id_prop, 0);
33170  		ret = drm_bridge_attach(encoder, lvds->bridge, NULL, 0);
33183  	return 0;
33234 +	if (lvds->id < 0)
33235 +		lvds->id = 0;
33287 +	return 0;
33291 -	if (ret < 0) {
33308 +		     PX30_LVDS_MODE_EN(0) | PX30_LVDS_P2S_EN(0));
33326 +		     RK3126_LVDS_P2S_EN(0) | RK3126_LVDS_MODE_EN(0));
33345 +	val = RK3288_LVDS_PWRDWN(0) | RK3288_LVDS_CON_CLKINV(0) |
33359 +			val |= RK3288_LVDS_CON_STARTPHASE(0);
33362 +		val |= RK3288_LVDS_CON_ENABLE_2(0) |
33397 +		     RK3368_LVDS_MODE_EN(0) | RK3368_LVDS_P2S_EN(0));
33424 +		lvds->pixel_order = pixel_order >= 0 ? pixel_order : 0;
33427  	return 0;
33441 +	regmap_write(lvds->grf, RK3568_GRF_VO_CON2, RK3568_LVDS0_MODE_EN(0));
33494 +#define PX30_GRF_PD_VO_CON1		0x0438
33498 +#define RK1808_GRF_PD_VO_CON1		0x0444
33501 +#define RV1106_VENC_GRF_VOP_IO_WRAPPER	0x1000c
33502 +#define RV1106_IO_BYPASS_SEL(v)		HIWORD_UPDATE(v, 0, 1)
33503 +#define RV1106_VOGRF_VOP_PIPE_BYPASS	0x60034
33504 +#define RV1106_VOP_PIPE_BYPASS(v)	HIWORD_UPDATE(v, 0, 1)
33506 +#define RV1126_GRF_IOFUNC_CON3		0x1026c
33507 +#define RV1126_LCDC_IO_BYPASS(v)	HIWORD_UPDATE(v, 0, 0)
33509 +#define RK3288_GRF_SOC_CON6		0x025c
33511 +#define RK3288_GRF_SOC_CON7		0x0260
33518 +#define RK3568_GRF_VO_CON1		0X0364
33577 +		return 0;
33662 -		bus_format = info->bus_formats[0];
33663 +		s->bus_format = info->bus_formats[0];
33715  	return 0;
33738 +	if (max_clock != 0 && request_clock > max_clock)
33777 +	if (ret < 0) {
33792 +		if (ret < 0) {
33803 +		if (ret < 0) {
33811 +		drm_object_attach_property(&connector->base, private->connector_id_prop, 0);
33815 +		ret = drm_bridge_attach(encoder, rgb->bridge, NULL, 0);
33823 +	return 0;
33860 -	int ret = 0, child_count = 0;
33873 +	if (id < 0)
33874 +		id = 0;
33881 -	port = of_graph_get_port_by_id(dev->of_node, 0);
33887 -			endpoint_id = 0;
33889 -		/* if subdriver (> 0) or error case (< 0), ignore entry */
33890 -		if (rockchip_drm_endpoint_is_subdriver(endpoint) != 0)
33894 -		ret = drm_of_find_panel_or_bridge(dev->of_node, 0, endpoint_id,
33929 -	if (ret < 0) {
33940 +	return 0;
33944 -	if (ret < 0) {
33974 -	ret = drm_bridge_attach(encoder, rgb->bridge, NULL, 0);
34005 +		     RK3288_LVDS_PWRDWN(0) | RK3288_LVDS_CON_ENABLE_2(1) |
34006 +		     RK3288_LVDS_CON_ENABLE_1(1) | RK3288_LVDS_CON_CLKINV(0) |
34017 +		     RK3288_LVDS_PWRDWN(1) | RK3288_LVDS_CON_ENABLE_2(0) |
34018 +		     RK3288_LVDS_CON_ENABLE_1(0) | RK3288_LVDS_CON_TTL_EN(0));
34062 +		     RV1106_IO_BYPASS_SEL(rgb->data_sync_bypass) ? 0x3 : 0x0);
34064 +		     RV1106_VOP_PIPE_BYPASS(rgb->data_sync_bypass) ? 0x3 : 0x0);
34163 +		VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
34168 +		VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
34244 -	.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
34245 -	.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
34246 -	.scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
34247 -	.scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
34292 -	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
34293 -	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
34294 -	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
34295 -	.act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
34296 -	.dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
34297 -	.dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
34298 -	.yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
34299 -	.uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
34300 -	.yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
34301 -	.uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
34303 +	.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
34304 +	.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
34305 +	.cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
34306 +	.cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
34307 +	.cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
34308 +	.yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
34309 +	.yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
34310 +	.yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
34311 +	.yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
34312 +	.yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
34313 +	.line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
34314 +	.cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
34315 +	.yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
34316 +	.vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
34317 +	.vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
34318 +	.vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
34319 +	.vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
34320 +	.bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
34321 +	.cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
34322 +	.yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
34323 +	.lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
34329 +	.scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
34330 +	.scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
34331 +	.scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
34332 +	.scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
34339 +	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
34340 +	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
34341 +	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
34342 +	.csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
34343 +	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
34344 +	.xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
34345 +	.ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
34346 +	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
34347 +	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
34348 +	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
34349 +	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
34350 +	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
34351 +	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
34352 +	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
34353 +	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffff, 0),
34354 +	.global_alpha_val = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 16),
34355 +	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
34356 +	.channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
34363 -	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
34364 -	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
34365 -	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
34366 -	.act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
34367 -	.dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
34368 -	.dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
34369 -	.yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
34370 -	.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
34371 +	.gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
34372 +	.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
34373 +	.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
34374 +	.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
34375 +	.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
34376 +	.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
34377 +	.yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
34378 +	.yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
34379 +	.src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xffff, 0),
34380 +	.global_alpha_val = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 16),
34381 +	.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0),
34385 -	{ .base = 0x00, .phy = &rk3036_win0_data,
34387 -	{ .base = 0x00, .phy = &rk3036_win1_data,
34390 +	.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
34391 +	.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
34392 +	.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
34393 +	.yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
34394 +	.yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
34403 +	.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
34404 +	.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
34405 +	.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
34406 +	.yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
34407 +	.yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
34413 -	.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
34414 -	.status = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 0),
34415 -	.enable = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 4),
34416 -	.clear = VOP_REG_SYNC(RK3036_INT_STATUS, 0xf, 8),
34418 +	.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
34419 +	.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
34420 +	.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
34421 +	.yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
34422 +	.yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
34426 -	.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
34427 -	.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
34428 -	.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
34429 -	.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
34437 -	.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
34439 +	.version = VOP_REG(RK3288_VERSION_INFO, 0xffff, 16),
34440 +	.standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
34441 +	.dma_stop = VOP_REG(RK3288_SYS_CTRL, 0x1, 21),
34442 +	.axi_outstanding_max_num = VOP_REG(RK3288_SYS_CTRL1, 0x1f, 13),
34443 +	.axi_max_outstanding_en = VOP_REG(RK3288_SYS_CTRL1, 0x1, 12),
34444 +	.reg_done_frm = VOP_REG_VER(RK3288_SYS_CTRL1, 0x1, 24, 3, 5, -1),
34445 +	.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
34446 +	.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
34447 +	.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
34448 +	.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
34449 +	.vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
34450 +	.vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
34451 +	.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
34452 +	.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
34453 +	.vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
34454 +	.post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
34455 +	.post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0),
34457 +	.dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
34458 +	.auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
34459 +	.dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
34460 +	.post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
34461 +	.global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
34462 +	.overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
34463 +	.core_dclk_div = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 4, 3, 4, -1),
34464 +	.p2i_en = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 5, 3, 4, -1),
34465 +	.dclk_ddr = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 8, 3, 1, -1),
34466 +	.dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
34467 +	.hdmi_dclk_out_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 1, 1),
34468 +	.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
34469 +	.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
34470 +	.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
34471 +	.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
34472 +	.mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
34473 +	.data01_swap = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 17, 3, 5, -1),
34474 +	.dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1),
34475 +	.pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x7, 4, 3, 0, 1),
34476 +	.dp_dclk_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x1, 19, 3, 5, -1),
34477 +	.dp_pin_pol = VOP_REG_VER(RK3399_DSP_CTRL1, 0x7, 16, 3, 5, -1),
34478 +	.rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 19, 3, 2, -1),
34479 +	.rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1),
34480 +	.tve_dclk_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 24),
34481 +	.tve_dclk_pol = VOP_REG(RK3288_SYS_CTRL, 0x1, 25),
34482 +	.tve_sw_mode = VOP_REG(RK3288_SYS_CTRL, 0x1, 26),
34483 +	.sw_uv_offset_en  = VOP_REG(RK3288_SYS_CTRL, 0x1, 27),
34484 +	.sw_genlock   = VOP_REG(RK3288_SYS_CTRL, 0x1, 28),
34485 +	.hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 23, 3, 2, -1),
34486 +	.hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1),
34487 +	.edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 2, -1),
34488 +	.edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1),
34489 +	.mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1),
34490 +	.mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1),
34492 +	.dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4),
34493 +	.dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3),
34494 +	.dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2),
34495 +	.pre_dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
34496 +	.dither_up_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
34498 +	.dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
34499 +	.dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
34500 +	.dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
34501 +	.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
34502 +	.update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1),
34503 +	.lut_buffer_index = VOP_REG_VER(RK3399_DBG_POST_REG1, 0x1, 1, 3, 5, -1),
34504 +	.dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
34505 +	.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
34507 +	.afbdc_rstn = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 3, 3, 5, -1),
34508 +	.afbdc_en = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 0, 3, 5, -1),
34509 +	.afbdc_sel = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x3, 1, 3, 5, -1),
34510 +	.afbdc_format = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1f, 16, 3, 5, -1),
34512 +					      0x1, 21, 3, 5, -1),
34513 +	.afbdc_hdr_ptr = VOP_REG_VER(RK3399_AFBCD0_HDR_PTR, 0xffffffff,
34514 +				     0, 3, 5, -1),
34515 +	.afbdc_pic_size = VOP_REG_VER(RK3399_AFBCD0_PIC_SIZE, 0xffffffff,
34516 +				      0, 3, 5, -1),
34517 +	.bcsh_brightness = VOP_REG(RK3288_BCSH_BCS, 0xff, 0),
34518 +	.bcsh_contrast = VOP_REG(RK3288_BCSH_BCS, 0x1ff, 8),
34519 +	.bcsh_sat_con = VOP_REG(RK3288_BCSH_BCS, 0x3ff, 20),
34520 +	.bcsh_out_mode = VOP_REG(RK3288_BCSH_BCS, 0x3, 30),
34521 +	.bcsh_sin_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 0),
34522 +	.bcsh_cos_hue = VOP_REG(RK3288_BCSH_H, 0x1ff, 16),
34523 +	.bcsh_r2y_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 6, 3, 1, -1),
34524 +	.bcsh_r2y_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 4, 3, 1, -1),
34525 +	.bcsh_y2r_csc_mode = VOP_REG_VER(RK3368_BCSH_CTRL, 0x3, 2, 3, 1, -1),
34526 +	.bcsh_y2r_en = VOP_REG_VER(RK3368_BCSH_CTRL, 0x1, 0, 3, 1, -1),
34527 +	.bcsh_color_bar = VOP_REG(RK3288_BCSH_COLOR_BAR, 0xffffff, 8),
34528 +	.bcsh_en = VOP_REG(RK3288_BCSH_COLOR_BAR, 0x1, 0),
34530 +	.xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
34531 +	.ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
34533 +	.dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
34535 +	.cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
34539 -	.standby = VOP_REG_SYNC(RK3036_SYS_CTRL, 0x1, 30),
34540 -	.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
34541 -	.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
34542 -	.dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
34543 -	.dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
34544 -	.dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
34545 -	.cfg_done = VOP_REG_SYNC(RK3036_REG_CFG_DONE, 0x1, 0),
34553 +	{ .base = 0x00, .phy = &rk3288_win01_data,
34555 +	{ .base = 0x40, .phy = &rk3288_win01_data,
34557 +	{ .base = 0x00, .phy = &rk3288_win23_data,
34561 +	{ .base = 0x50, .phy = &rk3288_win23_data,
34585 -	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
34586 -	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
34587 -	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
34588 -	.dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
34589 -	.dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
34590 -	.yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0),
34591 -	.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
34595 +	.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
34596 +	.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
34597 +	.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
34598 +	.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
34602 -	{ .base = 0x00, .phy = &rk3036_win0_data,
34604 -	{ .base = 0x00, .phy = &rk3126_win1_data,
34607 +	.grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 13),
34618 +	.grf_dclk_inv = VOP_REG(RK3288_GRF_SOC_CON15, 0x1, 15),
34622 +	.soc_id = 0x3288,
34623 +	.vop_id = 0,
34624 +	.version = VOP_VERSION(3, 0),
34636 +	.soc_id = 0x3288,
34638 +	.version = VOP_VERSION(3, 0),
34652 -	0, 0,
34656 -	0,
34659 -	0, 0,
34673 -	.line_flag_num[0] = VOP_REG(PX30_LINE_FLAG, 0xfff, 0),
34674 -	.status = VOP_REG_MASK_SYNC(PX30_INTR_STATUS, 0xffff, 0),
34675 -	.enable = VOP_REG_MASK_SYNC(PX30_INTR_EN, 0xffff, 0),
34676 -	.clear = VOP_REG_MASK_SYNC(PX30_INTR_CLEAR, 0xffff, 0),
34680 +	.line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
34681 +	.line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
34682 +	.status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
34683 +	.enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
34684 +	.clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
34688 -	.standby = VOP_REG_SYNC(PX30_SYS_CTRL2, 0x1, 1),
34689 -	.out_mode = VOP_REG(PX30_DSP_CTRL2, 0xf, 16),
34690 -	.dsp_blank = VOP_REG(PX30_DSP_CTRL2, 0x1, 14),
34691 -	.dither_down_en = VOP_REG(PX30_DSP_CTRL2, 0x1, 8),
34692 -	.dither_down_sel = VOP_REG(PX30_DSP_CTRL2, 0x1, 7),
34693 -	.dither_down_mode = VOP_REG(PX30_DSP_CTRL2, 0x1, 6),
34694 -	.cfg_done = VOP_REG_SYNC(PX30_REG_CFG_DONE, 0x1, 0),
34698 +	.gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
34699 +	.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
34700 +	.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
34701 +	.ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
34702 +	.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
34703 +	.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
34704 +	.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
34705 +	.yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
34706 +	.yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
34707 +	.src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xffff, 0),
34708 +	.global_alpha_val = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 16),
34709 +	.dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xffffffff, 0),
34713 -	.htotal_pw = VOP_REG(PX30_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
34714 -	.hact_st_end = VOP_REG(PX30_DSP_HACT_ST_END, 0x0fff0fff, 0),
34715 -	.vtotal_pw = VOP_REG(PX30_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
34716 -	.vact_st_end = VOP_REG(PX30_DSP_VACT_ST_END, 0x0fff0fff, 0),
34718 +	.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
34719 +	.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
34720 +	.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
34721 +	.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
34722 +	.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
34723 +	.yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
34724 +	.yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
34728 -	.rgb_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 1),
34729 -	.rgb_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 2),
34730 -	.rgb_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 0),
34731 -	.mipi_dclk_pol = VOP_REG(PX30_DSP_CTRL0, 0x1, 25),
34732 -	.mipi_pin_pol = VOP_REG(PX30_DSP_CTRL0, 0x7, 26),
34733 -	.mipi_en = VOP_REG(PX30_DSP_CTRL0, 0x1, 24),
34735 +	.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
34736 +	.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
34737 +	.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
34738 +	.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
34739 +	.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
34740 +	.yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
34741 +	.yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
34745 -	.scale_yrgb_x = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
34746 -	.scale_yrgb_y = VOP_REG(PX30_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
34747 -	.scale_cbcr_x = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
34748 -	.scale_cbcr_y = VOP_REG(PX30_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
34750 +	.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
34751 +	.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
34752 +	.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
34753 +	.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
34754 +	.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
34755 +	.yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
34756 +	.yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
34764 -	.enable = VOP_REG(PX30_WIN0_CTRL0, 0x1, 0),
34765 -	.format = VOP_REG(PX30_WIN0_CTRL0, 0x7, 1),
34766 -	.rb_swap = VOP_REG(PX30_WIN0_CTRL0, 0x1, 12),
34767 -	.act_info = VOP_REG(PX30_WIN0_ACT_INFO, 0xffffffff, 0),
34768 -	.dsp_info = VOP_REG(PX30_WIN0_DSP_INFO, 0xffffffff, 0),
34769 -	.dsp_st = VOP_REG(PX30_WIN0_DSP_ST, 0xffffffff, 0),
34770 -	.yrgb_mst = VOP_REG(PX30_WIN0_YRGB_MST0, 0xffffffff, 0),
34771 -	.uv_mst = VOP_REG(PX30_WIN0_CBR_MST0, 0xffffffff, 0),
34772 -	.yrgb_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 0),
34773 -	.uv_vir = VOP_REG(PX30_WIN0_VIR, 0x1fff, 16),
34774 -	.alpha_pre_mul = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 2),
34775 -	.alpha_mode = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 1),
34776 -	.alpha_en = VOP_REG(PX30_WIN0_ALPHA_CTRL, 0x1, 0),
34783 -	.enable = VOP_REG(PX30_WIN1_CTRL0, 0x1, 0),
34784 -	.format = VOP_REG(PX30_WIN1_CTRL0, 0x7, 4),
34785 -	.rb_swap = VOP_REG(PX30_WIN1_CTRL0, 0x1, 12),
34786 -	.dsp_info = VOP_REG(PX30_WIN1_DSP_INFO, 0xffffffff, 0),
34787 -	.dsp_st = VOP_REG(PX30_WIN1_DSP_ST, 0xffffffff, 0),
34788 -	.yrgb_mst = VOP_REG(PX30_WIN1_MST, 0xffffffff, 0),
34789 -	.yrgb_vir = VOP_REG(PX30_WIN1_VIR, 0x1fff, 0),
34790 -	.alpha_pre_mul = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 2),
34791 -	.alpha_mode = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 1),
34792 -	.alpha_en = VOP_REG(PX30_WIN1_ALPHA_CTRL, 0x1, 0),
34799 -	.gate = VOP_REG(PX30_WIN2_CTRL0, 0x1, 4),
34800 -	.enable = VOP_REG(PX30_WIN2_CTRL0, 0x1, 0),
34801 -	.format = VOP_REG(PX30_WIN2_CTRL0, 0x3, 5),
34802 -	.rb_swap = VOP_REG(PX30_WIN2_CTRL0, 0x1, 20),
34803 -	.dsp_info = VOP_REG(PX30_WIN2_DSP_INFO0, 0x0fff0fff, 0),
34804 -	.dsp_st = VOP_REG(PX30_WIN2_DSP_ST0, 0x1fff1fff, 0),
34805 -	.yrgb_mst = VOP_REG(PX30_WIN2_MST0, 0xffffffff, 0),
34806 -	.yrgb_vir = VOP_REG(PX30_WIN2_VIR0_1, 0x1fff, 0),
34807 -	.alpha_pre_mul = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 2),
34808 -	.alpha_mode = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 1),
34809 -	.alpha_en = VOP_REG(PX30_WIN2_ALPHA_CTRL, 0x1, 0),
34817 -	{ .base = 0x00, .phy = &px30_win0_data,
34819 +	{ .base = 0x00, .phy = &rk3288_win01_data,
34821 -	{ .base = 0x00, .phy = &px30_win1_data,
34822 +	{ .base = 0x40, .phy = &rk3288_win01_data,
34824 -	{ .base = 0x00, .phy = &px30_win2_data,
34826 +	{ .base = 0x00, .phy = &rk3368_win23_data,
34830 +	{ .base = 0x50, .phy = &rk3368_win23_data,
34845 +	.soc_id = 0x3368,
34846 +	.vop_id = 0,
34858 -	{ .base = 0x00, .phy = &px30_win1_data,
34863 +	.line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
34864 +	.line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
34865 +	.status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
34866 +	.enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
34867 +	.clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
34879 +	.grf_dclk_inv = VOP_REG(RK3368_GRF_SOC_CON6, 0x1, 5),
34883 -	.scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
34884 -	.scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
34885 -	.scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
34886 -	.scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
34888 +	.soc_id = 0x3366,
34889 +	.vop_id = 0,
34906 -	.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0),
34907 -	.format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 4),
34908 -	.rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 19),
34909 -	.act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0),
34910 -	.dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0),
34911 -	.dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0),
34912 -	.yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0),
34913 -	.uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0),
34914 -	.yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0),
34915 -	.uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16),
34917 +	0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
34918 +	0x00000000, 0xfff4cab4, 0x00087932, 0xfff1d4f2,
34925 -	.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1),
34926 -	.format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 7),
34927 -	.rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 23),
34928 -	.act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0),
34929 -	.dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0),
34930 -	.dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0),
34931 -	.yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0),
34932 -	.uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0),
34933 -	.yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0),
34934 -	.uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16),
34936 +	0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
34937 +	0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
34944 -	.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2),
34945 -	.format = VOP_REG(RK3066_SYS_CTRL1, 0x7, 10),
34946 -	.rb_swap = VOP_REG(RK3066_SYS_CTRL1, 0x1, 27),
34947 -	.dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0),
34948 -	.dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0),
34949 -	.yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0),
34950 -	.yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0),
34952 +	0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
34953 +	0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
34957 -	.htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
34958 -	.hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0),
34959 -	.vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
34960 -	.vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0),
34962 +	0x02040107, 0xff680064, 0x01c2fed6, 0xfe8701c2,
34963 +	0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
34967 -	.pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
34969 +	0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
34970 +	0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
34974 -	.standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1),
34975 -	.out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0),
34976 -	.cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0),
34977 -	.dither_down_en = VOP_REG(RK3066_DSP_CTRL0, 0x1, 11),
34978 -	.dither_down_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 10),
34979 -	.dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24),
34980 -	.dither_up = VOP_REG(RK3066_DSP_CTRL0, 0x1, 9),
34981 -	.dsp_lut_en = VOP_REG(RK3066_SYS_CTRL1, 0x1, 31),
34982 -	.data_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 25),
34984 +	0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
34985 +	0x0000ffd7, 0x00010200, 0x00080200, 0x00080200,
34989 -	{ .base = 0x00, .phy = &rk3066_win0_data,
34991 -	{ .base = 0x00, .phy = &rk3066_win1_data,
34993 -	{ .base = 0x00, .phy = &rk3066_win2_data,
34996 +	0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
34997 +	0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
35010 +	0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
35011 +	0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
35017 -	.line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12),
35018 -	.status = VOP_REG(RK3066_INT_STATUS, 0xf, 0),
35019 -	.enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4),
35020 -	.clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8),
35022 +	0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
35023 +	0x0000047a, 0x00000200, 0x00000200, 0x00000200,
35035 +	0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
35036 +	0x00000394, 0x00000200, 0x00000200, 0x00000200,
35040 -	.scale_yrgb_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
35041 -	.scale_yrgb_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
35042 -	.scale_cbcr_x = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
35043 -	.scale_cbcr_y = VOP_REG(RK3188_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
35056 -	.enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 0),
35057 -	.format = VOP_REG(RK3188_SYS_CTRL, 0x7, 3),
35058 -	.rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 15),
35059 -	.act_info = VOP_REG(RK3188_WIN0_ACT_INFO, 0x1fff1fff, 0),
35060 -	.dsp_info = VOP_REG(RK3188_WIN0_DSP_INFO, 0x0fff0fff, 0),
35061 -	.dsp_st = VOP_REG(RK3188_WIN0_DSP_ST, 0x1fff1fff, 0),
35062 -	.yrgb_mst = VOP_REG(RK3188_WIN0_YRGB_MST0, 0xffffffff, 0),
35063 -	.uv_mst = VOP_REG(RK3188_WIN0_CBR_MST0, 0xffffffff, 0),
35064 -	.yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 0),
35071 -	.enable = VOP_REG(RK3188_SYS_CTRL, 0x1, 1),
35072 -	.format = VOP_REG(RK3188_SYS_CTRL, 0x7, 6),
35073 -	.rb_swap = VOP_REG(RK3188_SYS_CTRL, 0x1, 19),
35075 -	.dsp_info = VOP_REG(RK3188_WIN1_DSP_INFO, 0x07ff07ff, 0),
35076 -	.dsp_st = VOP_REG(RK3188_WIN1_DSP_ST, 0x0fff0fff, 0),
35077 -	.yrgb_mst = VOP_REG(RK3188_WIN1_MST, 0xffffffff, 0),
35078 -	.yrgb_vir = VOP_REG(RK3188_WIN_VIR, 0x1fff, 16),
35082 -	.htotal_pw = VOP_REG(RK3188_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
35083 -	.hact_st_end = VOP_REG(RK3188_DSP_HACT_ST_END, 0x0fff0fff, 0),
35084 -	.vtotal_pw = VOP_REG(RK3188_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
35085 -	.vact_st_end = VOP_REG(RK3188_DSP_VACT_ST_END, 0x0fff0fff, 0),
35089 -	.pin_pol = VOP_REG(RK3188_DSP_CTRL0, 0xf, 4),
35093 -	.gate_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 31),
35094 -	.standby = VOP_REG(RK3188_SYS_CTRL, 0x1, 30),
35095 -	.out_mode = VOP_REG(RK3188_DSP_CTRL0, 0xf, 0),
35096 -	.cfg_done = VOP_REG(RK3188_REG_CFG_DONE, 0x1, 0),
35097 -	.dither_down_sel = VOP_REG(RK3188_DSP_CTRL0, 0x1, 27),
35098 -	.dither_down_en = VOP_REG(RK3188_DSP_CTRL0, 0x1, 11),
35099 -	.dither_down_mode = VOP_REG(RK3188_DSP_CTRL0, 0x1, 10),
35100 -	.dsp_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 24),
35101 -	.dither_up = VOP_REG(RK3188_DSP_CTRL0, 0x1, 9),
35102 -	.dsp_lut_en = VOP_REG(RK3188_SYS_CTRL, 0x1, 28),
35103 -	.data_blank = VOP_REG(RK3188_DSP_CTRL1, 0x1, 25),
35107 -	{ .base = 0x00, .phy = &rk3188_win0_data,
35109 -	{ .base = 0x00, .phy = &rk3188_win1_data,
35134 -	.line_flag_num[0] = VOP_REG(RK3188_INT_STATUS, 0xfff, 12),
35135 -	.status = VOP_REG(RK3188_INT_STATUS, 0xf, 0),
35136 -	.enable = VOP_REG(RK3188_INT_STATUS, 0xf, 4),
35137 -	.clear = VOP_REG(RK3188_INT_STATUS, 0xf, 8),
35139 +	.r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
35140 +	.y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
35141 +	.r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
35156 +	.r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
35157 +	.y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
35158 +	.r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
35165 -	.cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
35166 -	.cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
35167 -	.cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
35168 -	.cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
35169 -	.cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
35170 -	.yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
35171 -	.yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
35172 -	.yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
35173 -	.yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
35174 -	.yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
35175 -	.line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
35176 -	.cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
35177 -	.yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
35178 -	.vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
35179 -	.vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
35180 -	.vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
35181 -	.vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
35182 -	.bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
35183 -	.cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
35184 -	.yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
35185 -	.lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
35187 +	.r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 16),
35188 +	.r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 18),
35190 +	.csc_mode = VOP_REG(RK3399_YUV2YUV_WIN, 0x3, 22),
35195 -	.scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
35196 -	.scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
35197 -	.scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
35198 -	.scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
35200 +	.r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 24),
35201 +	.r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 26),
35203 +	.csc_mode = VOP_REG(RK3399_YUV2YUV_WIN, 0x3, 30),
35214  	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
35215  	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
35216 +	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
35217 +	.fmt_yuyv = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 17),
35218 +	.csc_mode = VOP_REG_VER(RK3288_WIN0_CTRL0, 0x3, 10, 3, 2, -1),
35219  	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
35220 +	.xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
35221 +	.ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
35222  	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
35223  	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
35224  	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
35226  	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
35227  	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
35228  	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
35229 -	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
35230 -	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
35231 -	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
35232 +	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffff, 0),
35233 +	.global_alpha_val = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 16),
35234 +	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
35235 +	.channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
35242 -	.enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
35243 -	.gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
35244 -	.format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
35245 -	.rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
35246 -	.dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
35247 -	.dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
35248 -	.yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
35249 -	.yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
35250 -	.src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
35251 -	.dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
35253 +	{ .base = 0x00, .phy = &rk3399_win01_data, .csc = &rk3399_win0_csc,
35257 +	{ .base = 0x40, .phy = &rk3399_win01_data, .csc = &rk3399_win1_csc,
35261 +	{ .base = 0x00, .phy = &rk3368_win23_data, .csc = &rk3399_win2_csc,
35267 +	{ .base = 0x50, .phy = &rk3368_win23_data, .csc = &rk3399_win3_csc,
35276 -	.htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
35277 -	.hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
35278 -	.vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
35279 -	.vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
35280 -	.hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
35281 -	.vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
35283 +	.soc_id = 0x3399,
35284 +	.vop_id = 0,
35297 -	.pin_pol = VOP_REG(RK3288_DSP_CTRL0, 0xf, 4),
35298 -	.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
35299 -	.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
35300 -	.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
35301 -	.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
35303 +	{ .base = 0x00, .phy = &rk3399_win01_data, .csc = &rk3399_win0_csc,
35308 +	{ .base = 0x00, .phy = &rk3368_win23_data, .csc = &rk3399_win2_csc,
35318 -	.standby = VOP_REG_SYNC(RK3288_SYS_CTRL, 0x1, 22),
35319 -	.gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
35320 -	.mmu_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 20),
35321 -	.dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4),
35322 -	.dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3),
35323 -	.dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2),
35324 -	.pre_dither_down = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
35325 -	.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
35326 -	.dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
35327 -	.data_blank = VOP_REG(RK3288_DSP_CTRL0, 0x1, 19),
35328 -	.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
35329 -	.out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
35330 -	.cfg_done = VOP_REG_SYNC(RK3288_REG_CFG_DONE, 0x1, 0),
35333 +	.soc_id = 0x3399,
35354  	{ .base = 0x00, .phy = &rk3288_win01_data,
35356  	{ .base = 0x40, .phy = &rk3288_win01_data,
35358 -	{ .base = 0x00, .phy = &rk3288_win23_data,
35360 -	{ .base = 0x50, .phy = &rk3288_win23_data,
35374 -	.line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
35375 -	.status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
35376 -	.enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
35377 -	.clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
35379 +	.soc_id = 0x3228,
35380 +	.vop_id = 0,
35402 +	0,
35422 +	0,
35443 +	0,
35463 +	0,
35483 +	0,
35484 +	0,     0,     1,     2,
35503 +	0,
35523 +	0,  0,  1,  2,
35592 +	0,
35593 +	0,	0,	0,	0,
35594 +	0,	0,	0,	314,
35605 -	0, 0,
35608  	0,
35610 -	0, 0, 0, 0, 0, 0, 0,
35613 +	2083, 1389, 694,  0,
35648 +	.standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
35649 +	.dma_stop = VOP_REG(RK3328_SYS_CTRL, 0x1, 21),
35650 +	.axi_outstanding_max_num = VOP_REG(RK3328_SYS_CTRL1, 0x1f, 13),
35651 +	.axi_max_outstanding_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 12),
35652 +	.reg_done_frm = VOP_REG(RK3328_SYS_CTRL1, 0x1, 24),
35653 +	.auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
35654 +	.htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
35655 +	.hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
35656 +	.vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
35657 +	.vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
35658 +	.vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
35659 +	.vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
35660 +	.hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
35661 +	.vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
35662 +	.vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
35663 +	.post_scl_factor = VOP_REG(RK3328_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
35664 +	.post_scl_ctrl = VOP_REG(RK3328_POST_SCL_CTRL, 0x3, 0),
35665 +	.dsp_out_yuv = VOP_REG(RK3328_POST_SCL_CTRL, 0x1, 2),
35666 +	.dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
35667 +	.dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
35668 +	.post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
35669 +	.global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
35670 +	.overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
35671 +	.core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
35672 +	.dclk_ddr = VOP_REG(RK3328_DSP_CTRL0, 0x1, 8),
35673 +	.p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
35674 +	.rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
35675 +	.hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
35676 +	.edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
35677 +	.mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
35678 +	.tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24),
35679 +	.tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25),
35680 +	.tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26),
35681 +	.sw_uv_offset_en  = VOP_REG(RK3328_SYS_CTRL, 0x1, 27),
35682 +	.sw_genlock   = VOP_REG(RK3328_SYS_CTRL, 0x1, 28),
35683 +	.sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29),
35684 +	.rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
35685 +	.hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
35686 +	.edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
35687 +	.mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
35688 +	.rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
35689 +	.hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
35690 +	.edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
35691 +	.mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
35693 +	.dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4),
35694 +	.dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3),
35695 +	.dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2),
35696 +	.pre_dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1),
35697 +	.dither_up_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
35699 +	.dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
35700 +	.dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
35701 +	.dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
35702 +	.dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
35703 +	.out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
35705 +	.xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
35706 +	.ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
35708 +	.dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
35710 +	.alpha_hard_calc = VOP_REG(RK3328_SYS_CTRL1, 0x1, 27),
35711 +	.level2_overlay_en = VOP_REG(RK3328_SYS_CTRL1, 0x1, 28),
35713 +	.hdr2sdr_en = VOP_REG(RK3328_HDR2DR_CTRL, 0x1, 0),
35714 +	.hdr2sdr_en_win0_csc = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 9),
35715 +	.hdr2sdr_src_min = VOP_REG(RK3328_HDR2DR_SRC_RANGE, 0x3fff, 0),
35716 +	.hdr2sdr_src_max = VOP_REG(RK3328_HDR2DR_SRC_RANGE, 0x3fff, 16),
35717 +	.hdr2sdr_normfaceetf = VOP_REG(RK3328_HDR2DR_NORMFACEETF, 0x7ff, 0),
35718 +	.hdr2sdr_dst_min = VOP_REG(RK3328_HDR2DR_DST_RANGE, 0x3fff, 0),
35719 +	.hdr2sdr_dst_max = VOP_REG(RK3328_HDR2DR_DST_RANGE, 0x3fff, 16),
35720 +	.hdr2sdr_normfacgamma = VOP_REG(RK3328_HDR2DR_NORMFACGAMMA, 0xffff, 0),
35722 +	.bt1886eotf_pre_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 0),
35723 +	.rgb2rgb_pre_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 1),
35724 +	.rgb2rgb_pre_conv_mode = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 2),
35725 +	.st2084oetf_pre_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 3),
35726 +	.bt1886eotf_post_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 4),
35727 +	.rgb2rgb_post_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 5),
35728 +	.rgb2rgb_post_conv_mode = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 6),
35729 +	.st2084oetf_post_conv_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 7),
35730 +	.win_csc_mode_sel = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 31),
35732 +	.bcsh_brightness = VOP_REG(RK3328_BCSH_BCS, 0xff, 0),
35733 +	.bcsh_contrast = VOP_REG(RK3328_BCSH_BCS, 0x1ff, 8),
35734 +	.bcsh_sat_con = VOP_REG(RK3328_BCSH_BCS, 0x3ff, 20),
35735 +	.bcsh_out_mode = VOP_REG(RK3328_BCSH_BCS, 0x3, 30),
35736 +	.bcsh_sin_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 0),
35737 +	.bcsh_cos_hue = VOP_REG(RK3328_BCSH_H, 0x1ff, 16),
35738 +	.bcsh_r2y_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 6),
35739 +	.bcsh_r2y_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 4),
35740 +	.bcsh_y2r_csc_mode = VOP_REG(RK3328_BCSH_CTRL, 0x3, 2),
35741 +	.bcsh_y2r_en = VOP_REG(RK3328_BCSH_CTRL, 0x1, 0),
35742 +	.bcsh_color_bar = VOP_REG(RK3328_BCSH_COLOR_BAR, 0xffffff, 8),
35743 +	.bcsh_en = VOP_REG(RK3328_BCSH_COLOR_BAR, 0x1, 0),
35745 +	.cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
35752 -	.line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
35753 -	.line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
35754 -	.status = VOP_REG_MASK_SYNC(RK3368_INTR_STATUS, 0x3fff, 0),
35755 -	.enable = VOP_REG_MASK_SYNC(RK3368_INTR_EN, 0x3fff, 0),
35756 -	.clear = VOP_REG_MASK_SYNC(RK3368_INTR_CLEAR, 0x3fff, 0),
35757 +	.line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
35758 +	.line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
35759 +	.status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
35760 +	.enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
35761 +	.clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
35769 -	.enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
35770 -	.format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
35771 -	.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
35772 -	.x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
35773 -	.y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
35774 -	.act_info = VOP_REG(RK3368_WIN0_ACT_INFO, 0x1fff1fff, 0),
35775 -	.dsp_info = VOP_REG(RK3368_WIN0_DSP_INFO, 0x0fff0fff, 0),
35776 -	.dsp_st = VOP_REG(RK3368_WIN0_DSP_ST, 0x1fff1fff, 0),
35777 -	.yrgb_mst = VOP_REG(RK3368_WIN0_YRGB_MST, 0xffffffff, 0),
35778 -	.uv_mst = VOP_REG(RK3368_WIN0_CBR_MST, 0xffffffff, 0),
35779 -	.yrgb_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 0),
35780 -	.uv_vir = VOP_REG(RK3368_WIN0_VIR, 0x3fff, 16),
35781 -	.src_alpha_ctl = VOP_REG(RK3368_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
35782 -	.dst_alpha_ctl = VOP_REG(RK3368_WIN0_DST_ALPHA_CTRL, 0xff, 0),
35783 -	.channel = VOP_REG(RK3368_WIN0_CTRL2, 0xff, 0),
35785 +	.r2y_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 8),
35786 +	.r2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 5),
35787 +	.y2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 9),
35794 -	.gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
35795 -	.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
35796 -	.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
35797 -	.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
35798 -	.y_mir_en = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
35799 -	.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
35800 -	.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
35801 -	.yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
35802 -	.yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
35803 -	.src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
35804 -	.dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
35806 +	.r2y_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 10),
35807 +	.r2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 1),
35808 +	.y2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 11),
35812 -	{ .base = 0x00, .phy = &rk3368_win01_data,
35814 -	{ .base = 0x40, .phy = &rk3368_win01_data,
35816 -	{ .base = 0x00, .phy = &rk3368_win23_data,
35818 -	{ .base = 0x50, .phy = &rk3368_win23_data,
35821 +	.r2y_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 12),
35822 +	.r2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 1),
35823 +	.y2r_en = VOP_REG(RK3328_SDR2HDR_CTRL, 0x1, 13),
35827 -	.rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
35828 -	.hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
35829 -	.edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
35830 -	.mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
35831 -	.rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
35832 -	.hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
35833 -	.edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
35834 -	.mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
35835 -	.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
35836 -	.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
35837 -	.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
35838 -	.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
35840 +	{ .base = 0xd0, .phy = &rk3288_win01_data,  .csc = &rk3328_win0_csc,
35843 +	{ .base = 0x1d0, .phy = &rk3288_win01_data, .csc = &rk3328_win1_csc,
35846 +	{ .base = 0x2d0, .phy = &rk3288_win01_data, .csc = &rk3328_win2_csc,
35852 -	.global_regdone_en = VOP_REG(RK3368_SYS_CTRL, 0x1, 11),
35854 +	.soc_id = 0x3328,
35855 +	.vop_id = 0,
35878 +	.scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
35879 +	.scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
35880 +	.scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
35881 +	.scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
35887 -	.line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
35888 -	.line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
35889 -	.status = VOP_REG_MASK_SYNC(RK3366_INTR_STATUS0, 0xffff, 0),
35890 -	.enable = VOP_REG_MASK_SYNC(RK3366_INTR_EN0, 0xffff, 0),
35891 -	.clear = VOP_REG_MASK_SYNC(RK3366_INTR_CLEAR0, 0xffff, 0),
35893 +	.scale_yrgb_x = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 0x0),
35894 +	.scale_yrgb_y = VOP_REG(RK3036_WIN1_SCL_FACTOR_YRGB, 0xffff, 16),
35910 +	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
35911 +	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
35912 +	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
35913 +	.act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
35914 +	.dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
35915 +	.dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
35916 +	.yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
35917 +	.uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
35918 +	.yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
35919 +	.uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
35920 +	.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
35921 +	.alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0),
35922 +	.alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
35926 -	.dp_dclk_pol = VOP_REG(RK3399_DSP_CTRL1, 0x1, 19),
35927 -	.rgb_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 19),
35928 -	.hdmi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 23),
35929 -	.edp_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 27),
35930 -	.mipi_dclk_pol = VOP_REG(RK3368_DSP_CTRL1, 0x1, 31),
35931 -	.dp_pin_pol = VOP_REG(RK3399_DSP_CTRL1, 0x7, 16),
35932 -	.rgb_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 16),
35933 -	.hdmi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 20),
35934 -	.edp_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 24),
35935 -	.mipi_pin_pol = VOP_REG(RK3368_DSP_CTRL1, 0x7, 28),
35936 -	.dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
35937 -	.rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
35938 -	.hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
35939 -	.edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
35940 -	.mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
35941 -	.mipi_dual_channel_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 3),
35946 +	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
35947 +	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
35948 +	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
35949 +	.act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
35950 +	.dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
35951 +	.dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
35952 +	.yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
35953 +	.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
35954 +	.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
35955 +	.alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
35960 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 0),
35961 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 0, 0xffff, 16),
35962 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 0),
35963 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 4, 0xffff, 16),
35964 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 0),
35965 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 8, 0xffff, 16),
35966 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 0),
35967 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 12, 0xffff, 16),
35968 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 16, 0xffff, 0),
35969 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 20, 0xffffffff, 0),
35970 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 24, 0xffffffff, 0),
35971 -		VOP_REG(RK3399_WIN0_YUV2YUV_Y2R + 28, 0xffffffff, 0),
35974 +	{ .base = 0x00, .phy = &rk3036_win0_data,
35976 +	{ .base = 0x00, .phy = &rk3036_win1_data,
35989 -	{ .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data,
35990 -	  .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1) },
35991 -	{ .base = 0x60, .phy = &rk3399_yuv2yuv_win01_data,
35992 -	  .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9) },
35993 -	{ .base = 0xC0, .phy = &rk3399_yuv2yuv_win23_data },
35994 -	{ .base = 0x120, .phy = &rk3399_yuv2yuv_win23_data },
35998 +	.line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
35999 +	.status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
36000 +	.enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
36001 +	.clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
36005 +	.standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
36006 +	.out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
36007 +	.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
36008 +	.dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
36009 +	.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
36010 +	.dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
36011 +	.dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
36012 +	.dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
36013 +	.dither_up_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 9),
36014 +	.dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
36015 +	.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
36016 +	.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
36017 +	.hdmi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 22),
36018 +	.hdmi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 23),
36019 +	.hdmi_pin_pol = VOP_REG(RK3036_INT_SCALER, 0x7, 4),
36020 +	.rgb_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 24),
36021 +	.rgb_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 25),
36022 +	.lvds_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 26),
36023 +	.lvds_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 27),
36024 +	.mipi_en = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 28),
36025 +	.mipi_dclk_pol = VOP_REG(RK3036_AXI_BUS_CTRL, 0x1, 29),
36026 +	.vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
36027 +	.vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
36028 +	.cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
36032 +	.soc_id = 0x3036,
36033 +	.vop_id = 0,
36046 +	.scale_yrgb_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
36047 +	.scale_yrgb_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
36048 +	.scale_cbcr_x = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
36049 +	.scale_cbcr_y = VOP_REG(RK3066_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
36057 -	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
36058 -	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
36059 -	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
36060 -	.x_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 21),
36061 -	.y_mir_en = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 22),
36062 -	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
36063 -	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
36064 -	.dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
36065 -	.yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
36066 -	.uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
36067 -	.yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
36068 -	.uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
36069 -	.src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xff, 0),
36070 -	.dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xff, 0),
36071 -	.channel = VOP_REG(RK3288_WIN0_CTRL2, 0xff, 0),
36072 +	.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 0),
36073 +	.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 4),
36074 +	.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 19),
36075 +	.act_info = VOP_REG(RK3066_WIN0_ACT_INFO, 0x1fff1fff, 0),
36076 +	.dsp_info = VOP_REG(RK3066_WIN0_DSP_INFO, 0x0fff0fff, 0),
36077 +	.dsp_st = VOP_REG(RK3066_WIN0_DSP_ST, 0x1fff1fff, 0),
36078 +	.yrgb_mst = VOP_REG(RK3066_WIN0_YRGB_MST0, 0xffffffff, 0),
36079 +	.uv_mst = VOP_REG(RK3066_WIN0_CBR_MST0, 0xffffffff, 0),
36080 +	.yrgb_vir = VOP_REG(RK3066_WIN0_VIR, 0xffff, 0),
36081 +	.uv_vir = VOP_REG(RK3066_WIN0_VIR, 0x1fff, 16),
36082 +	.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 21),
36083 +	.alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 0)
36092 -	{ .base = 0x00, .phy = &rk3399_win01_data,
36097 +	.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 1),
36098 +	.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 7),
36099 +	.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 23),
36100 +	.act_info = VOP_REG(RK3066_WIN1_ACT_INFO, 0x1fff1fff, 0),
36101 +	.dsp_info = VOP_REG(RK3066_WIN1_DSP_INFO, 0x0fff0fff, 0),
36102 +	.dsp_st = VOP_REG(RK3066_WIN1_DSP_ST, 0x1fff1fff, 0),
36103 +	.yrgb_mst = VOP_REG(RK3066_WIN1_YRGB_MST, 0xffffffff, 0),
36104 +	.uv_mst = VOP_REG(RK3066_WIN1_CBR_MST, 0xffffffff, 0),
36105 +	.yrgb_vir = VOP_REG(RK3066_WIN1_VIR, 0xffff, 0),
36106 +	.uv_vir = VOP_REG(RK3066_WIN1_VIR, 0x1fff, 16),
36107 +	.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 22),
36108 +	.alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 1)
36114 +	.enable = VOP_REG(RK3066_SYS_CTRL1, 0x1, 2),
36115 +	.format = VOP_REG(RK3066_SYS_CTRL0, 0x7, 10),
36116 +	.rb_swap = VOP_REG(RK3066_SYS_CTRL0, 0x1, 27),
36117 +	.dsp_info = VOP_REG(RK3066_WIN2_DSP_INFO, 0x0fff0fff, 0),
36118 +	.dsp_st = VOP_REG(RK3066_WIN2_DSP_ST, 0x1fff1fff, 0),
36119 +	.yrgb_mst = VOP_REG(RK3066_WIN2_MST, 0xffffffff, 0),
36120 +	.yrgb_vir = VOP_REG(RK3066_WIN2_VIR, 0xffff, 0),
36121 +	.alpha_mode = VOP_REG(RK3066_DSP_CTRL0, 0x1, 23),
36122 +	.alpha_en = VOP_REG(RK3066_BLEND_CTRL, 0x1, 2)
36126 +	{ .base = 0x00, .phy = &rk3066_win0_data,
36128 -	{ .base = 0x40, .phy = &rk3368_win01_data,
36130 -	{ .base = 0x00, .phy = &rk3368_win23_data,
36131 +	{ .base = 0x00, .phy = &rk3066_win1_data,
36133 -	{ .base = 0x50, .phy = &rk3368_win23_data,
36134 +	{ .base = 0x00, .phy = &rk3066_win2_data,
36139 -	.rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
36140 -	.enable = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
36141 -	.win_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
36142 -	.format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
36143 -	.hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
36144 -	.hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
36145 -	.pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
36147 +	0,
36168 +	.line_flag_num[0] = VOP_REG(RK3066_INT_STATUS, 0xfff, 12),
36169 +	.status = VOP_REG(RK3066_INT_STATUS, 0xf, 0),
36170 +	.enable = VOP_REG(RK3066_INT_STATUS, 0xf, 4),
36171 +	.clear = VOP_REG(RK3066_INT_STATUS, 0xf, 8),
36175 -	{ .base = 0x00, .phy = &rk3368_win01_data,
36177 -	{ .base = 0x00, .phy = &rk3368_win23_data,
36180 +	.standby = VOP_REG(RK3066_SYS_CTRL0, 0x1, 1),
36181 +	.out_mode = VOP_REG(RK3066_DSP_CTRL0, 0xf, 0),
36182 +	.dsp_blank = VOP_REG(RK3066_DSP_CTRL1, 0x1, 24),
36183 +	.dclk_pol = VOP_REG(RK3066_DSP_CTRL0, 0x1, 7),
36184 +	.pin_pol = VOP_REG(RK3066_DSP_CTRL0, 0x7, 4),
36185 +	.dsp_layer_sel = VOP_REG(RK3066_DSP_CTRL0, 0x1, 8),
36186 +	.htotal_pw = VOP_REG(RK3066_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
36187 +	.hact_st_end = VOP_REG(RK3066_DSP_HACT_ST_END, 0x1fff1fff, 0),
36188 +	.vtotal_pw = VOP_REG(RK3066_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
36189 +	.vact_st_end = VOP_REG(RK3066_DSP_VACT_ST_END, 0x1fff1fff, 0),
36190 +	.cfg_done = VOP_REG(RK3066_REG_CFG_DONE, 0x1, 0),
36194 -	{ .base = 0x00, .phy = &rk3399_yuv2yuv_win01_data,
36195 -	  .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1)},
36196 -	{ .base = 0x60, .phy = &rk3399_yuv2yuv_win23_data },
36198 +	.soc_id = 0x3066,
36199 +	.vop_id = 0,
36235 -	{ .base = 0x00, .phy = &rk3288_win01_data,
36237 +	.scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
36238 +	.scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
36239 +	.scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
36240 +	.scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
36248 +	.enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0),
36249 +	.format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1),
36250 +	.rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12),
36251 +	.act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
36252 +	.dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
36253 +	.dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0),
36254 +	.yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0),
36255 +	.uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0),
36256 +	.yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0),
36257 +	.uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16),
36259 +	.alpha_pre_mul = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 2),
36260 +	.alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1),
36261 +	.alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0),
36262 +	.global_alpha_val = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0xff, 4),
36263 +	.key_color = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0xffffff, 0),
36264 +	.key_en = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0x1, 24),
36271 +	.enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0),
36272 +	.format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4),
36273 +	.rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12),
36274 +	.dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
36275 +	.dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0),
36276 +	.yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0),
36277 +	.yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0),
36279 +	.alpha_pre_mul = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 2),
36280 +	.alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
36281 +	.alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
36282 +	.global_alpha_val = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0xff, 4),
36283 +	.key_color = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0xffffff, 0),
36284 +	.key_en = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0x1, 24),
36288 +	{ .base = 0x00, .phy = &rk3366_lit_win0_data,
36290 -	{ .base = 0x40, .phy = &rk3288_win01_data,
36291 +	{ .base = 0x00, .phy = &rk3366_lit_win1_data,
36308 +	.line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
36309 +	.line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
36310 +	.status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
36311 +	.enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
36312 +	.clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
36316 -	.htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
36317 -	.hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
36318 -	.vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
36319 -	.vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
36320 -	.hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
36321 -	.vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
36325 +	.enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
36326 +	.format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
36327 +	.rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
36328 +	.dsp_info = VOP_REG(RK3126_WIN1_DSP_INFO, 0x0fff0fff, 0),
36329 +	.dsp_st = VOP_REG(RK3126_WIN1_DSP_ST, 0x1fff1fff, 0),
36330 +	.yrgb_mst = VOP_REG(RK3126_WIN1_MST, 0xffffffff, 0),
36331 +	.yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
36332 +	.alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
36333 +	.alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1),
36334 +	.alpha_pre_mul = VOP_REG(RK3036_DSP_CTRL0, 0x1, 29),
36338 -	.rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
36339 -	.hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
36340 -	.edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
36341 -	.mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
36342 -	.rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
36343 -	.hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
36344 -	.edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
36345 -	.mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
36346 -	.rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
36347 -	.hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
36348 -	.edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
36349 -	.mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
36351 +	{ .base = 0x00, .phy = &rk3036_win0_data,
36353 +	{ .base = 0x00, .phy = &rk3126_win1_data,
36358 -	.global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
36360 +	.soc_id = 0x3126,
36361 +	.vop_id = 0,
36372 -	.standby = VOP_REG_SYNC(RK3328_SYS_CTRL, 0x1, 22),
36373 -	.dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4),
36374 -	.dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3),
36375 -	.dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2),
36376 -	.pre_dither_down = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1),
36377 -	.dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
36378 -	.dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
36379 -	.out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
36380 -	.cfg_done = VOP_REG_SYNC(RK3328_REG_CFG_DONE, 0x1, 0),
36382 + * but RK3368 win2 register offset is 0xb0 and px30 is 0x190,
36383 + * so we set the PX30 VOPB win2 base = 0x190 - 0xb0 = 0xe0
36387 +	.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
36388 +	.axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
36389 +	.axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
36390 +	.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
36391 +	.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
36392 +	.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
36393 +	.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
36394 +	.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
36395 +	.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
36396 +	.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
36397 +	.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
36398 +	.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
36399 +	.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
36400 +	.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
36401 +	.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
36402 +	.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
36403 +	.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
36404 +	.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
36405 +	.hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
36406 +	.hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
36407 +	.lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
36408 +	.lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
36409 +	.mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
36410 +	.mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
36411 +	.mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
36412 +	.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
36413 +	.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
36414 +	.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
36415 +	.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
36416 +	.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
36417 +	.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
36418 +	.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
36419 +	.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
36420 +	.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
36421 +	.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
36422 +	.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
36423 +	.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
36424 +	.dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
36425 +	.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
36426 +	.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
36427 +	.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
36429 +	.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
36430 +	.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
36431 +	.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
36432 +	.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
36433 +	.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
36434 +	.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
36435 +	.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
36436 +	.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
36437 +	.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
36438 +	.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
36439 +	.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
36440 +	.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
36442 +	.afbdc_en = VOP_REG(PX30_AFBCD0_CTRL, 0x1, 0),
36443 +	.afbdc_format = VOP_REG(PX30_AFBCD0_CTRL, 0x1f, 4),
36444 +	.afbdc_pic_vir_width = VOP_REG(PX30_AFBCD0_CTRL, 0xffff, 16),
36445 +	.afbdc_hdr_ptr = VOP_REG(PX30_AFBCD0_HDR_PTR, 0xffffffff, 0),
36446 +	.afbdc_pic_size = VOP_REG(PX30_AFBCD0_PIC_SIZE, 0xffffffff, 0),
36447 +	.afbdc_pic_offset = VOP_REG(PX30_AFBCD0_PIC_OFFSET, 0xffffffff, 0),
36448 +	.afbdc_axi_ctrl =  VOP_REG(PX30_AFBCD0_AXI_CTRL, 0xffffffff, 0),
36450 +	.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
36451 +	.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
36452 +	.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
36453 +	.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
36454 +	.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
36455 +	.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
36456 +	.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
36457 +	.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
36458 +	.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
36459 +	.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
36460 +	.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
36462 +				      0xffffffff, 0),
36468 +	.gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
36469 +	.enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
36470 +	.format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
36471 +	.rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
36472 +	.dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
36473 +	.dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
36474 +	.yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
36475 +	.yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
36476 +	.alpha_pre_mul = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0x1, 2),
36477 +	.alpha_mode = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0x1, 1),
36478 +	.alpha_en = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0x1, 0),
36479 +	.global_alpha_val = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 4),
36480 +	.channel = VOP_REG(RK3368_WIN2_CTRL1, 0xf, 8),
36486 -	.line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
36487 -	.line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
36488 -	.status = VOP_REG_MASK_SYNC(RK3328_INTR_STATUS0, 0xffff, 0),
36489 -	.enable = VOP_REG_MASK_SYNC(RK3328_INTR_EN0, 0xffff, 0),
36490 -	.clear = VOP_REG_MASK_SYNC(RK3328_INTR_CLEAR0, 0xffff, 0),
36492 +	{ .base = 0x00, .phy = &rk3366_lit_win0_data,
36494 +	{ .base = 0x00, .phy = &rk3366_lit_win1_data,
36497 +	{ .base = 0xe0, .phy = &px30_win23_data,
36504 -	{ .base = 0xd0, .phy = &rk3368_win01_data,
36507 +	{ .base = 0x00, .phy = &rk3366_lit_win1_data,
36509 -	{ .base = 0x1d0, .phy = &rk3368_win01_data,
36514 +	.grf_dclk_inv = VOP_REG(PX30_GRF_PD_VO_CON1, 0x1, 4),
36518 +	.soc_id = 0x3326,
36531 +	.soc_id = 0x3326,
36532 +	.vop_id = 0,
36544 +	.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
36545 +	.axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
36546 +	.axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
36547 +	.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
36548 +	.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
36549 +	.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
36550 +	.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
36551 +	.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
36552 +	.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
36553 +	.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
36554 +	.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
36555 +	.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 3),
36556 +	.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
36557 +	.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
36558 +	.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
36559 +	.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
36560 +	.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
36561 +	.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
36562 +	.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
36563 +	.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
36564 +	.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
36565 +	.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
36566 +	.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
36567 +	.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
36568 +	.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
36569 +	.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
36570 +	.dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
36571 +	.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
36572 +	.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
36573 +	.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
36575 +	.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
36576 +	.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
36577 +	.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
36578 +	.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
36579 +	.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
36580 +	.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
36581 +	.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
36582 +	.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3f, 0),
36583 +	.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 8),
36584 +	.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 16),
36585 +	.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0xff, 0),
36586 +	.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0xff, 8),
36588 +	.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
36589 +	.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
36590 +	.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
36591 +	.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
36592 +	.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
36593 +	.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
36594 +	.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
36595 +	.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
36596 +	.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
36597 +	.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
36598 +	.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
36600 +				      0xffffffff, 0),
36610 +	0,
36611 +	0,
36614 +	0,
36621 +	.line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
36622 +	.line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
36623 +	.status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
36624 +	.enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
36625 +	.clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
36629 +	.soc_id = 0x3308,
36630 +	.vop_id = 0,
36641 +	.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
36642 +	.axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
36643 +	.axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
36644 +	.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
36645 +	.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
36646 +	.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
36647 +	.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
36648 +	.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
36649 +	.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
36650 +	.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
36651 +	.global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
36652 +	.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
36653 +	.dsp_layer_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xff, 22),
36654 +	.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
36655 +	.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
36656 +	.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
36657 +	.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
36658 +	.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
36659 +	.hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
36660 +	.hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
36661 +	.lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
36662 +	.lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
36663 +	.mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
36664 +	.mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
36665 +	.mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
36666 +	.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
36667 +	.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
36668 +	.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
36669 +	.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
36670 +	.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
36671 +	.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
36672 +	.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
36673 +	.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
36674 +	.yuv_clip = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 4),
36675 +	.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
36676 +	.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
36677 +	.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
36678 +	.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
36679 +	.dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
36680 +	.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
36681 +	.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
36682 +	.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
36684 +	.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
36685 +	.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
36686 +	.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
36687 +	.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
36688 +	.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
36689 +	.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
36690 +	.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
36691 +	.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
36692 +	.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
36693 +	.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
36694 +	.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
36695 +	.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
36697 +	.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
36698 +	.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
36699 +	.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
36700 +	.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
36701 +	.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
36702 +	.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
36703 +	.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
36704 +	.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
36705 +	.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
36706 +	.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
36707 +	.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
36709 +				      0xffffffff, 0),
36710 +	.bt1120_yc_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 30),
36711 +	.bt1120_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 31),
36715 +	{ .base = 0x00, .phy = &rk3366_lit_win0_data,
36717 -	{ .base = 0x2d0, .phy = &rk3368_win01_data,
36720 +	{ .base = 0xe0, .phy = &px30_win23_data,
36727 +	.grf_dclk_inv = VOP_REG(RV1126_GRF_IOFUNC_CON3, 0x1, 2),
36731 +	.soc_id = 0x1126,
36732 +	.vop_id = 0,
36733 +	.version = VOP_VERSION(2, 0xb),
36744 +	.standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
36745 +	.axi_outstanding_max_num = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1f, 16),
36746 +	.axi_max_outstanding_en = VOP_REG(RK3366_LIT_SYS_CTRL1, 0x1, 12),
36747 +	.htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
36748 +	.hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
36749 +	.vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
36750 +	.vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
36751 +	.vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
36752 +	.vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
36753 +	.dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
36754 +	.auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
36755 +	.overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
36756 +	.core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
36757 +	.dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
36758 +	.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
36759 +	.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
36760 +	.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
36761 +	.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
36762 +	.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
36763 +	.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
36764 +	.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
36765 +	.yuv_clip = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 4),
36766 +	.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
36767 +	.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
36768 +	.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
36769 +	.out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
36770 +	.dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
36771 +	.cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
36773 +	.bcsh_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 0),
36774 +	.bcsh_r2y_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 1),
36775 +	.bcsh_out_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 2),
36776 +	.bcsh_y2r_csc_mode = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x3, 4),
36777 +	.bcsh_y2r_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 6),
36778 +	.bcsh_r2y_en = VOP_REG(RK3366_LIT_BCSH_CTRL, 0x1, 7),
36779 +	.bcsh_color_bar = VOP_REG(RK3366_LIT_BCSH_COL_BAR, 0xffffff, 0),
36780 +	.bcsh_brightness = VOP_REG(RK3366_LIT_BCSH_BCS, 0xff, 0),
36781 +	.bcsh_contrast = VOP_REG(RK3366_LIT_BCSH_BCS, 0x1ff, 8),
36782 +	.bcsh_sat_con = VOP_REG(RK3366_LIT_BCSH_BCS, 0x3ff, 20),
36783 +	.bcsh_sin_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 0),
36784 +	.bcsh_cos_hue = VOP_REG(RK3366_LIT_BCSH_H, 0x1ff, 16),
36786 +	.mcu_pix_total = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 0),
36787 +	.mcu_cs_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 6),
36788 +	.mcu_cs_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 10),
36789 +	.mcu_rw_pst = VOP_REG(RK3366_LIT_MCU_CTRL, 0xf, 16),
36790 +	.mcu_rw_pend = VOP_REG(RK3366_LIT_MCU_CTRL, 0x3f, 20),
36791 +	.mcu_clk_sel = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 26),
36792 +	.mcu_hold_mode = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 27),
36793 +	.mcu_frame_st = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 28),
36794 +	.mcu_rs = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 29),
36795 +	.mcu_bypass = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 30),
36796 +	.mcu_type = VOP_REG(RK3366_LIT_MCU_CTRL, 0x1, 31),
36798 +				      0xffffffff, 0),
36799 +	.bt1120_yc_swap = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 30),
36800 +	.bt1120_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 31),
36801 +	.bt656_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 6),
36806 +	{ .base = 0x00, .phy = &rk3366_lit_win1_data,
36821 +	.grf_dclk_inv = VOP_REG(RV1106_VENC_GRF_VOP_IO_WRAPPER, 0x1, 2),
36825 +	.soc_id = 0x1106,
36826 +	.vop_id = 0,
36827 +	.version = VOP_VERSION(2, 0xc),
36910  #define RK3288_DSP_VACT_ST_END			0x0194
36911  #define RK3288_DSP_VS_ST_END_F1			0x0198
36912  #define RK3288_DSP_VACT_ST_END_F1		0x019c
36914 +#define RK3288_BCSH_COLOR_BAR			0x01b0
36915 +#define RK3288_BCSH_BCS				0x01b4
36916 +#define RK3288_BCSH_H				0x01b8
36917 +#define RK3288_GRF_SOC_CON15			0x03a4
36922  #define RK3368_CABC_GAMMA_LUT_ADDR		0x1800
36923  #define RK3368_MCU_BYPASS_WPORT			0x2200
36924  #define RK3368_MCU_BYPASS_RPORT			0x2300
36925 +#define RK3368_GRF_SOC_CON6			0x0418
36928  #define RK3366_REG_CFG_DONE			0x0000
36930  #define RK3399_YUV2YUV_WIN			0x02c0
36931  #define RK3399_YUV2YUV_POST			0x02c4
36932  #define RK3399_AUTO_GATING_EN			0x02cc
36933 +#define RK3399_DBG_POST_REG1			0x036c
36934  #define RK3399_WIN0_CSC_COE			0x03a0
36935  #define RK3399_WIN1_CSC_COE			0x03c0
36936  #define RK3399_WIN2_CSC_COE			0x03e0
36938  #define RK3328_DBG_POST_RESERVED		0x000006ec
36939  #define RK3328_DBG_DATAO			0x000006f0
36940  #define RK3328_DBG_DATAO_2			0x000006f4
36941 +#define RK3328_SDR2HDR_CTRL			0x00000700
36942 +#define RK3328_SDR2HDR_EOTF_OETF_Y0		0x00000704
36943 +#define RK3328_SDR2HDR_EOTF_OETF_Y1		0x00000710
36944 +#define RK3328_SDR2HDR_OETF_DX_DXPOW1		0x00000810
36945 +#define RK3328_SDR2HDR_OETF_XN1			0x00000910
36947 +#define RK3328_HDR2DR_CTRL			0x00000a10
36948 +#define RK3328_HDR2DR_SRC_RANGE			0x00000a14
36949 +#define RK3328_HDR2DR_NORMFACEETF		0x00000a18
36950 +#define RK3328_HDR2DR_DST_RANGE			0x00000a20
36951 +#define RK3328_HDR2DR_NORMFACGAMMA		0x00000a24
36952 +#define RK3328_HDR2SDR_EETF_OETF_Y0		0x00000a28
36953 +#define RK3328_HDR2DR_SAT_Y0			0x00000a2C
36954 +#define RK3328_HDR2SDR_EETF_OETF_Y1		0x00000a30
36955 +#define RK3328_HDR2DR_SAT_Y1			0x00000ab0
36958  #define RK3328_SDR2HDR_CTRL			0x00000700
36960  #define RK3036_SYS_CTRL			0x00
36961  #define RK3036_DSP_CTRL0		0x04
36962  #define RK3036_DSP_CTRL1		0x08
36963 +#define RK3036_INT_SCALER		0x0c
36964  #define RK3036_INT_STATUS		0x10
36965  #define RK3036_ALPHA_CTRL		0x14
36966  #define RK3036_WIN0_COLOR_KEY		0x18
36968  #define RK3036_HWC_LUT_ADDR		0x800
36972 -#define RK3126_WIN1_MST			0x4c
36973 -#define RK3126_WIN1_DSP_INFO		0x50
36974 -#define RK3126_WIN1_DSP_ST		0x54
36978 -#define PX30_REG_CFG_DONE			0x00000
36979 -#define PX30_VERSION				0x00004
36980 -#define PX30_DSP_BG				0x00008
36981 -#define PX30_MCU_CTRL				0x0000c
36982 -#define PX30_SYS_CTRL0				0x00010
36983 -#define PX30_SYS_CTRL1				0x00014
36984 -#define PX30_SYS_CTRL2				0x00018
36985 -#define PX30_DSP_CTRL0				0x00020
36986 -#define PX30_DSP_CTRL2				0x00028
36987 -#define PX30_VOP_STATUS				0x0002c
36988 -#define PX30_LINE_FLAG				0x00030
36989 -#define PX30_INTR_EN				0x00034
36990 -#define PX30_INTR_CLEAR				0x00038
36991 -#define PX30_INTR_STATUS			0x0003c
36992 -#define PX30_WIN0_CTRL0				0x00050
36993 -#define PX30_WIN0_CTRL1				0x00054
36994 -#define PX30_WIN0_COLOR_KEY			0x00058
36995 -#define PX30_WIN0_VIR				0x0005c
36996 -#define PX30_WIN0_YRGB_MST0			0x00060
36997 -#define PX30_WIN0_CBR_MST0			0x00064
36998 -#define PX30_WIN0_ACT_INFO			0x00068
36999 -#define PX30_WIN0_DSP_INFO			0x0006c
37000 -#define PX30_WIN0_DSP_ST			0x00070
37001 -#define PX30_WIN0_SCL_FACTOR_YRGB		0x00074
37002 -#define PX30_WIN0_SCL_FACTOR_CBR		0x00078
37003 -#define PX30_WIN0_SCL_OFFSET			0x0007c
37004 -#define PX30_WIN0_ALPHA_CTRL			0x00080
37005 -#define PX30_WIN1_CTRL0				0x00090
37006 -#define PX30_WIN1_CTRL1				0x00094
37007 -#define PX30_WIN1_VIR				0x00098
37008 -#define PX30_WIN1_MST				0x000a0
37009 -#define PX30_WIN1_DSP_INFO			0x000a4
37010 -#define PX30_WIN1_DSP_ST			0x000a8
37011 -#define PX30_WIN1_COLOR_KEY			0x000ac
37012 -#define PX30_WIN1_ALPHA_CTRL			0x000bc
37013 -#define PX30_HWC_CTRL0				0x000e0
37014 -#define PX30_HWC_CTRL1				0x000e4
37015 -#define PX30_HWC_MST				0x000e8
37016 -#define PX30_HWC_DSP_ST				0x000ec
37017 -#define PX30_HWC_ALPHA_CTRL			0x000f0
37018 -#define PX30_DSP_HTOTAL_HS_END			0x00100
37019 -#define PX30_DSP_HACT_ST_END			0x00104
37020 -#define PX30_DSP_VTOTAL_VS_END			0x00108
37021 -#define PX30_DSP_VACT_ST_END			0x0010c
37022 -#define PX30_DSP_VS_ST_END_F1			0x00110
37023 -#define PX30_DSP_VACT_ST_END_F1			0x00114
37024 -#define PX30_BCSH_CTRL				0x00160
37025 -#define PX30_BCSH_COL_BAR			0x00164
37026 -#define PX30_BCSH_BCS				0x00168
37027 -#define PX30_BCSH_H				0x0016c
37028 -#define PX30_FRC_LOWER01_0			0x00170
37029 -#define PX30_FRC_LOWER01_1			0x00174
37030 -#define PX30_FRC_LOWER10_0			0x00178
37031 -#define PX30_FRC_LOWER10_1			0x0017c
37032 -#define PX30_FRC_LOWER11_0			0x00180
37033 -#define PX30_FRC_LOWER11_1			0x00184
37034 -#define PX30_MCU_RW_BYPASS_PORT			0x0018c
37035 -#define PX30_WIN2_CTRL0				0x00190
37036 -#define PX30_WIN2_CTRL1				0x00194
37037 -#define PX30_WIN2_VIR0_1			0x00198
37038 -#define PX30_WIN2_VIR2_3			0x0019c
37039 -#define PX30_WIN2_MST0				0x001a0
37040 -#define PX30_WIN2_DSP_INFO0			0x001a4
37041 -#define PX30_WIN2_DSP_ST0			0x001a8
37042 -#define PX30_WIN2_COLOR_KEY			0x001ac
37043 -#define PX30_WIN2_ALPHA_CTRL			0x001bc
37044 -#define PX30_BLANKING_VALUE			0x001f4
37045 -#define PX30_FLAG_REG_FRM_VALID			0x001f8
37046 -#define PX30_FLAG_REG				0x001fc
37047 -#define PX30_HWC_LUT_ADDR			0x00600
37048 -#define PX30_GAMMA_LUT_ADDR			0x00a00
37052 -#define RK3188_SYS_CTRL			0x00
37053 -#define RK3188_DSP_CTRL0		0x04
37054 -#define RK3188_DSP_CTRL1		0x08
37055 -#define RK3188_INT_STATUS		0x10
37056 -#define RK3188_WIN0_YRGB_MST0		0x20
37057 -#define RK3188_WIN0_CBR_MST0		0x24
37058 -#define RK3188_WIN0_YRGB_MST1		0x28
37059 -#define RK3188_WIN0_CBR_MST1		0x2c
37060 -#define RK3188_WIN_VIR			0x30
37061 -#define RK3188_WIN0_ACT_INFO		0x34
37062 -#define RK3188_WIN0_DSP_INFO		0x38
37063 -#define RK3188_WIN0_DSP_ST		0x3c
37064 -#define RK3188_WIN0_SCL_FACTOR_YRGB	0x40
37065 -#define RK3188_WIN0_SCL_FACTOR_CBR	0x44
37066 -#define RK3188_WIN1_MST			0x4c
37067 -#define RK3188_WIN1_DSP_INFO		0x50
37068 -#define RK3188_WIN1_DSP_ST		0x54
37069 -#define RK3188_DSP_HTOTAL_HS_END	0x6c
37070 -#define RK3188_DSP_HACT_ST_END		0x70
37071 -#define RK3188_DSP_VTOTAL_VS_END	0x74
37072 -#define RK3188_DSP_VACT_ST_END		0x78
37073 -#define RK3188_REG_CFG_DONE		0x90
37077  #define RK3066_SYS_CTRL0		0x00
37078  #define RK3066_SYS_CTRL1		0x04
37079  #define RK3066_DSP_CTRL0		0x08
37081  #define RK3066_MCU_BYPASS_RPORT		0x200
37082  #define RK3066_WIN2_LUT_ADDR		0x400
37083  #define RK3066_DSP_LUT_ADDR		0x800
37087 +#define RK3366_LIT_REG_CFG_DONE			0x00000
37088 +#define RK3366_LIT_VERSION			0x00004
37089 +#define RK3366_LIT_DSP_BG			0x00008
37090 +#define RK3366_LIT_MCU_CTRL			0x0000c
37091 +#define RK3366_LIT_SYS_CTRL0			0x00010
37092 +#define RK3366_LIT_SYS_CTRL1			0x00014
37093 +#define RK3366_LIT_SYS_CTRL2			0x00018
37094 +#define RK3366_LIT_DSP_CTRL0			0x00020
37095 +#define RK3366_LIT_DSP_CTRL2			0x00028
37096 +#define RK3366_LIT_VOP_STATUS			0x0002c
37097 +#define RK3366_LIT_LINE_FLAG			0x00030
37098 +#define RK3366_LIT_INTR_EN			0x00034
37099 +#define RK3366_LIT_INTR_CLEAR			0x00038
37100 +#define RK3366_LIT_INTR_STATUS			0x0003c
37101 +#define RK3366_LIT_WIN0_CTRL0			0x00050
37102 +#define RK3366_LIT_WIN0_CTRL1			0x00054
37103 +#define RK3366_LIT_WIN0_COLOR_KEY		0x00058
37104 +#define RK3366_LIT_WIN0_VIR			0x0005c
37105 +#define RK3366_LIT_WIN0_YRGB_MST0		0x00060
37106 +#define RK3366_LIT_WIN0_CBR_MST0		0x00064
37107 +#define RK3366_LIT_WIN0_ACT_INFO		0x00068
37108 +#define RK3366_LIT_WIN0_DSP_INFO		0x0006c
37109 +#define RK3366_LIT_WIN0_DSP_ST			0x00070
37110 +#define RK3366_LIT_WIN0_SCL_FACTOR_YRGB		0x00074
37111 +#define RK3366_LIT_WIN0_SCL_FACTOR_CBR		0x00078
37112 +#define RK3366_LIT_WIN0_SCL_OFFSET		0x0007c
37113 +#define RK3366_LIT_WIN0_ALPHA_CTRL		0x00080
37114 +#define RK3366_LIT_WIN1_CTRL0			0x00090
37115 +#define RK3366_LIT_WIN1_CTRL1			0x00094
37116 +#define RK3366_LIT_WIN1_VIR			0x00098
37117 +#define RK3366_LIT_WIN1_MST			0x000a0
37118 +#define RK3366_LIT_WIN1_DSP_INFO		0x000a4
37119 +#define RK3366_LIT_WIN1_DSP_ST			0x000a8
37120 +#define RK3366_LIT_WIN1_COLOR_KEY		0x000ac
37121 +#define RK3366_LIT_WIN1_ALPHA_CTRL		0x000bc
37122 +#define RK3366_LIT_HWC_CTRL0			0x000e0
37123 +#define RK3366_LIT_HWC_CTRL1			0x000e4
37124 +#define RK3366_LIT_HWC_MST			0x000e8
37125 +#define RK3366_LIT_HWC_DSP_ST			0x000ec
37126 +#define RK3366_LIT_HWC_ALPHA_CTRL		0x000f0
37127 +#define RK3366_LIT_DSP_HTOTAL_HS_END		0x00100
37128 +#define RK3366_LIT_DSP_HACT_ST_END		0x00104
37129 +#define RK3366_LIT_DSP_VTOTAL_VS_END		0x00108
37130 +#define RK3366_LIT_DSP_VACT_ST_END		0x0010c
37131 +#define RK3366_LIT_DSP_VS_ST_END_F1		0x00110
37132 +#define RK3366_LIT_DSP_VACT_ST_END_F1		0x00114
37133 +#define RK3366_LIT_BCSH_CTRL			0x00160
37134 +#define RK3366_LIT_BCSH_COL_BAR			0x00164
37135 +#define RK3366_LIT_BCSH_BCS			0x00168
37136 +#define RK3366_LIT_BCSH_H			0x0016c
37137 +#define RK3366_LIT_FRC_LOWER01_0		0x00170
37138 +#define RK3366_LIT_FRC_LOWER01_1		0x00174
37139 +#define RK3366_LIT_FRC_LOWER10_0		0x00178
37140 +#define RK3366_LIT_FRC_LOWER10_1		0x0017c
37141 +#define RK3366_LIT_FRC_LOWER11_0		0x00180
37142 +#define RK3366_LIT_FRC_LOWER11_1		0x00184
37143 +#define RK3366_LIT_MCU_RW_BYPASS_PORT		0x0018c
37144 +#define RK3366_LIT_DBG_REG_000			0x00190
37145 +#define RK3366_LIT_BLANKING_VALUE		0x001f4
37146 +#define RK3366_LIT_FLAG_REG_FRM_VALID		0x001f8
37147 +#define RK3366_LIT_FLAG_REG			0x001fc
37148 +#define RK3366_LIT_HWC_LUT_ADDR			0x00600
37149 +#define RK3366_LIT_GAMMA_LUT_ADDR		0x00a00
37153 +#define RK3126_WIN1_MST				0x0004c
37154 +#define RK3126_WIN1_DSP_INFO			0x00050
37155 +#define RK3126_WIN1_DSP_ST			0x00054
37159 +#define PX30_CABC_CTRL0				0x00200
37160 +#define PX30_CABC_CTRL1				0x00204
37161 +#define PX30_CABC_CTRL2				0x00208
37162 +#define PX30_CABC_CTRL3				0x0020c
37163 +#define PX30_CABC_GAUSS_LINE0_0			0x00210
37164 +#define PX30_CABC_GAUSS_LINE0_1			0x00214
37165 +#define PX30_CABC_GAUSS_LINE1_0			0x00218
37166 +#define PX30_CABC_GAUSS_LINE1_1			0x0021c
37167 +#define PX30_CABC_GAUSS_LINE2_0			0x00220
37168 +#define PX30_CABC_GAUSS_LINE2_1			0x00224
37169 +#define PX30_AFBCD0_CTRL			0x00240
37170 +#define PX30_AFBCD0_HDR_PTR			0x00244
37171 +#define PX30_AFBCD0_PIC_SIZE			0x00248
37172 +#define PX30_AFBCD0_PIC_OFFSET			0x0024c
37173 +#define PX30_AFBCD0_AXI_CTRL			0x00250
37174 +#define PX30_GRF_PD_VO_CON1			0x00438
37177 +#define RV1106_VENC_GRF_VOP_IO_WRAPPER		0x1000c
37179 +#define RV1126_GRF_IOFUNC_CON3			0x1026c
37183 +#define RK3568_GRF_VO_CON1			0x0364
37185 +#define RK3568_REG_CFG_DONE			0x000
37188 +#define RK3568_VERSION_INFO			0x004
37189 +#define RK3568_SYS_AUTO_GATING_CTRL		0x008
37190 +#define RK3568_SYS_AXI_LUT_CTRL			0x024
37191 +#define RK3568_DSP_IF_EN			0x028
37192 +#define RK3568_DSP_IF_CTRL			0x02c
37193 +#define RK3568_DSP_IF_POL			0x030
37194 +#define RK3568_SYS_PD_CTRL			0x034
37195 +#define RK3568_WB_CTRL				0x40
37196 +#define RK3568_WB_XSCAL_FACTOR			0x44
37197 +#define RK3568_WB_YRGB_MST			0x48
37198 +#define RK3568_WB_CBR_MST			0x4C
37199 +#define RK3568_OTP_WIN_EN			0x50
37200 +#define RK3568_LUT_PORT_SEL			0x58
37201 +#define RK3568_SYS_STATUS0			0x60
37202 +#define RK3568_SYS_STATUS1			0x64
37203 +#define RK3568_SYS_STATUS2			0x68
37204 +#define RK3568_SYS_STATUS3			0x6C
37205 +#define RK3568_VP0_LINE_FLAG			0x70
37206 +#define RK3568_VP1_LINE_FLAG			0x74
37207 +#define RK3568_VP2_LINE_FLAG			0x78
37208 +#define RK3588_VP3_LINE_FLAG			0x7C
37209 +#define RK3568_SYS0_INT_EN			0x80
37210 +#define RK3568_SYS0_INT_CLR			0x84
37211 +#define RK3568_SYS0_INT_STATUS			0x88
37212 +#define RK3568_SYS1_INT_EN			0x90
37213 +#define RK3568_SYS1_INT_CLR			0x94
37214 +#define RK3568_SYS1_INT_STATUS			0x98
37215 +#define RK3568_VP0_INT_EN			0xA0
37216 +#define RK3568_VP0_INT_CLR			0xA4
37217 +#define RK3568_VP0_INT_STATUS			0xA8
37218 +#define RK3568_VP0_INT_RAW_STATUS		0xAC
37219 +#define RK3568_VP1_INT_EN			0xB0
37220 +#define RK3568_VP1_INT_CLR			0xB4
37221 +#define RK3568_VP1_INT_STATUS			0xB8
37222 +#define RK3568_VP1_INT_RAW_STATUS		0xBC
37223 +#define RK3568_VP2_INT_EN			0xC0
37224 +#define RK3568_VP2_INT_CLR			0xC4
37225 +#define RK3568_VP2_INT_STATUS			0xC8
37226 +#define RK3568_VP2_INT_RAW_STATUS		0xCC
37227 +#define RK3588_VP3_INT_EN			0xD0
37228 +#define RK3588_VP3_INT_CLR			0xD4
37229 +#define RK3588_VP3_INT_STATUS			0xD8
37231 +#define RK3588_DSC_8K_SYS_CTRL			0x200
37232 +#define RK3588_DSC_8K_RST			0x204
37233 +#define RK3588_DSC_8K_CFG_DONE			0x208
37234 +#define RK3588_DSC_8K_INIT_DLY			0x20C
37235 +#define RK3588_DSC_8K_HTOTAL_HS_END		0x210
37236 +#define RK3588_DSC_8K_HACT_ST_END		0x214
37237 +#define RK3588_DSC_8K_VTOTAL_VS_END		0x218
37238 +#define RK3588_DSC_8K_VACT_ST_END		0x21C
37239 +#define RK3588_DSC_8K_STATUS			0x220
37240 +#define RK3588_DSC_4K_SYS_CTRL			0x230
37241 +#define RK3588_DSC_4K_RST			0x234
37242 +#define RK3588_DSC_4K_CFG_DONE			0x238
37243 +#define RK3588_DSC_4K_INIT_DLY			0x23C
37244 +#define RK3588_DSC_4K_HTOTAL_HS_END		0x240
37245 +#define RK3588_DSC_4K_HACT_ST_END		0x244
37246 +#define RK3588_DSC_4K_VTOTAL_VS_END		0x248
37247 +#define RK3588_DSC_4K_VACT_ST_END		0x24C
37248 +#define RK3588_DSC_4K_STATUS			0x250
37251 +#define RK3568_VP0_DSP_CTRL				0xC00
37252 +#define RK3568_VP0_DUAL_CHANNEL_CTRL			0xC04
37253 +#define RK3568_VP0_COLOR_BAR_CTRL			0xC08
37254 +#define RK3568_VP0_CLK_CTRL				0xC0C
37255 +#define RK3568_VP0_3D_LUT_CTRL				0xC10
37256 +#define RK3568_VP0_3D_LUT_MST				0xC20
37257 +#define RK3568_VP0_DSP_BG				0xC2C
37258 +#define RK3568_VP0_PRE_SCAN_HTIMING			0xC30
37259 +#define RK3568_VP0_POST_DSP_HACT_INFO			0xC34
37260 +#define RK3568_VP0_POST_DSP_VACT_INFO			0xC38
37261 +#define RK3568_VP0_POST_SCL_FACTOR_YRGB			0xC3C
37262 +#define RK3568_VP0_POST_SCL_CTRL			0xC40
37263 +#define RK3568_VP0_POST_DSP_VACT_INFO_F1		0xC44
37264 +#define RK3568_VP0_DSP_HTOTAL_HS_END			0xC48
37265 +#define RK3568_VP0_DSP_HACT_ST_END			0xC4C
37266 +#define RK3568_VP0_DSP_VTOTAL_VS_END			0xC50
37267 +#define RK3568_VP0_DSP_VACT_ST_END			0xC54
37268 +#define RK3568_VP0_DSP_VS_ST_END_F1			0xC58
37269 +#define RK3568_VP0_DSP_VACT_ST_END_F1			0xC5C
37270 +#define RK3568_VP0_BCSH_CTRL				0xC60
37271 +#define RK3568_VP0_BCSH_BCS				0xC64
37272 +#define RK3568_VP0_BCSH_H				0xC68
37273 +#define RK3568_VP0_BCSH_COLOR_BAR			0xC6C
37275 +#define RK3568_VP1_DSP_CTRL				0xD00
37276 +#define RK3568_VP1_DUAL_CHANNEL_CTRL			0xD04
37277 +#define RK3568_VP1_COLOR_BAR_CTRL			0xD08
37278 +#define RK3568_VP1_CLK_CTRL				0xD0C
37279 +#define RK3588_VP1_3D_LUT_CTRL				0xD10
37280 +#define RK3588_VP1_3D_LUT_MST				0xD20
37281 +#define RK3568_VP1_DSP_BG				0xD2C
37282 +#define RK3568_VP1_PRE_SCAN_HTIMING			0xD30
37283 +#define RK3568_VP1_POST_DSP_HACT_INFO			0xD34
37284 +#define RK3568_VP1_POST_DSP_VACT_INFO			0xD38
37285 +#define RK3568_VP1_POST_SCL_FACTOR_YRGB			0xD3C
37286 +#define RK3568_VP1_POST_SCL_CTRL			0xD40
37287 +#define RK3568_VP1_DSP_HACT_INFO			0xD34
37288 +#define RK3568_VP1_DSP_VACT_INFO			0xD38
37289 +#define RK3568_VP1_POST_DSP_VACT_INFO_F1		0xD44
37290 +#define RK3568_VP1_DSP_HTOTAL_HS_END			0xD48
37291 +#define RK3568_VP1_DSP_HACT_ST_END			0xD4C
37292 +#define RK3568_VP1_DSP_VTOTAL_VS_END			0xD50
37293 +#define RK3568_VP1_DSP_VACT_ST_END			0xD54
37294 +#define RK3568_VP1_DSP_VS_ST_END_F1			0xD58
37295 +#define RK3568_VP1_DSP_VACT_ST_END_F1			0xD5C
37296 +#define RK3568_VP1_BCSH_CTRL				0xD60
37297 +#define RK3568_VP1_BCSH_BCS				0xD64
37298 +#define RK3568_VP1_BCSH_H				0xD68
37299 +#define RK3568_VP1_BCSH_COLOR_BAR			0xD6C
37301 +#define RK3568_VP2_DSP_CTRL				0xE00
37302 +#define RK3568_VP2_DUAL_CHANNEL_CTRL			0xE04
37303 +#define RK3568_VP2_COLOR_BAR_CTRL			0xE08
37304 +#define RK3568_VP2_CLK_CTRL				0xE0C
37305 +#define RK3588_VP2_3D_LUT_CTRL				0xE10
37306 +#define RK3588_VP2_3D_LUT_MST				0xE20
37307 +#define RK3568_VP2_DSP_BG				0xE2C
37308 +#define RK3568_VP2_PRE_SCAN_HTIMING			0xE30
37309 +#define RK3568_VP2_POST_DSP_HACT_INFO			0xE34
37310 +#define RK3568_VP2_POST_DSP_VACT_INFO			0xE38
37311 +#define RK3568_VP2_POST_SCL_FACTOR_YRGB			0xE3C
37312 +#define RK3568_VP2_POST_SCL_CTRL			0xE40
37313 +#define RK3568_VP2_DSP_HACT_INFO			0xE34
37314 +#define RK3568_VP2_DSP_VACT_INFO			0xE38
37315 +#define RK3568_VP2_POST_DSP_VACT_INFO_F1		0xE44
37316 +#define RK3568_VP2_DSP_HTOTAL_HS_END			0xE48
37317 +#define RK3568_VP2_DSP_HACT_ST_END			0xE4C
37318 +#define RK3568_VP2_DSP_VTOTAL_VS_END			0xE50
37319 +#define RK3568_VP2_DSP_VACT_ST_END			0xE54
37320 +#define RK3568_VP2_DSP_VS_ST_END_F1			0xE58
37321 +#define RK3568_VP2_DSP_VACT_ST_END_F1			0xE5C
37322 +#define RK3568_VP2_BCSH_CTRL				0xE60
37323 +#define RK3568_VP2_BCSH_BCS				0xE64
37324 +#define RK3568_VP2_BCSH_H				0xE68
37325 +#define RK3568_VP2_BCSH_COLOR_BAR			0xE6C
37327 +#define RK3588_VP3_DSP_CTRL				0xF00
37328 +#define RK3588_VP3_DUAL_CHANNEL_CTRL			0xF04
37329 +#define RK3588_VP3_COLOR_BAR_CTRL			0xF08
37330 +#define RK3568_VP3_CLK_CTRL				0xF0C
37331 +#define RK3588_VP3_DSP_BG				0xF2C
37332 +#define RK3588_VP3_PRE_SCAN_HTIMING			0xF30
37333 +#define RK3588_VP3_POST_DSP_HACT_INFO			0xF34
37334 +#define RK3588_VP3_POST_DSP_VACT_INFO			0xF38
37335 +#define RK3588_VP3_POST_SCL_FACTOR_YRGB			0xF3C
37336 +#define RK3588_VP3_POST_SCL_CTRL			0xF40
37337 +#define RK3588_VP3_DSP_HACT_INFO			0xF34
37338 +#define RK3588_VP3_DSP_VACT_INFO			0xF38
37339 +#define RK3588_VP3_POST_DSP_VACT_INFO_F1		0xF44
37340 +#define RK3588_VP3_DSP_HTOTAL_HS_END			0xF48
37341 +#define RK3588_VP3_DSP_HACT_ST_END			0xF4C
37342 +#define RK3588_VP3_DSP_VTOTAL_VS_END			0xF50
37343 +#define RK3588_VP3_DSP_VACT_ST_END			0xF54
37344 +#define RK3588_VP3_DSP_VS_ST_END_F1			0xF58
37345 +#define RK3588_VP3_DSP_VACT_ST_END_F1			0xF5C
37346 +#define RK3588_VP3_BCSH_CTRL				0xF60
37347 +#define RK3588_VP3_BCSH_BCS				0xF64
37348 +#define RK3588_VP3_BCSH_H				0xF68
37349 +#define RK3588_VP3_BCSH_COLOR_BAR			0xF6C
37352 +#define RK3568_OVL_CTRL				0x600
37353 +#define RK3568_OVL_LAYER_SEL			0x604
37354 +#define RK3568_OVL_PORT_SEL			0x608
37355 +#define RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL	0x610
37356 +#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL	0x614
37357 +#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL	0x618
37358 +#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL	0x61C
37359 +#define RK3568_MIX0_SRC_COLOR_CTRL		0x650
37360 +#define RK3568_MIX0_DST_COLOR_CTRL		0x654
37361 +#define RK3568_MIX0_SRC_ALPHA_CTRL		0x658
37362 +#define RK3568_MIX0_DST_ALPHA_CTRL		0x65C
37363 +#define RK3568_HDR0_SRC_COLOR_CTRL		0x6C0
37364 +#define RK3568_HDR0_DST_COLOR_CTRL		0x6C4
37365 +#define RK3568_HDR0_SRC_ALPHA_CTRL		0x6C8
37366 +#define RK3568_HDR0_DST_ALPHA_CTRL		0x6CC
37367 +#define RK3568_HDR1_SRC_COLOR_CTRL		0x6D0
37368 +#define RK3568_HDR1_DST_COLOR_CTRL		0x6D4
37369 +#define RK3568_HDR1_SRC_ALPHA_CTRL		0x6D8
37370 +#define RK3568_HDR1_DST_ALPHA_CTRL		0x6DC
37371 +#define RK3568_VP0_BG_MIX_CTRL			0x6E0
37372 +#define RK3568_VP1_BG_MIX_CTRL			0x6E4
37373 +#define RK3568_VP2_BG_MIX_CTRL			0x6E8
37374 +#define RK3588_VP3_BG_MIX_CTRL			0x6EC
37375 +#define RK3568_CLUSTER_DLY_NUM			0x6F0
37376 +#define RK3568_CLUSTER_DLY_NUM1			0x6F4
37377 +#define RK3568_SMART_DLY_NUM			0x6F8
37380 +#define RK3568_CLUSTER0_WIN0_CTRL0		0x1000
37381 +#define RK3568_CLUSTER0_WIN0_CTRL1		0x1004
37382 +#define RK3568_CLUSTER0_WIN0_CTRL2		0x1008
37383 +#define RK3568_CLUSTER0_WIN0_YRGB_MST		0x1010
37384 +#define RK3568_CLUSTER0_WIN0_CBR_MST		0x1014
37385 +#define RK3568_CLUSTER0_WIN0_VIR		0x1018
37386 +#define RK3568_CLUSTER0_WIN0_ACT_INFO		0x1020
37387 +#define RK3568_CLUSTER0_WIN0_DSP_INFO		0x1024
37388 +#define RK3568_CLUSTER0_WIN0_DSP_ST		0x1028
37389 +#define RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB	0x1030
37390 +#define RK3568_CLUSTER0_WIN0_AFBCD_TRANSFORM_OFFSET	0x103C
37391 +#define RK3568_CLUSTER0_WIN0_AFBCD_OUTPUT_CTRL	0x1050
37392 +#define RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE	0x1054
37393 +#define RK3568_CLUSTER0_WIN0_AFBCD_HDR_PTR	0x1058
37394 +#define RK3568_CLUSTER0_WIN0_AFBCD_VIR_WIDTH	0x105C
37395 +#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_SIZE	0x1060
37396 +#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET	0x1064
37397 +#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET	0x1068
37398 +#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL		0x106C
37400 +#define RK3568_CLUSTER0_WIN1_CTRL0		0x1080
37401 +#define RK3568_CLUSTER0_WIN1_CTRL1		0x1084
37402 +#define RK3568_CLUSTER0_WIN1_YRGB_MST		0x1090
37403 +#define RK3568_CLUSTER0_WIN1_CBR_MST		0x1094
37404 +#define RK3568_CLUSTER0_WIN1_VIR		0x1098
37405 +#define RK3568_CLUSTER0_WIN1_ACT_INFO		0x10A0
37406 +#define RK3568_CLUSTER0_WIN1_DSP_INFO		0x10A4
37407 +#define RK3568_CLUSTER0_WIN1_DSP_ST		0x10A8
37408 +#define RK3568_CLUSTER0_WIN1_SCL_FACTOR_YRGB	0x10B0
37409 +#define RK3568_CLUSTER0_WIN1_AFBCD_OUTPUT_CTRL	0x10D0
37410 +#define RK3568_CLUSTER0_WIN1_AFBCD_ROTATE_MODE	0x10D4
37411 +#define RK3568_CLUSTER0_WIN1_AFBCD_HDR_PTR	0x10D8
37412 +#define RK3568_CLUSTER0_WIN1_AFBCD_VIR_WIDTH	0x10DC
37413 +#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_SIZE	0x10E0
37414 +#define RK3568_CLUSTER0_WIN1_AFBCD_PIC_OFFSET	0x10E4
37415 +#define RK3568_CLUSTER0_WIN1_AFBCD_DSP_OFFSET	0x10E8
37416 +#define RK3568_CLUSTER0_WIN1_AFBCD_CTRL		0x10EC
37418 +#define RK3568_CLUSTER0_CTRL			0x1100
37420 +#define RK3568_CLUSTER1_WIN0_CTRL0		0x1200
37421 +#define RK3568_CLUSTER1_WIN0_CTRL1		0x1204
37422 +#define RK3568_CLUSTER1_WIN0_CTRL2		0x1208
37423 +#define RK3568_CLUSTER1_WIN0_YRGB_MST		0x1210
37424 +#define RK3568_CLUSTER1_WIN0_CBR_MST		0x1214
37425 +#define RK3568_CLUSTER1_WIN0_VIR		0x1218
37426 +#define RK3568_CLUSTER1_WIN0_ACT_INFO		0x1220
37427 +#define RK3568_CLUSTER1_WIN0_DSP_INFO		0x1224
37428 +#define RK3568_CLUSTER1_WIN0_DSP_ST		0x1228
37429 +#define RK3568_CLUSTER1_WIN0_SCL_FACTOR_YRGB	0x1230
37430 +#define RK3568_CLUSTER1_WIN0_AFBCD_TRANSFORM_OFFSET	0x123C
37431 +#define RK3568_CLUSTER1_WIN0_AFBCD_OUTPUT_CTRL	0x1250
37432 +#define RK3568_CLUSTER1_WIN0_AFBCD_ROTATE_MODE	0x1254
37433 +#define RK3568_CLUSTER1_WIN0_AFBCD_HDR_PTR	0x1258
37434 +#define RK3568_CLUSTER1_WIN0_AFBCD_VIR_WIDTH	0x125C
37435 +#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_SIZE	0x1260
37436 +#define RK3568_CLUSTER1_WIN0_AFBCD_PIC_OFFSET	0x1264
37437 +#define RK3568_CLUSTER1_WIN0_AFBCD_DSP_OFFSET	0x1268
37438 +#define RK3568_CLUSTER1_WIN0_AFBCD_CTRL		0x126C
37440 +#define RK3568_CLUSTER1_WIN1_CTRL0		0x1280
37441 +#define RK3568_CLUSTER1_WIN1_CTRL1		0x1284
37442 +#define RK3568_CLUSTER1_WIN1_YRGB_MST		0x1290
37443 +#define RK3568_CLUSTER1_WIN1_CBR_MST		0x1294
37444 +#define RK3568_CLUSTER1_WIN1_VIR		0x1298
37445 +#define RK3568_CLUSTER1_WIN1_ACT_INFO		0x12A0
37446 +#define RK3568_CLUSTER1_WIN1_DSP_INFO		0x12A4
37447 +#define RK3568_CLUSTER1_WIN1_DSP_ST		0x12A8
37448 +#define RK3568_CLUSTER1_WIN1_SCL_FACTOR_YRGB	0x12B0
37449 +#define RK3568_CLUSTER1_WIN1_AFBCD_OUTPUT_CTRL	0x12D0
37450 +#define RK3568_CLUSTER1_WIN1_AFBCD_ROTATE_MODE	0x12D4
37451 +#define RK3568_CLUSTER1_WIN1_AFBCD_HDR_PTR	0x12D8
37452 +#define RK3568_CLUSTER1_WIN1_AFBCD_VIR_WIDTH	0x12DC
37453 +#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_SIZE	0x12E0
37454 +#define RK3568_CLUSTER1_WIN1_AFBCD_PIC_OFFSET	0x12E4
37455 +#define RK3568_CLUSTER1_WIN1_AFBCD_DSP_OFFSET	0x12E8
37456 +#define RK3568_CLUSTER1_WIN1_AFBCD_CTRL		0x12EC
37458 +#define RK3568_CLUSTER1_CTRL			0x1300
37460 +#define RK3588_CLUSTER2_WIN0_CTRL0		0x1400
37461 +#define RK3588_CLUSTER2_WIN0_CTRL1		0x1404
37462 +#define RK3588_CLUSTER2_WIN0_CTRL2		0x1408
37463 +#define RK3588_CLUSTER2_WIN0_YRGB_MST		0x1410
37464 +#define RK3588_CLUSTER2_WIN0_CBR_MST		0x1414
37465 +#define RK3588_CLUSTER2_WIN0_VIR		0x1418
37466 +#define RK3588_CLUSTER2_WIN0_ACT_INFO		0x1420
37467 +#define RK3588_CLUSTER2_WIN0_DSP_INFO		0x1424
37468 +#define RK3588_CLUSTER2_WIN0_DSP_ST		0x1428
37469 +#define RK3588_CLUSTER2_WIN0_SCL_FACTOR_YRGB	0x1430
37470 +#define RK3588_CLUSTER2_WIN0_AFBCD_TRANSFORM_OFFSET	0x143C
37471 +#define RK3588_CLUSTER2_WIN0_AFBCD_OUTPUT_CTRL	0x1450
37472 +#define RK3588_CLUSTER2_WIN0_AFBCD_ROTATE_MODE	0x1454
37473 +#define RK3588_CLUSTER2_WIN0_AFBCD_HDR_PTR	0x1458
37474 +#define RK3588_CLUSTER2_WIN0_AFBCD_VIR_WIDTH	0x145C
37475 +#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_SIZE	0x1460
37476 +#define RK3588_CLUSTER2_WIN0_AFBCD_PIC_OFFSET	0x1464
37477 +#define RK3588_CLUSTER2_WIN0_AFBCD_DSP_OFFSET	0x1468
37478 +#define RK3588_CLUSTER2_WIN0_AFBCD_CTRL		0x146C
37480 +#define RK3588_CLUSTER2_WIN1_CTRL0		0x1480
37481 +#define RK3588_CLUSTER2_WIN1_CTRL1		0x1484
37482 +#define RK3588_CLUSTER2_WIN1_YRGB_MST		0x1490
37483 +#define RK3588_CLUSTER2_WIN1_CBR_MST		0x1494
37484 +#define RK3588_CLUSTER2_WIN1_VIR		0x1498
37485 +#define RK3588_CLUSTER2_WIN1_ACT_INFO		0x14A0
37486 +#define RK3588_CLUSTER2_WIN1_DSP_INFO		0x14A4
37487 +#define RK3588_CLUSTER2_WIN1_DSP_ST		0x14A8
37488 +#define RK3588_CLUSTER2_WIN1_SCL_FACTOR_YRGB	0x14B0
37489 +#define RK3588_CLUSTER2_WIN1_AFBCD_OUTPUT_CTRL	0x14D0
37490 +#define RK3588_CLUSTER2_WIN1_AFBCD_ROTATE_MODE	0x14D4
37491 +#define RK3588_CLUSTER2_WIN1_AFBCD_HDR_PTR	0x14D8
37492 +#define RK3588_CLUSTER2_WIN1_AFBCD_VIR_WIDTH	0x14DC
37493 +#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_SIZE	0x14E0
37494 +#define RK3588_CLUSTER2_WIN1_AFBCD_PIC_OFFSET	0x14E4
37495 +#define RK3588_CLUSTER2_WIN1_AFBCD_DSP_OFFSET	0x14E8
37496 +#define RK3588_CLUSTER2_WIN1_AFBCD_CTRL		0x14EC
37498 +#define RK3588_CLUSTER2_CTRL			0x1500
37500 +#define RK3588_CLUSTER3_WIN0_CTRL0		0x1600
37501 +#define RK3588_CLUSTER3_WIN0_CTRL1		0x1604
37502 +#define RK3588_CLUSTER3_WIN0_CTRL2		0x1608
37503 +#define RK3588_CLUSTER3_WIN0_YRGB_MST		0x1610
37504 +#define RK3588_CLUSTER3_WIN0_CBR_MST		0x1614
37505 +#define RK3588_CLUSTER3_WIN0_VIR		0x1618
37506 +#define RK3588_CLUSTER3_WIN0_ACT_INFO		0x1620
37507 +#define RK3588_CLUSTER3_WIN0_DSP_INFO		0x1624
37508 +#define RK3588_CLUSTER3_WIN0_DSP_ST		0x1628
37509 +#define RK3588_CLUSTER3_WIN0_SCL_FACTOR_YRGB	0x1630
37510 +#define RK3588_CLUSTER3_WIN0_AFBCD_TRANSFORM_OFFSET	0x163C
37511 +#define RK3588_CLUSTER3_WIN0_AFBCD_OUTPUT_CTRL	0x1650
37512 +#define RK3588_CLUSTER3_WIN0_AFBCD_ROTATE_MODE	0x1654
37513 +#define RK3588_CLUSTER3_WIN0_AFBCD_HDR_PTR	0x1658
37514 +#define RK3588_CLUSTER3_WIN0_AFBCD_VIR_WIDTH	0x165C
37515 +#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_SIZE	0x1660
37516 +#define RK3588_CLUSTER3_WIN0_AFBCD_PIC_OFFSET	0x1664
37517 +#define RK3588_CLUSTER3_WIN0_AFBCD_DSP_OFFSET	0x1668
37518 +#define RK3588_CLUSTER3_WIN0_AFBCD_CTRL		0x166C
37520 +#define RK3588_CLUSTER3_WIN1_CTRL0		0x1680
37521 +#define RK3588_CLUSTER3_WIN1_CTRL1		0x1684
37522 +#define RK3588_CLUSTER3_WIN1_YRGB_MST		0x1690
37523 +#define RK3588_CLUSTER3_WIN1_CBR_MST		0x1694
37524 +#define RK3588_CLUSTER3_WIN1_VIR		0x1698
37525 +#define RK3588_CLUSTER3_WIN1_ACT_INFO		0x16A0
37526 +#define RK3588_CLUSTER3_WIN1_DSP_INFO		0x16A4
37527 +#define RK3588_CLUSTER3_WIN1_DSP_ST		0x16A8
37528 +#define RK3588_CLUSTER3_WIN1_SCL_FACTOR_YRGB	0x16B0
37529 +#define RK3588_CLUSTER3_WIN1_AFBCD_OUTPUT_CTRL	0x16D0
37530 +#define RK3588_CLUSTER3_WIN1_AFBCD_ROTATE_MODE	0x16D4
37531 +#define RK3588_CLUSTER3_WIN1_AFBCD_HDR_PTR	0x16D8
37532 +#define RK3588_CLUSTER3_WIN1_AFBCD_VIR_WIDTH	0x16DC
37533 +#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_SIZE	0x16E0
37534 +#define RK3588_CLUSTER3_WIN1_AFBCD_PIC_OFFSET	0x16E4
37535 +#define RK3588_CLUSTER3_WIN1_AFBCD_DSP_OFFSET	0x16E8
37536 +#define RK3588_CLUSTER3_WIN1_AFBCD_CTRL		0x16EC
37538 +#define RK3588_CLUSTER3_CTRL			0x1700
37541 +#define RK3568_ESMART0_CTRL0			0x1800
37542 +#define RK3568_ESMART0_CTRL1			0x1804
37543 +#define RK3568_ESMART0_AXI_CTRL			0x1808
37544 +#define RK3568_ESMART0_REGION0_CTRL		0x1810
37545 +#define RK3568_ESMART0_REGION0_YRGB_MST		0x1814
37546 +#define RK3568_ESMART0_REGION0_CBR_MST		0x1818
37547 +#define RK3568_ESMART0_REGION0_VIR		0x181C
37548 +#define RK3568_ESMART0_REGION0_ACT_INFO		0x1820
37549 +#define RK3568_ESMART0_REGION0_DSP_INFO		0x1824
37550 +#define RK3568_ESMART0_REGION0_DSP_ST		0x1828
37551 +#define RK3568_ESMART0_REGION0_SCL_CTRL		0x1830
37552 +#define RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB	0x1834
37553 +#define RK3568_ESMART0_REGION0_SCL_FACTOR_CBR	0x1838
37554 +#define RK3568_ESMART0_REGION0_SCL_OFFSET	0x183C
37555 +#define RK3568_ESMART0_REGION1_CTRL		0x1840
37556 +#define RK3568_ESMART0_REGION1_YRGB_MST		0x1844
37557 +#define RK3568_ESMART0_REGION1_CBR_MST		0x1848
37558 +#define RK3568_ESMART0_REGION1_VIR		0x184C
37559 +#define RK3568_ESMART0_REGION1_ACT_INFO		0x1850
37560 +#define RK3568_ESMART0_REGION1_DSP_INFO		0x1854
37561 +#define RK3568_ESMART0_REGION1_DSP_ST		0x1858
37562 +#define RK3568_ESMART0_REGION1_SCL_CTRL		0x1860
37563 +#define RK3568_ESMART0_REGION1_SCL_FACTOR_YRGB	0x1864
37564 +#define RK3568_ESMART0_REGION1_SCL_FACTOR_CBR	0x1868
37565 +#define RK3568_ESMART0_REGION1_SCL_OFFSET	0x186C
37566 +#define RK3568_ESMART0_REGION2_CTRL		0x1870
37567 +#define RK3568_ESMART0_REGION2_YRGB_MST		0x1874
37568 +#define RK3568_ESMART0_REGION2_CBR_MST		0x1878
37569 +#define RK3568_ESMART0_REGION2_VIR		0x187C
37570 +#define RK3568_ESMART0_REGION2_ACT_INFO		0x1880
37571 +#define RK3568_ESMART0_REGION2_DSP_INFO		0x1884
37572 +#define RK3568_ESMART0_REGION2_DSP_ST		0x1888
37573 +#define RK3568_ESMART0_REGION2_SCL_CTRL		0x1890
37574 +#define RK3568_ESMART0_REGION2_SCL_FACTOR_YRGB	0x1894
37575 +#define RK3568_ESMART0_REGION2_SCL_FACTOR_CBR	0x1898
37576 +#define RK3568_ESMART0_REGION2_SCL_OFFSET	0x189C
37577 +#define RK3568_ESMART0_REGION3_CTRL		0x18A0
37578 +#define RK3568_ESMART0_REGION3_YRGB_MST		0x18A4
37579 +#define RK3568_ESMART0_REGION3_CBR_MST		0x18A8
37580 +#define RK3568_ESMART0_REGION3_VIR		0x18AC
37581 +#define RK3568_ESMART0_REGION3_ACT_INFO		0x18B0
37582 +#define RK3568_ESMART0_REGION3_DSP_INFO		0x18B4
37583 +#define RK3568_ESMART0_REGION3_DSP_ST		0x18B8
37584 +#define RK3568_ESMART0_REGION3_SCL_CTRL		0x18C0
37585 +#define RK3568_ESMART0_REGION3_SCL_FACTOR_YRGB	0x18C4
37586 +#define RK3568_ESMART0_REGION3_SCL_FACTOR_CBR	0x18C8
37587 +#define RK3568_ESMART0_REGION3_SCL_OFFSET	0x18CC
37588 +#define RK3568_ESMART0_COLOR_KEY_CTRL		0x18D0
37590 +#define RK3568_ESMART1_CTRL0			0x1A00
37591 +#define RK3568_ESMART1_CTRL1			0x1A04
37592 +#define RK3568_ESMART1_REGION0_CTRL		0x1A10
37593 +#define RK3568_ESMART1_REGION0_YRGB_MST		0x1A14
37594 +#define RK3568_ESMART1_REGION0_CBR_MST		0x1A18
37595 +#define RK3568_ESMART1_REGION0_VIR		0x1A1C
37596 +#define RK3568_ESMART1_REGION0_ACT_INFO		0x1A20
37597 +#define RK3568_ESMART1_REGION0_DSP_INFO		0x1A24
37598 +#define RK3568_ESMART1_REGION0_DSP_ST		0x1A28
37599 +#define RK3568_ESMART1_REGION0_SCL_CTRL		0x1A30
37600 +#define RK3568_ESMART1_REGION0_SCL_FACTOR_YRGB	0x1A34
37601 +#define RK3568_ESMART1_REGION0_SCL_FACTOR_CBR	0x1A38
37602 +#define RK3568_ESMART1_REGION0_SCL_OFFSET	0x1A3C
37603 +#define RK3568_ESMART1_REGION1_CTRL		0x1A40
37604 +#define RK3568_ESMART1_REGION1_YRGB_MST		0x1A44
37605 +#define RK3568_ESMART1_REGION1_CBR_MST		0x1A48
37606 +#define RK3568_ESMART1_REGION1_VIR		0x1A4C
37607 +#define RK3568_ESMART1_REGION1_ACT_INFO		0x1A50
37608 +#define RK3568_ESMART1_REGION1_DSP_INFO		0x1A54
37609 +#define RK3568_ESMART1_REGION1_DSP_ST		0x1A58
37610 +#define RK3568_ESMART1_REGION1_SCL_CTRL		0x1A60
37611 +#define RK3568_ESMART1_REGION1_SCL_FACTOR_YRGB	0x1A64
37612 +#define RK3568_ESMART1_REGION1_SCL_FACTOR_CBR	0x1A68
37613 +#define RK3568_ESMART1_REGION1_SCL_OFFSET	0x1A6C
37614 +#define RK3568_ESMART1_REGION2_CTRL		0x1A70
37615 +#define RK3568_ESMART1_REGION2_YRGB_MST		0x1A74
37616 +#define RK3568_ESMART1_REGION2_CBR_MST		0x1A78
37617 +#define RK3568_ESMART1_REGION2_VIR		0x1A7C
37618 +#define RK3568_ESMART1_REGION2_ACT_INFO		0x1A80
37619 +#define RK3568_ESMART1_REGION2_DSP_INFO		0x1A84
37620 +#define RK3568_ESMART1_REGION2_DSP_ST		0x1A88
37621 +#define RK3568_ESMART1_REGION2_SCL_CTRL		0x1A90
37622 +#define RK3568_ESMART1_REGION2_SCL_FACTOR_YRGB	0x1A94
37623 +#define RK3568_ESMART1_REGION2_SCL_FACTOR_CBR	0x1A98
37624 +#define RK3568_ESMART1_REGION2_SCL_OFFSET	0x1A9C
37625 +#define RK3568_ESMART1_REGION3_CTRL		0x1AA0
37626 +#define RK3568_ESMART1_REGION3_YRGB_MST		0x1AA4
37627 +#define RK3568_ESMART1_REGION3_CBR_MST		0x1AA8
37628 +#define RK3568_ESMART1_REGION3_VIR		0x1AAC
37629 +#define RK3568_ESMART1_REGION3_ACT_INFO		0x1AB0
37630 +#define RK3568_ESMART1_REGION3_DSP_INFO		0x1AB4
37631 +#define RK3568_ESMART1_REGION3_DSP_ST		0x1AB8
37632 +#define RK3568_ESMART1_REGION3_SCL_CTRL		0x1AC0
37633 +#define RK3568_ESMART1_REGION3_SCL_FACTOR_YRGB	0x1AC4
37634 +#define RK3568_ESMART1_REGION3_SCL_FACTOR_CBR	0x1AC8
37635 +#define RK3568_ESMART1_REGION3_SCL_OFFSET	0x1ACC
37637 +#define RK3568_SMART0_CTRL0			0x1C00
37638 +#define RK3568_SMART0_CTRL1			0x1C04
37639 +#define RK3568_SMART0_REGION0_CTRL		0x1C10
37640 +#define RK3568_SMART0_REGION0_YRGB_MST		0x1C14
37641 +#define RK3568_SMART0_REGION0_CBR_MST		0x1C18
37642 +#define RK3568_SMART0_REGION0_VIR		0x1C1C
37643 +#define RK3568_SMART0_REGION0_ACT_INFO		0x1C20
37644 +#define RK3568_SMART0_REGION0_DSP_INFO		0x1C24
37645 +#define RK3568_SMART0_REGION0_DSP_ST		0x1C28
37646 +#define RK3568_SMART0_REGION0_SCL_CTRL		0x1C30
37647 +#define RK3568_SMART0_REGION0_SCL_FACTOR_YRGB	0x1C34
37648 +#define RK3568_SMART0_REGION0_SCL_FACTOR_CBR	0x1C38
37649 +#define RK3568_SMART0_REGION0_SCL_OFFSET	0x1C3C
37650 +#define RK3568_SMART0_REGION1_CTRL		0x1C40
37651 +#define RK3568_SMART0_REGION1_YRGB_MST		0x1C44
37652 +#define RK3568_SMART0_REGION1_CBR_MST		0x1C48
37653 +#define RK3568_SMART0_REGION1_VIR		0x1C4C
37654 +#define RK3568_SMART0_REGION1_ACT_INFO		0x1C50
37655 +#define RK3568_SMART0_REGION1_DSP_INFO		0x1C54
37656 +#define RK3568_SMART0_REGION1_DSP_ST		0x1C58
37657 +#define RK3568_SMART0_REGION1_SCL_CTRL		0x1C60
37658 +#define RK3568_SMART0_REGION1_SCL_FACTOR_YRGB	0x1C64
37659 +#define RK3568_SMART0_REGION1_SCL_FACTOR_CBR	0x1C68
37660 +#define RK3568_SMART0_REGION1_SCL_OFFSET	0x1C6C
37661 +#define RK3568_SMART0_REGION2_CTRL		0x1C70
37662 +#define RK3568_SMART0_REGION2_YRGB_MST		0x1C74
37663 +#define RK3568_SMART0_REGION2_CBR_MST		0x1C78
37664 +#define RK3568_SMART0_REGION2_VIR		0x1C7C
37665 +#define RK3568_SMART0_REGION2_ACT_INFO		0x1C80
37666 +#define RK3568_SMART0_REGION2_DSP_INFO		0x1C84
37667 +#define RK3568_SMART0_REGION2_DSP_ST		0x1C88
37668 +#define RK3568_SMART0_REGION2_SCL_CTRL		0x1C90
37669 +#define RK3568_SMART0_REGION2_SCL_FACTOR_YRGB	0x1C94
37670 +#define RK3568_SMART0_REGION2_SCL_FACTOR_CBR	0x1C98
37671 +#define RK3568_SMART0_REGION2_SCL_OFFSET	0x1C9C
37672 +#define RK3568_SMART0_REGION3_CTRL		0x1CA0
37673 +#define RK3568_SMART0_REGION3_YRGB_MST		0x1CA4
37674 +#define RK3568_SMART0_REGION3_CBR_MST		0x1CA8
37675 +#define RK3568_SMART0_REGION3_VIR		0x1CAC
37676 +#define RK3568_SMART0_REGION3_ACT_INFO		0x1CB0
37677 +#define RK3568_SMART0_REGION3_DSP_INFO		0x1CB4
37678 +#define RK3568_SMART0_REGION3_DSP_ST		0x1CB8
37679 +#define RK3568_SMART0_REGION3_SCL_CTRL		0x1CC0
37680 +#define RK3568_SMART0_REGION3_SCL_FACTOR_YRGB	0x1CC4
37681 +#define RK3568_SMART0_REGION3_SCL_FACTOR_CBR	0x1CC8
37682 +#define RK3568_SMART0_REGION3_SCL_OFFSET	0x1CCC
37684 +#define RK3568_SMART1_CTRL0			0x1E00
37685 +#define RK3568_SMART1_CTRL1			0x1E04
37686 +#define RK3568_SMART1_REGION0_CTRL		0x1E10
37687 +#define RK3568_SMART1_REGION0_YRGB_MST		0x1E14
37688 +#define RK3568_SMART1_REGION0_CBR_MST		0x1E18
37689 +#define RK3568_SMART1_REGION0_VIR		0x1E1C
37690 +#define RK3568_SMART1_REGION0_ACT_INFO		0x1E20
37691 +#define RK3568_SMART1_REGION0_DSP_INFO		0x1E24
37692 +#define RK3568_SMART1_REGION0_DSP_ST		0x1E28
37693 +#define RK3568_SMART1_REGION0_SCL_CTRL		0x1E30
37694 +#define RK3568_SMART1_REGION0_SCL_FACTOR_YRGB	0x1E34
37695 +#define RK3568_SMART1_REGION0_SCL_FACTOR_CBR	0x1E38
37696 +#define RK3568_SMART1_REGION0_SCL_OFFSET	0x1E3C
37697 +#define RK3568_SMART1_REGION1_CTRL		0x1E40
37698 +#define RK3568_SMART1_REGION1_YRGB_MST		0x1E44
37699 +#define RK3568_SMART1_REGION1_CBR_MST		0x1E48
37700 +#define RK3568_SMART1_REGION1_VIR		0x1E4C
37701 +#define RK3568_SMART1_REGION1_ACT_INFO		0x1E50
37702 +#define RK3568_SMART1_REGION1_DSP_INFO		0x1E54
37703 +#define RK3568_SMART1_REGION1_DSP_ST		0x1E58
37704 +#define RK3568_SMART1_REGION1_SCL_CTRL		0x1E60
37705 +#define RK3568_SMART1_REGION1_SCL_FACTOR_YRGB	0x1E64
37706 +#define RK3568_SMART1_REGION1_SCL_FACTOR_CBR	0x1E68
37707 +#define RK3568_SMART1_REGION1_SCL_OFFSET	0x1E6C
37708 +#define RK3568_SMART1_REGION2_CTRL		0x1E70
37709 +#define RK3568_SMART1_REGION2_YRGB_MST		0x1E74
37710 +#define RK3568_SMART1_REGION2_CBR_MST		0x1E78
37711 +#define RK3568_SMART1_REGION2_VIR		0x1E7C
37712 +#define RK3568_SMART1_REGION2_ACT_INFO		0x1E80
37713 +#define RK3568_SMART1_REGION2_DSP_INFO		0x1E84
37714 +#define RK3568_SMART1_REGION2_DSP_ST		0x1E88
37715 +#define RK3568_SMART1_REGION2_SCL_CTRL		0x1E90
37716 +#define RK3568_SMART1_REGION2_SCL_FACTOR_YRGB	0x1E94
37717 +#define RK3568_SMART1_REGION2_SCL_FACTOR_CBR	0x1E98
37718 +#define RK3568_SMART1_REGION2_SCL_OFFSET	0x1E9C
37719 +#define RK3568_SMART1_REGION3_CTRL		0x1EA0
37720 +#define RK3568_SMART1_REGION3_YRGB_MST		0x1EA4
37721 +#define RK3568_SMART1_REGION3_CBR_MST		0x1EA8
37722 +#define RK3568_SMART1_REGION3_VIR		0x1EAC
37723 +#define RK3568_SMART1_REGION3_ACT_INFO		0x1EB0
37724 +#define RK3568_SMART1_REGION3_DSP_INFO		0x1EB4
37725 +#define RK3568_SMART1_REGION3_DSP_ST		0x1EB8
37726 +#define RK3568_SMART1_REGION3_SCL_CTRL		0x1EC0
37727 +#define RK3568_SMART1_REGION3_SCL_FACTOR_YRGB	0x1EC4
37728 +#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR	0x1EC8
37729 +#define RK3568_SMART1_REGION3_SCL_OFFSET	0x1ECC
37732 +#define RK3568_HDR_LUT_CTRL				0x2000
37733 +#define RK3568_HDR_LUT_MST				0x2004
37734 +#define RK3568_SDR2HDR_CTRL				0x2010
37736 +#define RK3568_SDR2HDR_CTRL1				0x2018
37737 +#define RK3568_HDR2SDR_CTRL1				0x201C
37738 +#define RK3568_HDR2SDR_CTRL				0x2020
37739 +#define RK3568_HDR2SDR_SRC_RANGE			0x2024
37740 +#define RK3568_HDR2SDR_NORMFACEETF			0x2028
37741 +#define RK3568_HDR2SDR_DST_RANGE			0x202C
37742 +#define RK3568_HDR2SDR_NORMFACCGAMMA			0x2030
37743 +#define RK3568_HDR_EETF_OETF_Y0				0x203C
37744 +#define RK3568_HDR_SAT_Y0				0x20C0
37745 +#define RK3568_HDR_EOTF_OETF_Y0				0x20F0
37746 +#define RK3568_HDR_OETF_DX_POW1				0x2200
37747 +#define RK3568_HDR_OETF_XN1				0x2300
37750 +#define RK3588_DSC_8K_PPS0_3				0x4000
37751 +#define RK3588_DSC_8K_CTRL0				0x40A0
37752 +#define RK3588_DSC_8K_CTRL1				0x40A4
37753 +#define RK3588_DSC_8K_STS0				0x40A8
37754 +#define RK3588_DSC_8K_ERS				0x40C4
37756 +#define RK3588_DSC_4K_PPS0_3				0x4100
37757 +#define RK3588_DSC_4K_CTRL0				0x41A0
37758 +#define RK3588_DSC_4K_CTRL1				0x41A4
37759 +#define RK3588_DSC_4K_STS0				0x41A8
37760 +#define RK3588_DSC_4K_ERS				0x41C4
37762 +#define RK3588_GRF_SOC_CON1				0x0304
37763 +#define RK3588_GRF_VOP_CON2				0x08
37764 +#define RK3588_GRF_VO1_CON0				0x00
37767 +#define RK3588_PMU_PWR_GATE_CON1			0x150
37768 +#define RK3588_PMU_SUBMEM_PWR_GATE_CON1			0x1B4
37769 +#define RK3588_PMU_SUBMEM_PWR_GATE_CON2			0x1B8
37770 +#define RK3588_PMU_SUBMEM_PWR_GATE_STATUS		0x1BC
37771 +#define RK3588_PMU_BISR_CON3				0x20C
37772 +#define RK3588_PMU_BISR_STATUS5				0x294
37776 index 02ddb237f..0b3adca2e 100644
37789  #define REG_IEN        0x18 /* interrupt enable */
37790  #define REG_IPD        0x1c /* interrupt pending */
37791  #define REG_FCNT       0x20 /* finished count */
37792 +#define REG_CON1       0x228 /* control register1 */
37795  #define TXBUFFER_BASE 0x100
37801 +	RK_I2C_VERSION0 = 0,
37816 -#define REG_INT_ALL       0x7f
37817 +#define REG_INT_ALL       0xff
37820 +#define IEN_ALL_DISABLE   0
37822 +#define REG_CON1_AUTO_STOP BIT(0)
37893 +	unsigned int len, con1 = 0;
37932 +	int length = 0;
37983  	if (i2c->processed != 0) {
37999  	u32 cnt = 0;
38018 -		dev_warn(i2c->dev, "unexpected irq in START: 0x%x\n", ipd);
38077  		byte = (val >> ((i % 4) * 8)) & 0xff;
38104 +			if ((i2c->msg->len - i2c->processed) > 0)
38108 +		i2c->processed = 0;
38135 -		dev_warn(i2c->dev, "irq in STATE_IDLE, ipd = 0x%x\n", ipd);
38137 +				     "irq in STATE_IDLE, ipd = 0x%x\n",
38172  	i2c->addr = msgs[0].addr;
38175  	i2c->processed = 0;
38176  	i2c->error = 0;
38180 +		i2c_writel(i2c, 0, REG_CON1);
38185  	int ret = 0;
38211 -			i2c_writel(i2c, 0, REG_IEN);
38244 +			rk3x_i2c_irq(0, i2c);
38248 +	if (tmo <= 0) {
38249 +		dev_err(i2c->dev, "restart timeout, ipd: 0x%02x, state: %d\n",
38253 +		i2c_writel(i2c, 0, REG_IEN);
38292 +	return 0;
38303 +	i2c->suspended = 0;
38306  	return 0;
38314 +	.grf_offset = 0x408,
38319 +	.grf_offset = 0x118,
38337  	int ret = 0;
38354  	i2c->regs = devm_platform_ioremap_resource(pdev, 0);
38374 -		if (bus_nr < 0) {
38383 -		if (ret != 0) {
38391 +			if (bus_nr < 0) {
38397 +				/* rv1108 i2c2 set grf offset-0x408, bit-10 */
38401 +				/* rv1126 i2c2 set pmugrf offset-0x118, bit-4 */
38409 +			if (ret != 0) {
38425  	if (ret < 0)
38435  	return 0;
38496 +	if (status == 0)
38514 +			"%d i2c clients have been registered at 0x%02x",
38534 -		"Failed to register i2c client %s at 0x%02x (%d)\n",
38557 +	return 0;
38565 +	addrinfo.cnt = 0;
38596  #define SARADC_DLY_PU_SOC_MASK		0x3f
38628 +		return 0;
38638 -		if (ret < 0) {
38643 +		if (info->uv_vref < 0)
38682 +	SARADC_CHANNEL(0, "adc0", 10),
38732 +	u32 val = 0;
38789 +	if (info->uv_vref < 0) {
38796  	if (ret < 0) {
38804 +	timer_setup(&info->timer, rockchip_saradc_timer, 0);
38896  	return 0;
38923 +	return 0;
38941 +	return 0;
39000 +	pgsizes = domain->pgsize_bitmap & GENMASK(__fls(size), 0);
39010 +		pgsizes &= GENMASK(__ffs(addr_merge), 0);
39023 +	pgsizes = domain->pgsize_bitmap & ~GENMASK(pgsize_idx, 0);
39071 +	pr_debug("mapping: iova 0x%lx pa %pa pgsize 0x%zx count %zu\n",
39079 +		*mapped = ret ? 0 : pgsize;
39090  	int ret = 0;
39094  		     domain->pgsize_bitmap == 0UL))
39098  	pr_debug("map: iova 0x%lx pa %pa size 0x%zx\n", iova, &paddr, size);
39102 +		size_t mapped = 0;
39104 -		pr_debug("mapping: iova 0x%lx pa %pa pgsize 0x%zx\n",
39129  	if (ret == 0 && ops->iotlb_sync_map)
39161  		     domain->pgsize_bitmap == 0UL))
39162  		return 0;
39178  	unsigned int i = 0;
39230  #define RK_MMU_DTE_ADDR		0x00	/* Directory table address */
39243  #define RK_IOMMU_PGSIZE_BITMAP 0x007ff000
39245 +#define DT_LO_MASK 0xfffff000
39251 +#define PAGE_DESC_LO_MASK   0xfffff000
39311  #define RK_DTE_PT_ADDRESS_MASK    0xfffff000
39312  #define RK_DTE_PT_VALID           BIT(0)
39316 + * 31:12 - PT address bit 31:0
39320 + *     0 - 1 if PT @ PT address is valid
39322 +#define RK_DTE_PT_ADDRESS_MASK_V2 0xfffffff0
39361  #define RK_PTE_PAGE_VALID         BIT(0)
39365 + * 31:12 - Page address bit 31:0
39371 + *     0 - 1 if Page @ Page address is valid
39373 +#define RK_PTE_PAGE_ADDRESS_MASK_V2  0xfffffff0
39374 +#define RK_PTE_PAGE_FLAGS_MASK_V2    0x0000000e
39403 +	u32 flags = 0;
39405 +	flags |= (prot & IOMMU_READ) ? RK_PTE_PAGE_READABLE_V2 : 0;
39406 +	flags |= (prot & IOMMU_WRITE) ? RK_PTE_PAGE_WRITABLE_V2 : 0;
39422 +	int retry_count = 0;
39428  		return 0;
39431  		return 0;
39436 +		return 0;
39443  		for (i = 0; i < iommu->num_mmu; i++)
39458 +	int retry_count = 0;
39464  		return 0;
39469 +		return 0;
39476  		for (i = 0; i < iommu->num_mmu; i++)
39491 +	int retry_count = 0;
39497  		return 0;
39502 +		return 0;
39509  		for (i = 0; i < iommu->num_mmu; i++)
39524 +	int retry_count = 0;
39530  		return 0;
39535 +		return 0;
39542  		for (i = 0; i < iommu->num_mmu; i++)
39560  		return 0;
39573  	for (i = 0; i < iommu->num_mmu; i++) {
39576 +		if (iommu->version >= 0x2)
39591 +		return 0;
39599 +	if (iommu->version >= 0x2) {
39611 +	if (iommu->version >= 0x2)
39622 +	if (iommu->version >= 0x2)
39655 +			if (int_mask != 0x0)
39669 +	phys_addr_t pt_phys, phys = 0;
39749  	return 0;
39765 +	for (pte_count = 0; pte_count < pte_total; pte_count++) {
39788 +	return 0;
39896 +	/* Just return 0 if iova is unmapped */
39899 +		return 0;
39932 +		if (WARN_ON_ONCE(ret < 0))
39936 +			for (i = 0; i < iommu->num_mmu; i++)
39963 +	return 0;
39981  	for (i = 0; i < iommu->num_mmu; i++) {
39984 +		if (iommu->version >= 0x2) {
40037 -		return 0;
40046 +		return 0;
40054  	if (!ret || WARN_ON_ONCE(ret < 0))
40055  		return 0;
40067 +	for (i = 0; i < NUM_DT_ENTRIES; i++) {
40136  	return 0;
40148 +	for (i = 0; i < iommu->num_mmu; i++)
40149 +		rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0);
40161 +	for (i = 0; i < iommu->num_mmu; i++) {
40206 +	.version = 0x1,
40210 +	.version = 0x2,
40248  	iommu->num_mmu = 0;
40260 -	for (i = 0; i < iommu->num_clocks; ++i)
40282  		iommu->num_clocks = 0;
40284 +	else if (err < 0)
40296 +	if (iommu->version >= 0x2)
40308 +	if (iommu->version >= 0x2)
40318  	for (i = 0; i < iommu->num_irq; i++) {
40326  	return 0;
40331  		return 0;
40334 +		return 0;
40337  	return 0;
40341  		return 0;
40344 +		return 0;
40499  	val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
40509  		return 0;
40513 +		return 0;
40517  		return 0;
40529  		return 0;
40533 +		return 0;
40537  		return 0;
40628 index 0c18714ae..5d1dc9915 100644
40696  	return 0;
40731 -	ctl->base = of_iomap(node, 0);
40736 +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
40745 -	domain = irq_domain_create_hierarchy(parent_domain, 0,
40756 +	ctl->domain = irq_domain_create_hierarchy(parent_domain, 0,
40773  	return 0;
40787 +	return 0;
40821  #define MAILBOX_A2B_INTEN		0x00
40822  #define MAILBOX_A2B_STATUS		0x04
40872 -	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x\n",
40876 +	dev_dbg(mb->mbox.dev, "Chan[%d]: A2B message, cmd 0x%08x, data 0x%08x\n",
40884  	return 0;
40890 +	u32 val = 0U;
40902  	return 0;
40911 -	writel_relaxed(0, mb->mbox_base + MAILBOX_B2A_INTEN);
40915 +	u32 val = 0U;
40934  	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
40943 +			dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x, data 0x%08x\n",
40966 -	for (idx = 0; idx < mb->mbox.num_chans; idx++) {
40980 -		dev_dbg(mb->mbox.dev, "Chan[%d]: B2A message, cmd 0x%08x\n",
40993  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
41007  	for (i = 0; i < mb->mbox.num_chans; i++) {
41009 -		if (irq < 0)
41016 -		if (ret < 0)
41018 +		if (irq < 0) {
41020 +			if (i > 0 && irq == -ENXIO)
41021 +				mb->chans[i].irq = mb->chans[0].irq;
41032 +			if (ret < 0)
41170  	return 0;
41186 +	int clr_num = 0;
41209 +	int ret = 0;
41210 +	int clr_num = 0;
41224 +	if (clr_num > 0)
41393 +		.resources = &rk816_pwrkey_resources[0],
41398 +		.resources = &rk816_rtc_resources[0],
41412  		.resources = &rk817_rtc_resources[0],
41499  	{ RK818_H5V_EN_REG,	  BIT(0),	    RK818_H5V_EN },
41527 +		.reg_offset = 0,
41531 +		.reg_offset = 0,
41586 +		.reg_offset = 0,
41590 +		.reg_offset = 0,
41594 +		.reg_offset = 0,
41598 +		.reg_offset = 0,
41602 +		.reg_offset = 0,
41606 +		.reg_offset = 0,
41610 +		.reg_offset = 0,
41670 +			   (0x3 << 5), (0x3 << 5));
41673 +			   (0x3 << 2), (0x0 << 2));
41758 +			   (0x3 << 5), (0x3 << 5));
41761 +			   (0x3 << 2), (0x0 << 2));
41830 +		ret = sscanf(buf, "%c %x %x ", &cmd, &input[0], &input[1]);
41835 +		addr = input[0] & 0xff;
41836 +		data = input[1] & 0xff;
41837 +		pr_info("cmd : %c %x %x\n\n", cmd, input[0], input[1]);
41849 +		ret = sscanf(buf, "%c %x ", &cmd, &input[0]);
41854 +		pr_info("cmd : %c %x\n\n", cmd, input[0]);
41855 +		addr = input[0] & 0xff;
41857 +		pr_info("%x %x\n", input[0], data);
41892 +		return 0;
41904 +		return 0;
41940 +		return 0;
41950 +	return 0;
41977 +	if (power_en_active0 != 0) {
41980 +		value = power_en_active0 & 0x0f;
41982 +			     RK817_POWER_EN_REG(0),
41983 +			     value | 0xf0);
41984 +		value = (power_en_active0 & 0xf0) >> 4;
41987 +			     value | 0xf0);
41988 +		value = power_en_active1 & 0x0f;
41991 +			     value | 0xf0);
41992 +		value = (power_en_active1 & 0xf0) >> 4;
41995 +			     value | 0xf0);
42007 +	 *	0b'00: reset the PMIC itself completely.
42008 +	 *	0b'01: reset the 'RST' related register only.
42010 +	 * In the case of 0b'00, PMIC reset itself which triggers SoC NPOR-reset
42014 +	 * Here we check if this reboot cmd is what we expect for 0b'01.
42016 +	for (i = 0; i < ARRAY_SIZE(pmic_rst_reg_only_cmd); i++) {
42039 +	ret = of_property_read_u32_index(np, "fb-inner-reg-idxs", 0, &inner);
42093 +	u8 on_source = 0, off_source = 0;
42095 +	int pm_off = 0, msb, lsb;
42189 +			dev_err(&client->dev, "read 0x%x failed\n", on_source);
42195 +			dev_err(&client->dev, "read 0x%x failed\n", off_source);
42199 +		dev_info(&client->dev, "source: on=0x%02x, off=0x%02x\n",
42211 +	for (i = 0; i < nr_pre_init_regs; i++) {
42218 +				"0x%x write err\n",
42237 -	for (i = 0; i < nr_pre_init_regs; i++) {
42249 -				"0x%x write err\n",
42285  	return 0;
42318  	return 0;
42324 -	int ret = 0;
42326 +	int i, ret = 0;
42329 +	for (i = 0; i < suspend_reg_num; i++) {
42335 +			dev_err(dev, "0x%x write err\n",
42387 -	int ret = 0;
42389 +	int i, ret = 0;
42392 +	for (i = 0; i < resume_reg_num; i++) {
42398 +			dev_err(dev, "0x%x write err\n",
42526 -	return 0;
42575 +	/*  0: oob  1:cap-sdio-irq */
42578 +	} else if (is_cap_sdio_irq == 0) {
42588 +	return 0;
42615 -MMC_DEV_ATTR(vendor, "0x%04x\n", card->cis.vendor);
42616 -MMC_DEV_ATTR(device, "0x%04x\n", card->cis.device);
42618 -MMC_DEV_ATTR(ocr, "0x%08x\n", card->ocr);
42619 -MMC_DEV_ATTR(rca, "0x%04x\n", card->rca);
42628 -	if (!card->info[num-1][0])								\
42629 -		return 0;									\
42681  			ret = mmc_io_rw_direct(card, 0, 0,
42683  	return 0;
42694 -		return 0;
42697 -		return 0;
42713 -	if (err <= 0)
42729 +		if (err <= 0)
42732 +		return 0;
42734 +	if (err > 0) {
42736 +		err = 0;
42741 -	return 0;
42757  	return 0;
42791 -	return mmc_send_io_op_cond(host, 0, NULL);
42823 +		rocr = 0xa0ffff00;
42856  	    mmc_sd_get_cid(host, ocr & rocr, card->raw_cid, NULL) == 0) {
42860  		    memcmp(card->raw_cid, oldcard->raw_cid, sizeof(card->raw_cid)) != 0)) {
42947 -		return 0;
42960  			retries = 0;
42992  	return 0;
43015 +	ret = mmc_send_io_op_cond(host, 0, NULL);
43030 +	int i, err = 0;
43032  	for (i = 0; i < host->card->sdio_funcs; i++) {
43046 -	return 0;
43053 -		return 0;
43062 -	host->pm_flags = 0;
43064 -	return 0;
43119 -			queue_delayed_work(system_wq, &host->sdio_irq_work, 0);
43177 - * Returns 0 if the HW reset was executed synchronously, returns 1 if the HW
43192 -		host->rescan_entered = 0;
43194 -		_mmc_detect_change(host, 0, false);
43214 +	return mmc_sdio_reinit_card(host, 0);
43224 +		err = mmc_send_io_op_cond(host, 0, &ocr);
43230 +		ocr = 0x20ffff00;
43233  	err = mmc_send_io_op_cond(host, 0, &ocr);
43245 +	err = mmc_sdio_init_card(host, rocr, NULL, 0);
43274 +		host->chip_alive = 0;
43287 +	err = mmc_send_io_op_cond(host, 0, &ocr);
43297 +	err = mmc_sdio_init_card(host, rocr, card, 0);
43302 +	return 0;
43337  	 * Note: div can only be 0 or 1, but div must be set to 1 for eMMC
43375 +	for (i = 0; i < ARRAY_SIZE(degrees); i++) {
43392 +	return 0;
43405 +			return 0;
43432  		priv->default_sample_phase = 0;
43445  	return 0;
43497  	return 0;
43500 index da5923a92..0b53484e9 100644
43531  #define DWCMSHC_CTRL_HS400		0x7
43533 +#define DWCMSHC_VER_ID			0x500
43534 +#define DWCMSHC_VER_TYPE		0x504
43535 +#define DWCMSHC_HOST_CTRL3		0x508
43536 +#define DWCMSHC_EMMC_CONTROL		0x52c
43537 +#define DWCMSHC_EMMC_ATCTRL		0x540
43540 +#define DWCMSHC_EMMC_DLL_CTRL		0x800
43541 +#define DWCMSHC_EMMC_DLL_RXCLK		0x804
43542 +#define DWCMSHC_EMMC_DLL_TXCLK		0x808
43543 +#define DWCMSHC_EMMC_DLL_STRBIN		0x80c
43544 +#define DWCMSHC_EMMC_DLL_STATUS0	0x840
43545 +#define DWCMSHC_EMMC_DLL_START		BIT(0)
43550 +#define DLL_TXCLK_TAPNUM_DEFAULT	0x10
43551 +#define DLL_STRBIN_TAPNUM_DEFAULT	0x8
43557 +#define DLL_RXCLK_INVERTER		0
43561 +	(((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0))
43603 +	host->mmc->actual_clock = 0;
43606 +	if (clock == 0)
43621 +	extra &= ~BIT(0);
43626 +		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
43627 +		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
43628 +		sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
43635 +	sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL);
43647 +	extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT |
43648 +		0x2 << DWCMSHC_EMMC_DLL_INC |
43659 +	extra = 0x1 << 16 | /* tune clock stop en */
43660 +		0x2 << 17 | /* pre-change delay */
43661 +		0x3 << 19;  /* post-change delay */
43713 +	priv->rockchip_clks[0].id = "axi";
43734 +	sdhci_writel(host, 0x0, DWCMSHC_HOST_CTRL3);
43736 +	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
43737 +	sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
43738 +	return 0;
43797  	return 0;
43845 +	sdhci_set_clock(host, 0);
43847 +	return 0;
43858 +	return 0;
43883 index e7fbc9b30..0fac2a260 100644
43943 +#define XPCS_APB_INCREMENT		(0x4)
43944 +#define XPCS_APB_MASK			GENMASK_ULL(20, 0)
43946 +#define SR_MII_BASE			(0x1F0000)
43947 +#define SR_MII1_BASE			(0x1A0000)
43949 +#define VR_MII_DIG_CTRL1		(0x8000)
43950 +#define VR_MII_AN_CTRL			(0x8001)
43951 +#define VR_MII_AN_INTR_STS		(0x8002)
43952 +#define VR_MII_LINK_TIMER_CTRL		(0x800A)
43956 +#define MII_MAC_AUTO_SW			(0x0200)
43957 +#define PCS_MODE_OFFSET			(0x1)
43958 +#define MII_AN_INTR_EN			(0x1)
43959 +#define PCS_SGMII_MODE			(0x2 << PCS_MODE_OFFSET)
43960 +#define PCS_QSGMII_MODE			(0X3 << PCS_MODE_OFFSET)
43966 +	(((x) == 0) ? SR_MII_BASE : (SR_MII1_BASE + ((x) - 1) * 0x10000)); \
44000 +		if (ret < 0)
44004 +	return (ret & MDIO_CTRL1_RESET) ? -ETIMEDOUT : 0;
44013 +	if (ret < 0)
44024 +	if (mode == PHY_INTERFACE_MODE_QSGMII && id > 0)
44025 +		return 0;
44033 +	xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_INTR_STS, 0x0);
44034 +	xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_LINK_TIMER_CTRL, 0x1);
44037 +		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL,
44040 +		xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_AN_CTRL,
44044 +		for (i = 0; i < 4; i++) {
44073 +	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
44074 +	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
44077 +	((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE(id) : soc##_GMAC_TXCLK_DLY_DISABLE(id)) | \
44078 +	 (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE(id) : soc##_GMAC_RXCLK_DLY_DISABLE(id)))
44081 +	((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
44082 +	 (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
44084  #define PX30_GRF_GMAC_CON1		0x0904
44090 +#define RK1808_GRF_GMAC_CON0		0X0900
44091 +#define RK1808_GRF_GMAC_CON1		0X0904
44094 +#define RK1808_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
44095 +#define RK1808_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
44108 +#define RK1808_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(0)
44109 +#define RK1808_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
44211  #define RK3128_GRF_MAC_CON0	0x0168
44212  #define RK3128_GRF_MAC_CON1	0x016c
44248 +#define RK3308_GRF_MAC_CON0		0x04a0
44253 +#define RK3308_MAC_SPEED_10M		GRF_CLR_BIT(0)
44254 +#define Rk3308_MAC_SPEED_100M		GRF_BIT(0)
44306  #define RK3328_GRF_MAC_CON0	0x0900
44307  #define RK3328_GRF_MAC_CON1	0x0904
44308  #define RK3328_GRF_MAC_CON2	0x0908
44358 +#define RK3568_GRF_GMAC0_CON0		0X0380
44359 +#define RK3568_GRF_GMAC0_CON1		0X0384
44360 +#define RK3568_GRF_GMAC1_CON0		0X0388
44361 +#define RK3568_GRF_GMAC1_CON1		0X038c
44373 +#define RK3568_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
44374 +#define RK3568_GMAC_TXCLK_DLY_DISABLE		GRF_CLR_BIT(0)
44377 +#define RK3568_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
44378 +#define RK3568_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
44380 +#define RK3568_PIPE_GRF_XPCS_CON0	0X0040
44382 +#define RK3568_PIPE_GRF_XPCS_QGMII_MAC_SEL	GRF_BIT(0)
44497 +#define RK3588_GRF_GMAC_CON7			0X031c
44498 +#define RK3588_GRF_GMAC_CON8			0X0320
44499 +#define RK3588_GRF_GMAC_CON9			0X0324
44506 +#define RK3588_GMAC_CLK_RX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 8)
44507 +#define RK3588_GMAC_CLK_TX_DL_CFG(val)		HIWORD_UPDATE(val, 0xFF, 0)
44510 +#define RK3588_GRF_GMAC_CON0			0X0008
44511 +#define RK3588_GRF_CLK_CON1			0X0070
44583 +	unsigned int val = 0, id = bsp_priv->bus_id;
44635  #define RV1108_GRF_GMAC_CON0		0X0900
44642 +#define RV1126_GRF_GMAC_CON0		0X0070
44643 +#define RV1126_GRF_GMAC_CON1		0X0074
44644 +#define RV1126_GRF_GMAC_CON2		0X0078
44655 +#define RV1126_M0_GMAC_TXCLK_DLY_ENABLE		GRF_BIT(0)
44656 +#define RV1126_M0_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(0)
44663 +#define RV1126_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 8)
44664 +#define RV1126_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0x7F, 0)
44759  #define RK_GRF_MACPHY_CON0		0xb00
44760  #define RK_GRF_MACPHY_CON1		0xb04
44761  #define RK_GRF_MACPHY_CON2		0xb08
44781  		bsp_priv->clk_phy = of_clk_get(plat->phy_node, 0);
44798  	return 0;
44833  	return 0;
44853 -		bsp_priv->tx_delay = 0x30;
44856  		dev_err(dev, "set tx_delay to 0x%x\n",
44862 -		bsp_priv->rx_delay = 0x10;
44865  		dev_err(dev, "set rx_delay to 0x%x\n",
44900 -		bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
44906 -		bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
44912 -		bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
45009 +	unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
45015 +	if (id < 0 || id >= MAX_ETH) {
45021 +	if (ret <= 0 ||
45030 +		if (ret != 0)
45070  	return 0;
45157 +#define T_CSB_P_S		0
45158 +#define T_PGENB_P_S		0
45159 +#define T_LOAD_P_S		0
45160 +#define T_ADDR_P_S		0
45161 +#define T_STROBE_P_S		(0 + 110) /* 1.1us */
45162 +#define T_CSB_P_L		(0 + 110 + 1000 + 20) /* 200ns */
45163 +#define T_PGENB_P_L		(0 + 110 + 1000 + 20)
45164 +#define T_LOAD_P_L		(0 + 110 + 1000 + 20)
45165 +#define T_ADDR_P_L		(0 + 110 + 1000 + 20)
45166 +#define T_STROBE_P_L		(0 + 110 + 1000) /* 10us */
45167 +#define T_CSB_R_S		0
45168 +#define T_PGENB_R_S		0
45169 +#define T_LOAD_R_S		0
45178 +#define T_CSB_P			0x28
45179 +#define T_PGENB_P		0x2c
45180 +#define T_LOAD_P		0x30
45181 +#define T_ADDR_P		0x34
45182 +#define T_STROBE_P		0x38
45183 +#define T_CSB_R			0x3c
45184 +#define T_PGENB_R		0x40
45185 +#define T_LOAD_R		0x44
45186 +#define T_ADDR_R		0x48
45187 +#define T_STROBE_R		0x4c
45189 +#define RK1808_MOD		0x00
45193 +#define RK1808_USER_MODE	BIT(0)
45203  #define RK3288_A_MASK		0x3ff
45242 +	writel(0, base + T_CSB_P);
45243 +	writel(0, base + T_PGENB_P);
45244 +	writel(0, base + T_LOAD_P);
45245 +	writel(0, base + T_ADDR_P);
45246 +	writel(0, base + T_STROBE_P);
45247 +	writel(0, base + T_CSB_R);
45248 +	writel(0, base + T_PGENB_R);
45249 +	writel(0, base + T_LOAD_R);
45250 +	writel(0, base + T_ADDR_R);
45251 +	writel(0, base + T_STROBE_R);
45261 +	int ret, i = 0;
45266 +	if (ret < 0) {
45321 +	if (ret < 0) {
45350 +	return 0;
45362  	if (ret < 0) {
45372 +	return 0;
45385 +	if (ret < 0) {
45418  	return 0;
45422  	int ret, i = 0;
45426  	if (ret < 0) {
45448 +	if (ret < 0) {
45481 +	return 0;
45489  	int ret, i = 0;
45493  	if (ret < 0) {
45515 -	return 0;
45565  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
45597 +	return 0;
45629 +	return 0;
45643 index 596c185b5..0f45d8123 100644
45667 +				   opp->supplies[0].u_volt,
45668 +				   opp->supplies[0].u_volt_min,
45669 +				   opp->supplies[0].u_volt_max);
45676 +	return 0;
45699  	return 0;
45771  #define PCIE_PORT_LINK_CONTROL		0x710
45789  	rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
45833  	  Support for Rockchip USB2.0 PHY with Innosilicon IP block.
45863 +	  Enable this to support the Rockchip PCIe/USB3.0/SATA/QSGMII
45882 +	  Support for Rockchip USB2.0 PHY with NANENG IP block.
45937 +	  Enable this to support the Rockchip USB3.0/DP
45970  #define DATA_LANE_0_SKEW_PHASE_MASK		GENMASK(2, 0)
45971  #define DATA_LANE_0_SKEW_PHASE(x)		UPDATE(x, 2, 0)
45975 +#define PRE_EMPHASIS_DISABLE			0
45978 +#define PLL_POST_DIV_DISABLE			0
45979 +#define DATA_LANE_VOD_RANGE_SET_MASK		GENMASK(3, 0)
45980 +#define DATA_LANE_VOD_RANGE_SET(x)		UPDATE(x, 3, 0)
45983  #define SAMPLE_CLOCK_DIRECTION_FORWARD		0
45985 +#define PLL_OUTPUT_FREQUENCY_DIV_BY_1           0
45989 +#define PLL_MODE_SEL_LVDS_MODE			0
45992 +#define CLOCK_LANE_VOD_RANGE_SET_MASK	GENMASK(3, 0)
45993 +#define CLOCK_LANE_VOD_RANGE_SET(x)	UPDATE(x, 3, 0)
45994 +#define VOD_MIN_RANGE			0x1
45995 +#define VOD_MID_RANGE			0x3
45996 +#define VOD_BIG_RANGE			0x7
45997 +#define VOD_MAX_RANGE			0xf
45999  #define REG_DIG_RSTN_MASK			BIT(0)
46000  #define REG_DIG_RSTN_NORMAL			BIT(0)
46002  #define T_LPX_CNT_MASK				GENMASK(5, 0)
46003  #define T_LPX_CNT(x)				UPDATE(x, 5, 0)
46007  #define T_HS_PREPARE_CNT_MASK			GENMASK(6, 0)
46008  #define T_HS_PREPARE_CNT(x)			UPDATE(x, 6, 0)
46010 -#define T_HS_ZERO_CNT_MASK			GENMASK(5, 0)
46011 -#define T_HS_ZERO_CNT(x)			UPDATE(x, 5, 0)
46012 +#define T_HS_ZERO_CNT_LO_MASK			GENMASK(5, 0)
46013 +#define T_HS_ZERO_CNT_LO(x)			UPDATE(x, 5, 0)
46015  #define T_HS_TRAIL_CNT_MASK			GENMASK(6, 0)
46016  #define T_HS_TRAIL_CNT(x)			UPDATE(x, 6, 0)
46018 -#define T_HS_EXIT_CNT_MASK			GENMASK(4, 0)
46019 -#define T_HS_EXIT_CNT(x)			UPDATE(x, 4, 0)
46020 +#define T_HS_EXIT_CNT_LO_MASK			GENMASK(4, 0)
46021 +#define T_HS_EXIT_CNT_LO(x)			UPDATE(x, 4, 0)
46023 -#define T_CLK_POST_CNT_MASK			GENMASK(3, 0)
46024 -#define T_CLK_POST_CNT(x)			UPDATE(x, 3, 0)
46025 +#define T_CLK_POST_CNT_LO_MASK			GENMASK(3, 0)
46026 +#define T_CLK_POST_CNT_LO(x)			UPDATE(x, 3, 0)
46031  #define T_CLK_PRE_CNT_MASK			GENMASK(3, 0)
46032  #define T_CLK_PRE_CNT(x)			UPDATE(x, 3, 0)
46036  #define T_TA_GO_CNT_MASK			GENMASK(5, 0)
46037  #define T_TA_GO_CNT(x)				UPDATE(x, 5, 0)
46041  #define T_TA_SURE_CNT_MASK			GENMASK(5, 0)
46042  #define T_TA_SURE_CNT(x)			UPDATE(x, 5, 0)
46045  #define DSI_PHY_STATUS		0xb0
46046  #define PHY_LOCK		BIT(0)
46095 +	{ 110, 0x0, 0x20, 0x16, 0x02, 0x22},
46096 +	{ 150, 0x0, 0x06, 0x16, 0x03, 0x45},
46097 +	{ 200, 0x0, 0x18, 0x17, 0x04, 0x0b},
46098 +	{ 250, 0x0, 0x05, 0x17, 0x05, 0x16},
46099 +	{ 300, 0x0, 0x51, 0x18, 0x06, 0x2c},
46100 +	{ 400, 0x0, 0x64, 0x19, 0x07, 0x33},
46101 +	{ 500, 0x0, 0x20, 0x1b, 0x07, 0x4e},
46102 +	{ 600, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
46103 +	{ 700, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
46104 +	{ 800, 0x0, 0x21, 0x1f, 0x09, 0x29},
46105 +	{1000, 0x0, 0x09, 0x20, 0x09, 0x27},
46110 +	{ 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
46111 +	{ 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
46112 +	{ 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
46113 +	{ 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
46114 +	{ 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
46115 +	{ 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
46116 +	{ 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
46117 +	{ 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
46118 +	{ 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
46119 +	{ 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
46120 +	{1000, 0x05, 0x08, 0x20, 0x09, 0x30},
46121 +	{1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
46122 +	{1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
46123 +	{1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
46124 +	{1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
46125 +	{2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
46126 +	{2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
46127 +	{2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
46128 +	{2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
46168 -		{ 110000000, 0x20, 0x16, 0x02, 0x22},
46169 -		{ 150000000, 0x06, 0x16, 0x03, 0x45},
46170 -		{ 200000000, 0x18, 0x17, 0x04, 0x0b},
46171 -		{ 250000000, 0x05, 0x17, 0x05, 0x16},
46172 -		{ 300000000, 0x51, 0x18, 0x06, 0x2c},
46173 -		{ 400000000, 0x64, 0x19, 0x07, 0x33},
46174 -		{ 500000000, 0x20, 0x1b, 0x07, 0x4e},
46175 -		{ 600000000, 0x6a, 0x1d, 0x08, 0x3a},
46176 -		{ 700000000, 0x3e, 0x1e, 0x08, 0x6a},
46177 -		{ 800000000, 0x21, 0x1f, 0x09, 0x29},
46178 -		{1000000000, 0x09, 0x20, 0x09, 0x27},
46194 -	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
46196 +	for (i = 0; i < num_timings; i++)
46209 +	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
46211 +	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
46213 +	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
46215 +	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
46217 +	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
46220 +	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
46228  	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
46231  	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
46239  	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
46243  	phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
46279 -	for (i = 0; i < ARRAY_SIZE(timings); i++)
46306  	wakeup = 0x3ff;
46311  		phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
46313 -		phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
46317 +			phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
46320 +		phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
46322  		phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
46324 -		phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
46326 -		phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
46330 +			phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
46333 +		phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
46337 +			phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
46340 +		phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
46342  		phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
46344  		phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
46346  		phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
46352 -	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
46375 +	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
46381 +	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
46399  	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
46407  	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
46413 +	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
46417  	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
46426 +	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
46429 +	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
46433 +	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
46437 +	phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
46441 +	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
46457  	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
46473  	return 0;
46489  	return 0;
46513 +	return 0;
46524 +	return 0;
46535  	return 0;
46562 -	inno->phy_base = devm_platform_ioremap_resource(pdev, 0);
46605  	return 0;
46667 +#define FILTER_COUNTER		0xF4240
46721 + *	      0: from phy; 1: from grf
46913 +	return 0;
46938  	return 0;
47025 +	int ret = 0;
47131 +		if (rport->id_irq > 0 || rport->otg_mux_irq > 0 ||
47132 +		    rphy->irq > 0) {
47147 +		if ((rport->bvalid_irq > 0 || rport->otg_mux_irq > 0 ||
47148 +		    rphy->irq > 0) && !rport->vbus_always_on) {
47162 +			schedule_delayed_work(&rport->otg_sm_work, 0);
47196 -		return 0;
47209 +		ret = 0;
47239 -	return 0;
47246 +		schedule_delayed_work(&rport->bypass_uart_work, 0);
47258 -		return 0;
47262 +		ret = 0;
47274 -	return 0;
47280 +		schedule_delayed_work(&rport->bypass_uart_work, 0);
47298 +		 rport->bvalid_irq > 0)
47301  	return 0;
47307 +	int ret = 0;
47310 +		return 0;
47321 +	if (ret == 0)
47333 +	int ret = 0;
47403 +	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
47442 +	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
47461 +	if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
47482 +		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
47487 +		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE, 0);
47492 +		rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG, 0);
47561 -		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
47562 +		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0 ||
47563 +		    extcon_get_state(rphy->edev, EXTCON_USB_VBUS_EN) > 0) {
47577  				schedule_delayed_work(&rport->chg_work, 0);
47647 +		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0 ||
47649 +					    EXTCON_USB_VBUS_EN) > 0) {
47660 -			delay = 0;
47671  		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
47754 +				"Fail to read phy_sus reg offset 0x%x, ret %d\n",
47765  		rphy->dcd_retries = 0;
47766 +		rphy->primary_retries = 0;
47772  				delay = 0;
47789  				delay = 0;
47794 -		delay = 0;
47810 +				"Fail to set phy_sus reg offset 0x%x, ret %d\n",
47851  	if (ret < 0)
47855 -	if (ret < 0)
47868 +		if (ret < 0)
48014 -	if (rport->ls_irq < 0) {
48038 -	return 0;
48074 +	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
48098 -		ret = 0;
48143 +	if (rphy->irq > 0)
48144 +		return 0;
48155  	if (rport->otg_mux_irq > 0) {
48168 -		if (rport->bvalid_irq < 0) {
48178 +	if (rport->ls_irq <= 0) {
48206 +		if (rport->bvalid_irq <= 0) {
48231 +		if (rport->id_irq <= 0) {
48336 -	index = 0;
48342 +	return 0;
48435 +	if (rport->port_cfg->bvalid_grf_con.enable != 0)
48466 +	return 0;
48498 +		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
48541 +	rphy->irq = platform_get_irq(pdev, 0);
48549 +	index = 0;
48593 +	index = 0;
48652 +	if (rphy->irq > 0) {
48670 +	return 0;
48689 +	int ret = 0;
48725 +	ret = regmap_write(rphy->grf, 0x298, 0x00040000);
48729 +	return 0;
48734 +	int ret = 0;
48737 +	if (rphy->phy_cfg->reg == 0x760)
48738 +		ret = regmap_write(rphy->grf, 0x76c, 0x00070004);
48748 +	ret = regmap_write(rphy->grf, 0x0, 0x00070004);
48753 +	ret = regmap_write(rphy->grf, 0x30, 0x00070004);
48758 +	ret = regmap_write(rphy->grf, 0x18, 0x00040000);
48762 +	return 0;
48770 +	ret = regmap_write(rphy->grf, 0x2c, 0xffff0400);
48775 +	ret = regmap_write(rphy->grf, 0x0, 0x00070004);
48780 +	ret = regmap_write(rphy->grf, 0x30, 0x00070004);
48785 +	ret = regmap_write(rphy->grf, 0x18, 0x00040000);
48789 +	return 0;
48794 +	unsigned int open_pre_emphasize = 0xffff851f;
48795 +	unsigned int eye_height_tuning = 0xffff68c8;
48796 +	unsigned int compensation_tuning = 0xffff026e;
48797 +	int ret = 0;
48800 +	ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
48801 +	ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
48802 +	ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
48803 +	ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
48806 +	ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
48814 +	int ret = 0;
48816 +	if (rphy->phy_cfg->reg == 0xe450) {
48823 +		ret |= regmap_write(rphy->grf, 0x4480,
48824 +				    GENMASK(17, 16) | 0x0);
48825 +		ret |= regmap_write(rphy->grf, 0x44b4,
48826 +				    GENMASK(17, 16) | 0x0);
48834 +		ret |= regmap_write(rphy->grf, 0x4500,
48835 +				    GENMASK(17, 16) | 0x0);
48836 +		ret |= regmap_write(rphy->grf, 0x4534,
48837 +				    GENMASK(17, 16) | 0x0);
48843 +	if (rphy->phy_cfg->reg == 0xe450) {
48848 +		ret |= regmap_write(rphy->grf, 0x448c,
48849 +				    GENMASK(23, 16) | 0xe3);
48852 +		ret |= regmap_write(rphy->grf, 0x44b0,
48853 +				    GENMASK(18, 16) | 0x07);
48858 +		ret |= regmap_write(rphy->grf, 0x4480,
48859 +				    GENMASK(30, 30) | 0x4000);
48865 +		ret |= regmap_write(rphy->grf, 0x450c,
48866 +				    GENMASK(23, 16) | 0xe3);
48869 +		ret |= regmap_write(rphy->grf, 0x4530,
48870 +				    GENMASK(18, 16) | 0x07);
48875 +		ret |= regmap_write(rphy->grf, 0x4500,
48876 +				    GENMASK(30, 30) | 0x4000);
48885 +	int ret = 0;
48887 +	reg = readl(rphy->phy_base + 0x30);
48889 +	writel(reg & ~BIT(2), rphy->phy_base + 0x30);
48893 +	reg &= ~(0x07 << 0);
48894 +	reg |= (0x04 << 0);
48897 +	reg = readl(rphy->phy_base + 0x0400);
48899 +	reg &= ~(0x07 << 0);
48900 +	reg |= (0x04 << 0);
48901 +	writel(reg, rphy->phy_base + 0x0400);
48903 +	if (rphy->phy_cfg->reg == 0xfe8a0000) {
48905 +		reg = readl(rphy->phy_base + 0x30);
48906 +		reg &= ~(0x07 << 4);
48907 +		reg |= (0x06 << 4);
48908 +		writel(reg, rphy->phy_base + 0x30);
48914 +		ret |= regmap_write(rphy->grf, 0x0048, FILTER_COUNTER);
48920 +		ret |= regmap_write(rphy->grf, 0x004c, FILTER_COUNTER);
48931 +		reg = readl(rphy->phy_base + 0x3c);
48933 +		writel(reg & ~BIT(7), rphy->phy_base + 0x3c);
48935 +		reg = readl(rphy->phy_base + 0x3c);
48937 +		writel(reg | BIT(7), rphy->phy_base + 0x3c);
48940 +	return 0;
48945 +	int ret = 0;
48948 +	ret = regmap_write(rphy->grf, 0x0008,
48949 +			   GENMASK(29, 29) | 0x0000);
48958 +	if (rphy->phy_cfg->reg == 0x0000) {
48965 +		ret |= regmap_write(rphy->grf, 0x000c,
48966 +				    GENMASK(20, 16) | 0x0015);
48969 +		ret |= regmap_write(rphy->grf, 0x0004,
48970 +				   GENMASK(27, 24) | 0x0900);
48972 -	index = 0;
48977 +		ret |= regmap_write(rphy->grf, 0x0008,
48978 +				   GENMASK(20, 19) | 0x0010);
48985 +		ret |= regmap_write(rphy->grf, 0x0010,
48986 +				    GENMASK(17, 16) | 0x0003);
48987 +	} else if (rphy->phy_cfg->reg == 0x4000) {
48994 +		ret |= regmap_write(rphy->grf, 0x000c,
48995 +				    GENMASK(20, 16) | 0x0015);
49003 +		ret |= regmap_write(rphy->grf, 0x0004,
49004 +				   GENMASK(27, 24) | 0x0900);
49007 +		ret |= regmap_write(rphy->grf, 0x0008,
49008 +				   GENMASK(20, 19) | 0x0010);
49011 +		ret |= regmap_write(rphy->grf, 0x0010,
49012 +				    GENMASK(17, 16) | 0x0003);
49013 +	} else if (rphy->phy_cfg->reg == 0x8000) {
49020 +		ret |= regmap_write(rphy->grf, 0x000c,
49021 +				    GENMASK(20, 16) | 0x0014);
49024 +		ret |= regmap_write(rphy->grf, 0x0004,
49025 +				   GENMASK(27, 24) | 0x0900);
49028 +		ret |= regmap_write(rphy->grf, 0x0008,
49029 +				   GENMASK(20, 19) | 0x0010);
49030 +	} else if (rphy->phy_cfg->reg == 0xc000) {
49037 +		ret |= regmap_write(rphy->grf, 0x000c,
49038 +				    GENMASK(20, 16) | 0x0014);
49041 +		ret |= regmap_write(rphy->grf, 0x0004,
49042 +				   GENMASK(27, 24) | 0x0900);
49045 +		ret |= regmap_write(rphy->grf, 0x0008,
49046 +				   GENMASK(20, 19) | 0x0010);
49058 +	int ret = 0;
49064 +	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
49070 +		    (rport->id_irq > 0 || rphy->irq > 0)) {
49087 +		    rport->bvalid_irq > 0)
49114 +		if (wakeup_enable && rport->ls_irq > 0)
49138 +	int ret = 0;
49147 +	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
49153 +		    (rport->id_irq > 0 || rphy->irq > 0)) {
49183 +		    rport->bvalid_irq > 0)
49186 +		if (wakeup_enable && rport->ls_irq > 0)
49208 +		.reg = 0x100,
49210 +		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
49213 +				.phy_sus	= { 0x0100, 8, 0, 0, 0x1d1 },
49214 +				.bvalid_det_en	= { 0x0110, 2, 2, 0, 1 },
49215 +				.bvalid_det_st	= { 0x0114, 2, 2, 0, 1 },
49216 +				.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
49217 +				.bypass_dm_en	= { 0x0108, 2, 2, 0, 1},
49218 +				.bypass_sel	= { 0x0108, 3, 3, 0, 1},
49219 +				.iddig_output	= { 0x0100, 10, 10, 0, 1 },
49220 +				.iddig_en	= { 0x0100, 9, 9, 0, 1 },
49221 +				.idfall_det_en	= { 0x0110, 5, 5, 0, 1 },
49222 +				.idfall_det_st	= { 0x0114, 5, 5, 0, 1 },
49223 +				.idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
49224 +				.idrise_det_en	= { 0x0110, 4, 4, 0, 1 },
49225 +				.idrise_det_st	= { 0x0114, 4, 4, 0, 1 },
49226 +				.idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
49227 +				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
49228 +				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
49229 +				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
49230 +				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
49231 +				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
49232 +				.utmi_iddig	= { 0x0120, 6, 6, 0, 1 },
49233 +				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
49234 +				.vbus_det_en	= { 0x001c, 15, 15, 1, 0 },
49237 +				.phy_sus	= { 0x104, 8, 0, 0, 0x1d1 },
49238 +				.ls_det_en	= { 0x110, 1, 1, 0, 1 },
49239 +				.ls_det_st	= { 0x114, 1, 1, 0, 1 },
49240 +				.ls_det_clr	= { 0x118, 1, 1, 0, 1 },
49241 +				.utmi_ls	= { 0x120, 17, 16, 0, 1 },
49242 +				.utmi_hstdet	= { 0x120, 19, 19, 0, 1 }
49246 +			.chg_mode	= { 0x0100, 8, 0, 0, 0x1d7 },
49247 +			.cp_det		= { 0x0120, 24, 24, 0, 1 },
49248 +			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
49249 +			.dp_det		= { 0x0120, 25, 25, 0, 1 },
49250 +			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
49251 +			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
49252 +			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
49253 +			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
49254 +			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
49255 +			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
49263 +		.reg = 0x17c,
49266 +		.clkout_ctl	= { 0x0190, 15, 15, 1, 0 },
49269 +				.phy_sus	= { 0x017c, 8, 0, 0, 0x1d1 },
49270 +				.bvalid_det_en	= { 0x017c, 14, 14, 0, 1 },
49271 +				.bvalid_det_st	= { 0x017c, 15, 15, 0, 1 },
49272 +				.bvalid_det_clr	= { 0x017c, 15, 15, 0, 1 },
49273 +				.bypass_dm_en	= { 0x0190, 12, 12, 0, 1},
49274 +				.bypass_sel	= { 0x0190, 13, 13, 0, 1},
49275 +				.iddig_output	= { 0x017c, 10, 10, 0, 1 },
49276 +				.iddig_en	= { 0x017c, 9, 9, 0, 1 },
49277 +				.idfall_det_en  = { 0x01a0, 2, 2, 0, 1 },
49278 +				.idfall_det_st  = { 0x01a0, 3, 3, 0, 1 },
49279 +				.idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
49280 +				.idrise_det_en  = { 0x01a0, 0, 0, 0, 1 },
49281 +				.idrise_det_st  = { 0x01a0, 1, 1, 0, 1 },
49282 +				.idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
49283 +				.ls_det_en	= { 0x017c, 12, 12, 0, 1 },
49284 +				.ls_det_st	= { 0x017c, 13, 13, 0, 1 },
49285 +				.ls_det_clr	= { 0x017c, 13, 13, 0, 1 },
49286 +				.utmi_bvalid	= { 0x014c, 5, 5, 0, 1 },
49287 +				.utmi_iddig	= { 0x014c, 8, 8, 0, 1 },
49288 +				.utmi_ls	= { 0x014c, 7, 6, 0, 1 },
49291 +				.phy_sus	= { 0x0194, 8, 0, 0, 0x1d1 },
49292 +				.ls_det_en	= { 0x0194, 14, 14, 0, 1 },
49293 +				.ls_det_st	= { 0x0194, 15, 15, 0, 1 },
49294 +				.ls_det_clr	= { 0x0194, 15, 15, 0, 1 }
49298 +			.chg_mode	= { 0x017c, 8, 0, 0, 0x1d7 },
49299 +			.cp_det		= { 0x02c0, 6, 6, 0, 1 },
49300 +			.dcp_det	= { 0x02c0, 5, 5, 0, 1 },
49301 +			.dp_det		= { 0x02c0, 7, 7, 0, 1 },
49302 +			.idm_sink_en	= { 0x0184, 8, 8, 0, 1 },
49303 +			.idp_sink_en	= { 0x0184, 7, 7, 0, 1 },
49304 +			.idp_src_en	= { 0x0184, 9, 9, 0, 1 },
49305 +			.rdm_pdwn_en	= { 0x0184, 10, 10, 0, 1 },
49306 +			.vdm_src_en	= { 0x0184, 12, 12, 0, 1 },
49307 +			.vdp_src_en	= { 0x0184, 11, 11, 0, 1 },
49315  		.reg = 0x760,
49318  		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
49321 -				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
49322 +				.phy_sus	= { 0x0760, 8, 0, 0, 0x1d1 },
49323  				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
49324  				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
49325  				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
49326 +				.iddig_output   = { 0x0760, 10, 10, 0, 1 },
49327 +				.iddig_en       = { 0x0760, 9, 9, 0, 1 },
49328 +				.idfall_det_en	= { 0x0680, 6, 6, 0, 1 },
49329 +				.idfall_det_st	= { 0x0690, 6, 6, 0, 1 },
49330 +				.idfall_det_clr	= { 0x06a0, 6, 6, 0, 1 },
49331 +				.idrise_det_en	= { 0x0680, 5, 5, 0, 1 },
49332 +				.idrise_det_st	= { 0x0690, 5, 5, 0, 1 },
49333 +				.idrise_det_clr	= { 0x06a0, 5, 5, 0, 1 },
49334  				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
49335  				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
49336  				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
49337  				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
49338 +				.utmi_iddig	= { 0x0480, 1, 1, 0, 1 },
49339  				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
49340 +				.vbus_det_en	= { 0x0788, 15, 15, 1, 0 },
49343 -				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
49344 +				.phy_sus	= { 0x0764, 8, 0, 0, 0x1d1 },
49345  				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
49346  				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
49347  				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
49351 -			.opmode		= { 0x0760, 3, 0, 5, 1 },
49352 +			.chg_mode	= { 0x0760, 8, 0, 0, 0x1d7 },
49353  			.cp_det		= { 0x0884, 4, 4, 0, 1 },
49354  			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
49355  			.dp_det		= { 0x0884, 5, 5, 0, 1 },
49357  		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
49360 -				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
49361 +				.phy_sus	= { 0x804, 8, 0, 0, 0x1d1 },
49362 +				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
49363 +				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
49364 +				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
49367 +				.phy_sus	= { 0x800, 8, 0, 0, 0x1d1 },
49368  				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
49369  				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
49370  				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
49379 +		.reg = 0x100,
49382 +		.clkout_ctl	= { 0x0108, 4, 4, 1, 0 },
49385 +				.phy_sus	= { 0x0100, 8, 0, 0, 0x1d1 },
49386 +				.bvalid_det_en	= { 0x3020, 2, 2, 0, 1 },
49387 +				.bvalid_det_st	= { 0x3024, 2, 2, 0, 1 },
49388 +				.bvalid_det_clr = { 0x3028, 2, 2, 0, 1 },
49389 +				.iddig_output	= { 0x0100, 10, 10, 0, 1 },
49390 +				.iddig_en	= { 0x0100, 9, 9, 0, 1 },
49391 +				.idfall_det_en	= { 0x3020, 5, 5, 0, 1 },
49392 +				.idfall_det_st	= { 0x3024, 5, 5, 0, 1 },
49393 +				.idfall_det_clr = { 0x3028, 5, 5, 0, 1 },
49394 +				.idrise_det_en	= { 0x3020, 4, 4, 0, 1 },
49395 +				.idrise_det_st	= { 0x3024, 4, 4, 0, 1 },
49396 +				.idrise_det_clr = { 0x3028, 4, 4, 0, 1 },
49397 +				.ls_det_en	= { 0x3020, 0, 0, 0, 1 },
49398 +				.ls_det_st	= { 0x3024, 0, 0, 0, 1 },
49399 +				.ls_det_clr	= { 0x3028, 0, 0, 0, 1 },
49400 +				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
49401 +				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
49402 +				.utmi_iddig	= { 0x0120, 6, 6, 0, 1 },
49403 +				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
49404 +				.vbus_det_en	= { 0x001c, 15, 15, 1, 0 },
49407 -				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
49408 -				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
49409 -				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
49410 -				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
49411 +				.phy_sus	= { 0x0104, 8, 0, 0, 0x1d1 },
49412 +				.ls_det_en	= { 0x3020, 1, 1, 0, 1 },
49413 +				.ls_det_st	= { 0x3024, 1, 1, 0, 1 },
49414 +				.ls_det_clr	= { 0x3028, 1, 1, 0, 1 },
49415 +				.utmi_ls	= { 0x120, 17, 16, 0, 1 },
49416 +				.utmi_hstdet	= { 0x120, 19, 19, 0, 1 }
49420 +			.chg_mode	= { 0x0100, 8, 0, 0, 0x1d7 },
49421 +			.cp_det		= { 0x0120, 24, 24, 0, 1 },
49422 +			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
49423 +			.dp_det		= { 0x0120, 25, 25, 0, 1 },
49424 +			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
49425 +			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
49426 +			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
49427 +			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
49428 +			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
49429 +			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
49436  		.reg = 0x100,
49439  		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
49442 -				.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
49443 +				.phy_sus	= { 0x0100, 8, 0, 0, 0x1d1 },
49444  				.bvalid_det_en	= { 0x0110, 2, 2, 0, 1 },
49445  				.bvalid_det_st	= { 0x0114, 2, 2, 0, 1 },
49446  				.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
49447 +				.bypass_bc      = { 0x0008, 14, 14, 0, 1 },
49448 +				.bypass_otg     = { 0x0018, 15, 15, 1, 0 },
49449 +				.iddig_output   = { 0x0100, 10, 10, 0, 1 },
49450 +				.iddig_en       = { 0x0100, 9, 9, 0, 1 },
49451 +				.idfall_det_en	= { 0x0110, 5, 5, 0, 1 },
49452 +				.idfall_det_st	= { 0x0114, 5, 5, 0, 1 },
49453 +				.idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
49454 +				.idrise_det_en	= { 0x0110, 4, 4, 0, 1 },
49455 +				.idrise_det_st	= { 0x0114, 4, 4, 0, 1 },
49456 +				.idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
49457  				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
49458  				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
49459  				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
49460  				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
49461  				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
49462 +				.utmi_iddig	= { 0x0120, 6, 6, 0, 1 },
49463  				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
49464 +				.vbus_det_en	= { 0x001c, 15, 15, 1, 0 },
49467 -				.phy_sus	= { 0x104, 15, 0, 0, 0x1d1 },
49468 +				.phy_sus	= { 0x104, 8, 0, 0, 0x1d1 },
49469 +				.bypass_host	= { 0x048, 15, 15, 1, 0 },
49470  				.ls_det_en	= { 0x110, 1, 1, 0, 1 },
49471  				.ls_det_st	= { 0x114, 1, 1, 0, 1 },
49472  				.ls_det_clr	= { 0x118, 1, 1, 0, 1 },
49477 -			.opmode		= { 0x0100, 3, 0, 5, 1 },
49478 +			.chg_mode	= { 0x0100, 8, 0, 0, 0x1d7 },
49479  			.cp_det		= { 0x0120, 24, 24, 0, 1 },
49480  			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
49481  			.dp_det		= { 0x0120, 25, 25, 0, 1 },
49484  		.reg = 0x700,
49487  		.clkout_ctl	= { 0x0724, 15, 15, 1, 0 },
49490 -				.phy_sus	= { 0x0728, 15, 0, 0, 0x1d1 },
49491 +				.phy_sus	= { 0x0728, 8, 0, 0, 0x1d1 },
49492  				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
49493  				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
49494  				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 },
49501 +		.reg = 0x700,
49503 +		.clkout_ctl	= { 0x0724, 15, 15, 1, 0 },
49506 +				.phy_sus	= { 0x0700, 8, 0, 0, 0x1d1 },
49507 +				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
49508 +				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
49509 +				.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
49510 +				.iddig_output	= { 0x0700, 10, 10, 0, 1 },
49511 +				.iddig_en	= { 0x0700, 9, 9, 0, 1 },
49512 +				.idfall_det_en	= { 0x0680, 6, 6, 0, 1 },
49513 +				.idfall_det_st	= { 0x0690, 6, 6, 0, 1 },
49514 +				.idfall_det_clr	= { 0x06a0, 6, 6, 0, 1 },
49515 +				.idrise_det_en	= { 0x0680, 5, 5, 0, 1 },
49516 +				.idrise_det_st	= { 0x0690, 5, 5, 0, 1 },
49517 +				.idrise_det_clr	= { 0x06a0, 5, 5, 0, 1 },
49518 +				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
49519 +				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
49520 +				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
49521 +				.utmi_bvalid	= { 0x04bc, 23, 23, 0, 1 },
49522 +				.utmi_iddig     = { 0x04bc, 26, 26, 0, 1 },
49523 +				.utmi_ls	= { 0x04bc, 25, 24, 0, 1 },
49524 +				.vbus_det_en    = { 0x079c, 15, 15, 1, 0 },
49527 +				.phy_sus	= { 0x0728, 15, 0, 0, 0x1d1 },
49528 +				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
49529 +				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
49530 +				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
49534 +			.chg_mode	= { 0x0700, 8, 0, 0, 0x1d7 },
49535 +			.cp_det		= { 0x04b8, 30, 30, 0, 1 },
49536 +			.dcp_det	= { 0x04b8, 29, 29, 0, 1 },
49537 +			.dp_det		= { 0x04b8, 31, 31, 0, 1 },
49538 +			.idm_sink_en	= { 0x0718, 8, 8, 0, 1 },
49539 +			.idp_sink_en	= { 0x0718, 7, 7, 0, 1 },
49540 +			.idp_src_en	= { 0x0718, 9, 9, 0, 1 },
49541 +			.rdm_pdwn_en	= { 0x0718, 10, 10, 0, 1 },
49542 +			.vdm_src_en	= { 0x0718, 12, 12, 0, 1 },
49543 +			.vdp_src_en	= { 0x0718, 11, 11, 0, 1 },
49551  		.reg		= 0xe450,
49554  		.clkout_ctl	= { 0xe450, 4, 4, 1, 0 },
49557 -				.phy_sus	= { 0xe454, 1, 0, 2, 1 },
49558 +				.phy_sus = { 0xe454, 8, 0, 0x052, 0x1d1 },
49559  				.bvalid_det_en	= { 0xe3c0, 3, 3, 0, 1 },
49560  				.bvalid_det_st	= { 0xe3e0, 3, 3, 0, 1 },
49561  				.bvalid_det_clr	= { 0xe3d0, 3, 3, 0, 1 },
49562 +				.bypass_dm_en   = { 0xe450, 2, 2, 0, 1 },
49563 +				.bypass_sel     = { 0xe450, 3, 3, 0, 1 },
49564 +				.iddig_output	= { 0xe454, 10, 10, 0, 1 },
49565 +				.iddig_en	= { 0xe454, 9, 9, 0, 1 },
49566 +				.idfall_det_en	= { 0xe3c0, 5, 5, 0, 1 },
49567 +				.idfall_det_st	= { 0xe3e0, 5, 5, 0, 1 },
49568 +				.idfall_det_clr	= { 0xe3d0, 5, 5, 0, 1 },
49569 +				.idrise_det_en	= { 0xe3c0, 4, 4, 0, 1 },
49570 +				.idrise_det_st	= { 0xe3e0, 4, 4, 0, 1 },
49571 +				.idrise_det_clr	= { 0xe3d0, 4, 4, 0, 1 },
49572 +				.ls_det_en	= { 0xe3c0, 2, 2, 0, 1 },
49573 +				.ls_det_st	= { 0xe3e0, 2, 2, 0, 1 },
49574 +				.ls_det_clr	= { 0xe3d0, 2, 2, 0, 1 },
49575  				.utmi_avalid	= { 0xe2ac, 7, 7, 0, 1 },
49576  				.utmi_bvalid	= { 0xe2ac, 12, 12, 0, 1 },
49577 +				.utmi_iddig     = { 0xe2ac, 8, 8, 0, 1 },
49578 +				.utmi_ls	= { 0xe2ac, 14, 13, 0, 1 },
49579 +				.vbus_det_en    = { 0x449c, 15, 15, 1, 0 },
49582  				.phy_sus	= { 0xe458, 1, 0, 0x2, 0x1 },
49587 -			.opmode		= { 0xe454, 3, 0, 5, 1 },
49588 +			.chg_mode	= { 0xe454, 8, 0, 0, 0x1d7 },
49589  			.cp_det		= { 0xe2ac, 2, 2, 0, 1 },
49590  			.dcp_det	= { 0xe2ac, 1, 1, 0, 1 },
49591  			.dp_det		= { 0xe2ac, 0, 0, 0, 1 },
49594  		.reg		= 0xe460,
49597  		.clkout_ctl	= { 0xe460, 4, 4, 1, 0 },
49600 -				.phy_sus        = { 0xe464, 1, 0, 2, 1 },
49601 +				.phy_sus = { 0xe464, 8, 0, 0x052, 0x1d1 },
49602  				.bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
49603  				.bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
49604  				.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
49605 +				.iddig_output	= { 0xe464, 10, 10, 0, 1 },
49606 +				.iddig_en	= { 0xe464, 9, 9, 0, 1 },
49607 +				.idfall_det_en	= { 0xe3c0, 10, 10, 0, 1 },
49608 +				.idfall_det_st	= { 0xe3e0, 10, 10, 0, 1 },
49609 +				.idfall_det_clr	= { 0xe3d0, 10, 10, 0, 1 },
49610 +				.idrise_det_en	= { 0xe3c0, 9, 9, 0, 1 },
49611 +				.idrise_det_st	= { 0xe3e0, 9, 9, 0, 1 },
49612 +				.idrise_det_clr	= { 0xe3d0, 9, 9, 0, 1 },
49613 +				.ls_det_en	= { 0xe3c0, 7, 7, 0, 1 },
49614 +				.ls_det_st	= { 0xe3e0, 7, 7, 0, 1 },
49615 +				.ls_det_clr	= { 0xe3d0, 7, 7, 0, 1 },
49616  				.utmi_avalid	= { 0xe2ac, 10, 10, 0, 1 },
49617  				.utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
49618 +				.utmi_iddig     = { 0xe2ac, 11, 11, 0, 1 },
49619 +				.utmi_ls	= { 0xe2ac, 18, 17, 0, 1 },
49620 +				.vbus_det_en    = { 0x451c, 15, 15, 1, 0 },
49623  				.phy_sus	= { 0xe468, 1, 0, 0x2, 0x1 },
49625  				.utmi_hstdet	= { 0xe2ac, 27, 27, 0, 1 }
49629 +			.chg_mode	= { 0xe464, 8, 0, 0, 0x1d7 },
49630 +			.cp_det		= { 0xe2ac, 5, 5, 0, 1 },
49631 +			.dcp_det	= { 0xe2ac, 4, 4, 0, 1 },
49632 +			.dp_det		= { 0xe2ac, 3, 3, 0, 1 },
49633 +			.idm_sink_en	= { 0xe460, 8, 8, 0, 1 },
49634 +			.idp_sink_en	= { 0xe460, 7, 7, 0, 1 },
49635 +			.idp_src_en	= { 0xe460, 9, 9, 0, 1 },
49636 +			.rdm_pdwn_en	= { 0xe460, 10, 10, 0, 1 },
49637 +			.vdm_src_en	= { 0xe460, 12, 12, 0, 1 },
49638 +			.vdp_src_en	= { 0xe460, 11, 11, 0, 1 },
49646 +		.reg = 0xfe8a0000,
49650 +		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
49653 +				.phy_sus	= { 0x0000, 8, 0, 0, 0x1d1 },
49654 +				.bvalid_det_en	= { 0x0080, 2, 2, 0, 1 },
49655 +				.bvalid_det_st	= { 0x0084, 2, 2, 0, 1 },
49656 +				.bvalid_det_clr = { 0x0088, 2, 2, 0, 1 },
49657 +				.bvalid_grf_con	= { 0x0008, 15, 14, 0, 3 },
49658 +				.bypass_dm_en	= { 0x0008, 2, 2, 0, 1},
49659 +				.bypass_sel	= { 0x0008, 3, 3, 0, 1},
49660 +				.iddig_output	= { 0x0000, 10, 10, 0, 1 },
49661 +				.iddig_en	= { 0x0000, 9, 9, 0, 1 },
49662 +				.idfall_det_en	= { 0x0080, 5, 5, 0, 1 },
49663 +				.idfall_det_st	= { 0x0084, 5, 5, 0, 1 },
49664 +				.idfall_det_clr = { 0x0088, 5, 5, 0, 1 },
49665 +				.idrise_det_en	= { 0x0080, 4, 4, 0, 1 },
49666 +				.idrise_det_st	= { 0x0084, 4, 4, 0, 1 },
49667 +				.idrise_det_clr = { 0x0088, 4, 4, 0, 1 },
49668 +				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
49669 +				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
49670 +				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
49671 +				.utmi_avalid	= { 0x00c0, 10, 10, 0, 1 },
49672 +				.utmi_bvalid	= { 0x00c0, 9, 9, 0, 1 },
49673 +				.utmi_iddig	= { 0x00c0, 6, 6, 0, 1 },
49674 +				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },
49678 +				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d2 },
49679 +				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
49680 +				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
49681 +				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
49682 +				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
49683 +				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
49687 +			.chg_mode	= { 0x0000, 8, 0, 0, 0x1d7 },
49688 +			.cp_det		= { 0x00c0, 24, 24, 0, 1 },
49689 +			.dcp_det	= { 0x00c0, 23, 23, 0, 1 },
49690 +			.dp_det		= { 0x00c0, 25, 25, 0, 1 },
49691 +			.idm_sink_en	= { 0x0008, 8, 8, 0, 1 },
49692 +			.idp_sink_en	= { 0x0008, 7, 7, 0, 1 },
49693 +			.idp_src_en	= { 0x0008, 9, 9, 0, 1 },
49694 +			.rdm_pdwn_en	= { 0x0008, 10, 10, 0, 1 },
49695 +			.vdm_src_en	= { 0x0008, 12, 12, 0, 1 },
49696 +			.vdp_src_en	= { 0x0008, 11, 11, 0, 1 },
49700 +		.reg = 0xfe8b0000,
49703 +		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
49706 +				.phy_sus	= { 0x0000, 8, 0, 0x1d2, 0x1d1 },
49707 +				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
49708 +				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
49709 +				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
49710 +				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },
49711 +				.utmi_hstdet	= { 0x00c0, 7, 7, 0, 1 }
49714 +				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d1 },
49715 +				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
49716 +				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
49717 +				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
49718 +				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
49719 +				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
49728 +		.reg = 0x0000,
49731 +		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
49734 +				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
49735 +				.bvalid_det_en	= { 0x0080, 1, 1, 0, 1 },
49736 +				.bvalid_det_st	= { 0x0084, 1, 1, 0, 1 },
49737 +				.bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
49738 +				.bvalid_grf_con	= { 0x0010, 3, 2, 0, 3 },
49739 +				.bypass_dm_en	= { 0x000c, 5, 5, 0, 1 },
49740 +				.bypass_sel	= { 0x000c, 6, 6, 0, 1 },
49741 +				.iddig_output	= { 0x0010, 0, 0, 0, 1 },
49742 +				.iddig_en	= { 0x0010, 1, 1, 0, 1 },
49743 +				.idfall_det_en	= { 0x0080, 4, 4, 0, 1 },
49744 +				.idfall_det_st	= { 0x0084, 4, 4, 0, 1 },
49745 +				.idfall_det_clr = { 0x0088, 4, 4, 0, 1 },
49746 +				.idrise_det_en	= { 0x0080, 3, 3, 0, 1 },
49747 +				.idrise_det_st	= { 0x0084, 3, 3, 0, 1 },
49748 +				.idrise_det_clr = { 0x0088, 3, 3, 0, 1 },
49749 +				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
49750 +				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
49751 +				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
49752 +				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
49753 +				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
49754 +				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
49755 +				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
49756 +				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
49757 +				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
49758 +				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
49759 +				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
49760 +				.utmi_iddig	= { 0x00c0, 5, 5, 0, 1 },
49761 +				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
49765 +			.chg_mode	= { 0x0008, 2, 2, 0, 1 },
49766 +			.cp_det		= { 0x00c0, 0, 0, 0, 1 },
49767 +			.dcp_det	= { 0x00c0, 0, 0, 0, 1 },
49768 +			.dp_det		= { 0x00c0, 1, 1, 1, 0 },
49769 +			.idm_sink_en	= { 0x0008, 5, 5, 1, 0 },
49770 +			.idp_sink_en	= { 0x0008, 5, 5, 0, 1 },
49771 +			.idp_src_en	= { 0x0008, 14, 14, 0, 1 },
49772 +			.rdm_pdwn_en	= { 0x0008, 14, 14, 0, 1 },
49773 +			.vdm_src_en	= { 0x0008, 7, 6, 0, 3 },
49774 +			.vdp_src_en	= { 0x0008, 7, 6, 0, 3 },
49778 +		.reg = 0x4000,
49781 +		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
49785 +				.phy_sus	= { 0x000c, 11, 11, 0, 0 },
49786 +				.bvalid_det_en	= { 0x0080, 1, 1, 0, 1 },
49787 +				.bvalid_det_st	= { 0x0084, 1, 1, 0, 1 },
49788 +				.bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
49789 +				.bypass_dm_en	= { 0x000c, 5, 5, 0, 1 },
49790 +				.bypass_sel	= { 0x000c, 6, 6, 0, 1 },
49791 +				.iddig_output	= { 0x0010, 0, 0, 0, 1 },
49792 +				.iddig_en	= { 0x0010, 1, 1, 0, 1 },
49793 +				.idfall_det_en	= { 0x0080, 4, 4, 0, 1 },
49794 +				.idfall_det_st	= { 0x0084, 4, 4, 0, 1 },
49795 +				.idfall_det_clr = { 0x0088, 4, 4, 0, 1 },
49796 +				.idrise_det_en	= { 0x0080, 3, 3, 0, 1 },
49797 +				.idrise_det_st	= { 0x0084, 3, 3, 0, 1 },
49798 +				.idrise_det_clr = { 0x0088, 3, 3, 0, 1 },
49799 +				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
49800 +				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
49801 +				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
49802 +				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
49803 +				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
49804 +				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
49805 +				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
49806 +				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
49807 +				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
49808 +				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
49809 +				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
49810 +				.utmi_iddig	= { 0x00c0, 5, 5, 0, 1 },
49811 +				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
49815 +			.chg_mode	= { 0x0008, 2, 2, 0, 1 },
49816 +			.cp_det		= { 0x00c0, 0, 0, 0, 1 },
49817 +			.dcp_det	= { 0x00c0, 0, 0, 0, 1 },
49818 +			.dp_det		= { 0x00c0, 1, 1, 1, 0 },
49819 +			.idm_sink_en	= { 0x0008, 5, 5, 1, 0 },
49820 +			.idp_sink_en	= { 0x0008, 5, 5, 0, 1 },
49821 +			.idp_src_en	= { 0x0008, 14, 14, 0, 1 },
49822 +			.rdm_pdwn_en	= { 0x0008, 14, 14, 0, 1 },
49823 +			.vdm_src_en	= { 0x0008, 7, 6, 0, 3 },
49824 +			.vdp_src_en	= { 0x0008, 7, 6, 0, 3 },
49828 +		.reg = 0x8000,
49831 +		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
49834 +				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
49835 +				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
49836 +				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
49837 +				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
49838 +				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
49839 +				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
49840 +				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
49841 +				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
49842 +				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
49843 +				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
49844 +				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
49849 +		.reg = 0xc000,
49852 +		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
49855 +				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
49856 +				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
49857 +				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
49858 +				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
49859 +				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
49860 +				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
49861 +				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
49862 +				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
49863 +				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
49864 +				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
49865 +				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
49875 -			.opmode		= { 0x0100, 3, 0, 5, 1 },
49876 +			.chg_mode	= { 0x0100, 8, 0, 0, 0x1d7 },
49877  			.cp_det		= { 0x0804, 1, 1, 0, 1 },
49878  			.dcp_det	= { 0x0804, 0, 0, 0, 1 },
49879  			.dp_det		= { 0x0804, 2, 2, 0, 1 },
49945  #define CMN_SSM_BANDGAP			(0x21 << 2)
49946  #define CMN_SSM_BIAS			(0x22 << 2)
49948  #define RX_DIAG_SIGDET_TUNE(n)		((0x81dc | ((n) << 9)) << 2)
49949  #define RX_DIAG_SC2C_DELAY		(0x81e1 << 2)
49951 -#define PMA_LANE_CFG			(0xc000 << 2)
49952 +#define PHY_PMA_LANE_CFG		(0xc000 << 2)
49953 +#define PMA_LANE3_DP_LANE_SEL(x)	(((x) & 0x3) << 14)
49954 +#define PMA_LANE3_INTERFACE_SEL(x)	(((x) & 0x1) << 12)
49955 +#define PMA_LANE2_DP_LANE_SEL(x)	(((x) & 0x3) << 10)
49956 +#define PMA_LANE2_INTERFACE_SEL(x)	(((x) & 0x1) << 8)
49957 +#define PMA_LANE1_DP_LANE_SEL(x)	(((x) & 0x3) << 6)
49958 +#define PMA_LANE1_INTERFACE_SEL(x)	(((x) & 0x1) << 4)
49959 +#define PMA_LANE0_DP_LANE_SEL(x)	(((x) & 0x3) << 2)
49960 +#define PMA_LANE0_INTERFACE_SEL(x)	(((x) & 0x1) << 0)
49961  #define PIPE_CMN_CTRL1			(0xc001 << 2)
49962  #define PIPE_CMN_CTRL2			(0xc002 << 2)
49963  #define PIPE_COM_LOCK_CFG1		(0xc003 << 2)
49964  #define PIPE_COM_LOCK_CFG2		(0xc004 << 2)
49965  #define PIPE_RCV_DET_INH		(0xc005 << 2)
49966 -#define DP_MODE_CTL			(0xc008 << 2)
49967 +#define PHY_DP_MODE_CTL			(0xc008 << 2)
49975 +#define PHY_DP_POWER_STATE_MASK		GENMASK(3, 0)
49976 +#define PHY_DP_CLK_CTL			(0xc009 << 2)
49979 +#define DP_PLL_CLOCK_DISABLE		0
49981 +#define DP_PLL_ENABLE_MASK		BIT(0)
49982 +#define DP_PLL_ENABLE			BIT(0)
49983 +#define DP_PLL_DISABLE			0
49984  #define DP_CLK_CTL			(0xc009 << 2)
49985  #define STS				(0xc00F << 2)
49986  #define PHY_ISO_CMN_CTRL		(0xc010 << 2)
49988   * clock 0: PLL 0 div 1
49991 -#define CLK_PLL_CONFIG			0X30
49992 +#define CLK_PLL1_DIV1			0x20
49993 +#define CLK_PLL1_DIV2			0x30
49994  #define CLK_PLL_MASK			0x33
49996  #define CMN_READY			BIT(0)
50001  #define DP_PLL_ENABLE			BIT(0)
50005 +#define DP_PLL_DATA_RATE_MASK		0xff00
50009 -#define DP_MODE_ENTER_A0		0xc101
50010 -#define DP_MODE_ENTER_A2		0xc104
50011 +#define DP_MODE_MASK			0xf
50012 +#define DP_MODE_ENTER_A0		BIT(0)
50054  	{ 0x8,		CMN_DIAG_PLL0_LF_PROG },
50058 -	{ 0xf0,		CMN_PLL1_VCOCAL_INIT },
50059 -	{ 0x18,		CMN_PLL1_VCOCAL_ITER },
50060 -	{ 0x30b9,	CMN_PLL1_VCOCAL_START },
50061 -	{ 0x21c,	CMN_PLL1_INTDIV },
50062 -	{ 0,		CMN_PLL1_FRACDIV },
50063 -	{ 0x5,		CMN_PLL1_HIGH_THR },
50064 -	{ 0x35,		CMN_PLL1_SS_CTRL1 },
50065 -	{ 0x7f1e,	CMN_PLL1_SS_CTRL2 },
50066 -	{ 0x20,		CMN_PLL1_DSM_DIAG },
50067 -	{ 0,		CMN_PLLSM1_USER_DEF_CTRL },
50068 -	{ 0,		CMN_DIAG_PLL1_OVRD },
50069 -	{ 0,		CMN_DIAG_PLL1_FBH_OVRD },
50070 -	{ 0,		CMN_DIAG_PLL1_FBL_OVRD },
50071 -	{ 0x6,		CMN_DIAG_PLL1_V2I_TUNE },
50072 -	{ 0x45,		CMN_DIAG_PLL1_CP_TUNE },
50073 -	{ 0x8,		CMN_DIAG_PLL1_LF_PROG },
50074 -	{ 0x100,	CMN_DIAG_PLL1_PTATIS_TUNE1 },
50075 -	{ 0x7,		CMN_DIAG_PLL1_PTATIS_TUNE2 },
50076 -	{ 0x4,		CMN_DIAG_PLL1_INCLK_CTRL },
50078 +	{ 0x00f0, CMN_PLL1_VCOCAL_INIT },
50079 +	{ 0x0018, CMN_PLL1_VCOCAL_ITER },
50080 +	{ 0x30b9, CMN_PLL1_VCOCAL_START },
50081 +	{ 0x0087, CMN_PLL1_INTDIV },
50082 +	{ 0x0000, CMN_PLL1_FRACDIV },
50083 +	{ 0x0022, CMN_PLL1_HIGH_THR },
50084 +	{ 0x8000, CMN_PLL1_SS_CTRL1 },
50085 +	{ 0x0000, CMN_PLL1_SS_CTRL2 },
50086 +	{ 0x0020, CMN_PLL1_DSM_DIAG },
50087 +	{ 0x0000, CMN_PLLSM1_USER_DEF_CTRL },
50088 +	{ 0x0000, CMN_DIAG_PLL1_OVRD },
50089 +	{ 0x0000, CMN_DIAG_PLL1_FBH_OVRD },
50090 +	{ 0x0000, CMN_DIAG_PLL1_FBL_OVRD },
50091 +	{ 0x0006, CMN_DIAG_PLL1_V2I_TUNE },
50092 +	{ 0x0045, CMN_DIAG_PLL1_CP_TUNE },
50093 +	{ 0x0008, CMN_DIAG_PLL1_LF_PROG },
50094 +	{ 0x0100, CMN_DIAG_PLL1_PTATIS_TUNE1 },
50095 +	{ 0x0007, CMN_DIAG_PLL1_PTATIS_TUNE2 },
50096 +	{ 0x0001, CMN_DIAG_PLL1_INCLK_CTRL },
50100 +	{ 0x00f0, CMN_PLL1_VCOCAL_INIT },
50101 +	{ 0x0018, CMN_PLL1_VCOCAL_ITER },
50102 +	{ 0x30b9, CMN_PLL1_VCOCAL_START },
50103 +	{ 0x0086, CMN_PLL1_INTDIV },
50104 +	{ 0xf915, CMN_PLL1_FRACDIV },
50105 +	{ 0x0022, CMN_PLL1_HIGH_THR },
50106 +	{ 0x0140, CMN_PLL1_SS_CTRL1 },
50107 +	{ 0x7f03, CMN_PLL1_SS_CTRL2 },
50108 +	{ 0x0020, CMN_PLL1_DSM_DIAG },
50109 +	{ 0x0000, CMN_PLLSM1_USER_DEF_CTRL },
50110 +	{ 0x0000, CMN_DIAG_PLL1_OVRD },
50111 +	{ 0x0000, CMN_DIAG_PLL1_FBH_OVRD },
50112 +	{ 0x0000, CMN_DIAG_PLL1_FBL_OVRD },
50113 +	{ 0x0006, CMN_DIAG_PLL1_V2I_TUNE },
50114 +	{ 0x0045, CMN_DIAG_PLL1_CP_TUNE },
50115 +	{ 0x0008, CMN_DIAG_PLL1_LF_PROG },
50116 +	{ 0x0100, CMN_DIAG_PLL1_PTATIS_TUNE1 },
50117 +	{ 0x0007, CMN_DIAG_PLL1_PTATIS_TUNE2 },
50118 +	{ 0x0001, CMN_DIAG_PLL1_INCLK_CTRL },
50122 +	{ 0x00f0, CMN_PLL1_VCOCAL_INIT },
50123 +	{ 0x0018, CMN_PLL1_VCOCAL_ITER },
50124 +	{ 0x30b4, CMN_PLL1_VCOCAL_START },
50125 +	{ 0x00e1, CMN_PLL1_INTDIV },
50126 +	{ 0x0000, CMN_PLL1_FRACDIV },
50127 +	{ 0x0005, CMN_PLL1_HIGH_THR },
50128 +	{ 0x8000, CMN_PLL1_SS_CTRL1 },
50129 +	{ 0x0000, CMN_PLL1_SS_CTRL2 },
50130 +	{ 0x0020, CMN_PLL1_DSM_DIAG },
50131 +	{ 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
50132 +	{ 0x0000, CMN_DIAG_PLL1_OVRD },
50133 +	{ 0x0000, CMN_DIAG_PLL1_FBH_OVRD },
50134 +	{ 0x0000, CMN_DIAG_PLL1_FBL_OVRD },
50135 +	{ 0x0007, CMN_DIAG_PLL1_V2I_TUNE },
50136 +	{ 0x0045, CMN_DIAG_PLL1_CP_TUNE },
50137 +	{ 0x0008, CMN_DIAG_PLL1_LF_PROG },
50138 +	{ 0x0001, CMN_DIAG_PLL1_PTATIS_TUNE1 },
50139 +	{ 0x0001, CMN_DIAG_PLL1_PTATIS_TUNE2 },
50140 +	{ 0x0001, CMN_DIAG_PLL1_INCLK_CTRL },
50144 +	{ 0x00f0, CMN_PLL1_VCOCAL_INIT },
50145 +	{ 0x0018, CMN_PLL1_VCOCAL_ITER },
50146 +	{ 0x30b4, CMN_PLL1_VCOCAL_START },
50147 +	{ 0x00e0, CMN_PLL1_INTDIV },
50148 +	{ 0xf479, CMN_PLL1_FRACDIV },
50149 +	{ 0x0038, CMN_PLL1_HIGH_THR },
50150 +	{ 0x0204, CMN_PLL1_SS_CTRL1 },
50151 +	{ 0x7f03, CMN_PLL1_SS_CTRL2 },
50152 +	{ 0x0020, CMN_PLL1_DSM_DIAG },
50153 +	{ 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
50154 +	{ 0x0000, CMN_DIAG_PLL1_OVRD },
50155 +	{ 0x0000, CMN_DIAG_PLL1_FBH_OVRD },
50156 +	{ 0x0000, CMN_DIAG_PLL1_FBL_OVRD },
50157 +	{ 0x0007, CMN_DIAG_PLL1_V2I_TUNE },
50158 +	{ 0x0045, CMN_DIAG_PLL1_CP_TUNE },
50159 +	{ 0x0008, CMN_DIAG_PLL1_LF_PROG },
50160 +	{ 0x0001, CMN_DIAG_PLL1_PTATIS_TUNE1 },
50161 +	{ 0x0001, CMN_DIAG_PLL1_PTATIS_TUNE2 },
50162 +	{ 0x0001, CMN_DIAG_PLL1_INCLK_CTRL },
50166 +	{ 0x00f0, CMN_PLL1_VCOCAL_INIT },
50167 +	{ 0x0018, CMN_PLL1_VCOCAL_ITER },
50168 +	{ 0x30b4, CMN_PLL1_VCOCAL_START },
50169 +	{ 0x00e1, CMN_PLL1_INTDIV },
50170 +	{ 0x0000, CMN_PLL1_FRACDIV },
50171 +	{ 0x0005, CMN_PLL1_HIGH_THR },
50172 +	{ 0x8000, CMN_PLL1_SS_CTRL1 },
50173 +	{ 0x0000, CMN_PLL1_SS_CTRL2 },
50174 +	{ 0x0020, CMN_PLL1_DSM_DIAG },
50175 +	{ 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
50176 +	{ 0x0000, CMN_DIAG_PLL1_OVRD },
50177 +	{ 0x0000, CMN_DIAG_PLL1_FBH_OVRD },
50178 +	{ 0x0000, CMN_DIAG_PLL1_FBL_OVRD },
50179 +	{ 0x0007, CMN_DIAG_PLL1_V2I_TUNE },
50180 +	{ 0x0045, CMN_DIAG_PLL1_CP_TUNE },
50181 +	{ 0x0008, CMN_DIAG_PLL1_LF_PROG },
50182 +	{ 0x0001, CMN_DIAG_PLL1_PTATIS_TUNE1 },
50183 +	{ 0x0001, CMN_DIAG_PLL1_PTATIS_TUNE2 },
50184 +	{ 0x0001, CMN_DIAG_PLL1_INCLK_CTRL },
50188 +	{ 0x00f0, CMN_PLL1_VCOCAL_INIT },
50189 +	{ 0x0018, CMN_PLL1_VCOCAL_ITER },
50190 +	{ 0x30b4, CMN_PLL1_VCOCAL_START },
50191 +	{ 0x00e0, CMN_PLL1_INTDIV },
50192 +	{ 0xf479, CMN_PLL1_FRACDIV },
50193 +	{ 0x0038, CMN_PLL1_HIGH_THR },
50194 +	{ 0x0204, CMN_PLL1_SS_CTRL1 },
50195 +	{ 0x7f03, CMN_PLL1_SS_CTRL2 },
50196 +	{ 0x0020, CMN_PLL1_DSM_DIAG },
50197 +	{ 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
50198 +	{ 0x0000, CMN_DIAG_PLL1_OVRD },
50199 +	{ 0x0000, CMN_DIAG_PLL1_FBH_OVRD },
50200 +	{ 0x0000, CMN_DIAG_PLL1_FBL_OVRD },
50201 +	{ 0x0007, CMN_DIAG_PLL1_V2I_TUNE },
50202 +	{ 0x0045, CMN_DIAG_PLL1_CP_TUNE },
50203 +	{ 0x0008, CMN_DIAG_PLL1_LF_PROG },
50204 +	{ 0x0001, CMN_DIAG_PLL1_PTATIS_TUNE1 },
50205 +	{ 0x0001, CMN_DIAG_PLL1_PTATIS_TUNE2 },
50206 +	{ 0x0001, CMN_DIAG_PLL1_INCLK_CTRL },
50216 +	{{ .swing = 0x2a, .pe = 0x00 },
50217 +	 { .swing = 0x1f, .pe = 0x15 },
50218 +	 { .swing = 0x14, .pe = 0x22 },
50219 +	 { .swing = 0x02, .pe = 0x2b } },
50221 +	{{ .swing = 0x21, .pe = 0x00 },
50222 +	 { .swing = 0x12, .pe = 0x15 },
50223 +	 { .swing = 0x02, .pe = 0x22 },
50224 +	 { .swing = 0,    .pe = 0 } },
50226 +	{{ .swing = 0x15, .pe = 0x00 },
50227 +	 { .swing = 0x00, .pe = 0x15 },
50228 +	 { .swing = 0,    .pe = 0 },
50229 +	 { .swing = 0,    .pe = 0 } },
50265 +	if (ret < 0) {
50270 +	return 0;
50304 + *	  0	       ML1     SSTX    ML2     SSTX    ML2     SSTX
50399 -	for (i = 0; i < ARRAY_SIZE(dp_pll_cfg); i++)
50401 +	for (i = 0; i < cfg_size; i++)
50407  	writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
50417  	writel(0xbefc, tcphy->base + XCVR_PSM_RCTRL(lane));
50418  	writel(0x6799, tcphy->base + TX_PSC_A0(lane));
50420  	writel(0x98, tcphy->base + TX_PSC_A2(lane));
50421  	writel(0x98, tcphy->base + TX_PSC_A3(lane));
50423 -	writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
50424 -	writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_001(lane));
50425 -	writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_010(lane));
50426 -	writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_011(lane));
50427 -	writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_100(lane));
50428 -	writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_101(lane));
50429 -	writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_110(lane));
50430 -	writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_111(lane));
50431 -	writel(0, tcphy->base + TX_TXCC_CPOST_MULT_10(lane));
50432 -	writel(0, tcphy->base + TX_TXCC_CPOST_MULT_01(lane));
50433 -	writel(0, tcphy->base + TX_TXCC_CPOST_MULT_00(lane));
50434 -	writel(0, tcphy->base + TX_TXCC_CPOST_MULT_11(lane));
50436 -	writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
50437 -	writel(0x400, tcphy->base + TX_DIAG_TX_DRV(lane));
50440 -	rdata = (rdata & 0x8fff) | 0x6000;
50447 +	if (swing == 2 && pre_emp == 0 && link_rate != 540000) {
50448 +		writel(0x700, tcphy->base + TX_DIAG_TX_DRV(lane));
50449 +		writel(0x13c, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
50451 +		writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
50452 +		writel(0x0400, tcphy->base + TX_DIAG_TX_DRV(lane));
50456 +	val = val & 0x8fff;
50480 +		for (i = 0; i < 4; i++)
50484 +			tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 0);
50492 +	return 0;
50531 +	return 0;
50583 +	cmn_diag_hsclk_sel &= ~(GENMASK(5, 4) | GENMASK(1, 0));
50590 +		cmn_diag_hsclk_sel |= (3 << 4) | (0 << 0);
50598 +		cmn_diag_hsclk_sel |= (3 << 4) | (0 << 0);
50606 +		cmn_diag_hsclk_sel |= (2 << 4) | (0 << 0);
50621 +	for (i = 0; i < cfg_size; i++)
50633 +	if (ret < 0) {
50666 +	return 0;
50686 +	return 0;
50702  		for (i = 0; i < 4; i++)
50706 +			tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, i);
50714 -			tcphy_dp_cfg_lane(tcphy, 0);
50716 +			tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 0);
50717 +			tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 1);
50719  			tcphy_tx_usb3_cfg_lane(tcphy, 0);
50723 +			tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 2);
50724 +			tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 3);
50752 -	return 0;
50760  	int timeout, new_mode, ret = 0;
50772 +	for (tries = 0; tries < POWER_ON_TRIES; tries++) {
50796  	if (ret < 0) {
50807 -	if (ret < 0) {
50861  	return 0;
50899  #define UOC_CON3_UTMI_SUSPENDN				BIT(0)
50901 +#define RK3288_UOC0_CON0				0x320
50902 +#define RK3288_UOC0_CON0_COMMON_ON_N			BIT(0)
50905 +#define RK3288_UOC0_CON2				0x328
50912 +#define RK3288_UOC0_CON3				0x32c
50913 +#define RK3288_UOC0_CON3_UTMI_SUSPENDN			BIT(0)
50921 +#define RK3288_UOC0_CON3_IDDIG_SET_OTG			(0 << 12)
50926 +#define RK3288_UOC0_CON4				0x330
50930 +#define RK3288_SOC_STATUS2				0x288
50934 +#define RK3288_SOC_STATUS19				0x2cc
50946 +	USB_CHG_STATE_UNDEFINED = 0,
51037 +	int val = 0;
51046 +	if (!strncmp(buf, "0", 1) || !strncmp(buf, "otg", 3)) {
51111 +	int ret = 0;
51114 +	if (phy->bvalid_irq > 0) {
51142 +	if (phy->bvalid_irq > 0)
51145 +	return 0;
51152  	return 0;
51171 +		edev = extcon_get_edev_by_phandle(base->dev, 0);
51196 +	return 0;
51239 +		schedule_delayed_work(&rk_phy->chg_work, 0);
51325 +		dcd_retries = 0;
51326 +		primary_retries = 0;
51339 +			val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_DCDENB);
51361 +		val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_VDATSRCENB
51381 +				delay = 0;
51388 +				delay = 0;
51397 +		val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_VDATSRCENB
51411 +		val = HIWORD_UPDATE(0, RK3288_UOC0_CON2_SOFT_CON_SEL);
51442 +	if (ret < 0 || !(val & RK3288_UOC0_CON4_BVALID_IRQ_PD))
51465 +	int ret = 0;
51468 +	if (rk_phy->reg_offset == 0x320) {
51475 +		if (rk_phy->bvalid_irq <= 0) {
51513 +	} else if (rk_phy->reg_offset == 0x334) {
51567  	.usb_uart_phy = 0,
51570 -#define RK3288_UOC0_CON3				0x32c
51696 +	RK817_PINMUX_FUN0 = 0,
51777 +		.val_msk = 0,
51779 +		.dir_msk = 0
51857  		return 0;
51872 +					 0);
51881  	return 0;
51892 +		return 0;
51941  		return 0;
51959 +		return 0;
52103  	if (ret < 0) {
52151 -#define GPIO_SWPORT_DR		0x00
52152 -#define GPIO_SWPORT_DDR		0x04
52153 -#define GPIO_INTEN		0x30
52154 -#define GPIO_INTMASK		0x34
52155 -#define GPIO_INTTYPE_LEVEL	0x38
52156 -#define GPIO_INT_POLARITY	0x3c
52157 -#define GPIO_INT_STATUS		0x40
52158 -#define GPIO_INT_RAWSTATUS	0x44
52159 -#define GPIO_DEBOUNCE		0x48
52160 -#define GPIO_PORTS_EOI		0x4c
52161 -#define GPIO_EXT_PORT		0x50
52162 -#define GPIO_LS_SYNC		0x60
52206 -	DRV_TYPE_IO_DEFAULT = 0,
52218 -	PULL_TYPE_IO_DEFAULT = 0,
52334 -	ROCKCHIP_ROUTE_SAME = 0,
52453 +		.num = 0,
52455 +		.reg = 0x10000,
52456 +		.bit = 0,
52457 +		.mask = 0xf
52460 +		.num = 0,
52462 +		.reg = 0x10000,
52464 +		.mask = 0xf
52467 +		.num = 0,
52469 +		.reg = 0x10000,
52471 +		.mask = 0xf
52474 +		.num = 0,
52476 +		.reg = 0x10000,
52478 +		.mask = 0xf
52491 +		.reg = 0x24,
52492 +		.bit = 0,
52493 +		.mask = 0x3
52497 +		.reg = 0x24,
52499 +		.mask = 0x3
52503 +		.reg = 0x24,
52505 +		.mask = 0x3
52509 +		.reg = 0x24,
52511 +		.mask = 0x3
52515  		.reg = 0x24,
52517  		.mask = 0x3
52521 +		.reg = 0x24,
52523 +		.mask = 0x3
52527 +		.reg = 0x24,
52529 +		.mask = 0x3
52538 +	RK_MUXROUTE_GRF(3, RK_PD2, 1, 0x10260, WRITE_MASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */
52539 +	RK_MUXROUTE_GRF(3, RK_PB0, 3, 0x10260, WRITE_MASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */
52541 +	RK_MUXROUTE_GRF(0, RK_PD4, 4, 0x10260, WRITE_MASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */
52542 +	RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x10260, WRITE_MASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */
52543 +	RK_MUXROUTE_GRF(2, RK_PC7, 6, 0x10260, WRITE_MASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */
52545 +	RK_MUXROUTE_GRF(1, RK_PD0, 1, 0x10260, WRITE_MASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */
52546 +	RK_MUXROUTE_GRF(2, RK_PB3, 2, 0x10260, WRITE_MASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */
52548 +	RK_MUXROUTE_GRF(3, RK_PD4, 2, 0x10260, WRITE_MASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */
52549 +	RK_MUXROUTE_GRF(3, RK_PC0, 3, 0x10260, WRITE_MASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */
52551 +	RK_MUXROUTE_GRF(3, RK_PC6, 1, 0x10264, WRITE_MASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */
52552 +	RK_MUXROUTE_GRF(2, RK_PD1, 3, 0x10264, WRITE_MASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */
52554 +	RK_MUXROUTE_GRF(3, RK_PA4, 5, 0x10264, WRITE_MASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */
52555 +	RK_MUXROUTE_GRF(2, RK_PD4, 7, 0x10264, WRITE_MASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */
52556 +	RK_MUXROUTE_GRF(1, RK_PD6, 3, 0x10264, WRITE_MASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */
52558 +	RK_MUXROUTE_GRF(3, RK_PA0, 7, 0x10264, WRITE_MASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */
52559 +	RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x10264, WRITE_MASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */
52561 +	RK_MUXROUTE_GRF(2, RK_PA5, 7, 0x10264, WRITE_MASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */
52562 +	RK_MUXROUTE_GRF(3, RK_PB0, 5, 0x10264, WRITE_MASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */
52563 +	RK_MUXROUTE_GRF(1, RK_PD0, 4, 0x10264, WRITE_MASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */
52565 +	RK_MUXROUTE_GRF(3, RK_PC0, 5, 0x10264, WRITE_MASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */
52566 +	RK_MUXROUTE_GRF(1, RK_PC6, 3, 0x10264, WRITE_MASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */
52567 +	RK_MUXROUTE_GRF(2, RK_PD5, 6, 0x10264, WRITE_MASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */
52569 +	RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x10264, WRITE_MASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */
52570 +	RK_MUXROUTE_GRF(2, RK_PB7, 2, 0x10264, WRITE_MASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */
52572 +	RK_MUXROUTE_GRF(3, RK_PA1, 3, 0x10264, WRITE_MASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */
52573 +	RK_MUXROUTE_GRF(3, RK_PA7, 5, 0x10264, WRITE_MASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */
52575 +	RK_MUXROUTE_GRF(3, RK_PA4, 6, 0x10268, WRITE_MASK_VAL(0, 0, 0)), /* PWM8_M0 */
52576 +	RK_MUXROUTE_GRF(2, RK_PD7, 5, 0x10268, WRITE_MASK_VAL(0, 0, 1)), /* PWM8_M1 */
52578 +	RK_MUXROUTE_GRF(3, RK_PA5, 6, 0x10268, WRITE_MASK_VAL(2, 2, 0)), /* PWM9_M0 */
52579 +	RK_MUXROUTE_GRF(2, RK_PD6, 5, 0x10268, WRITE_MASK_VAL(2, 2, 1)), /* PWM9_M1 */
52581 +	RK_MUXROUTE_GRF(3, RK_PA6, 6, 0x10268, WRITE_MASK_VAL(4, 4, 0)), /* PWM10_M0 */
52582 +	RK_MUXROUTE_GRF(2, RK_PD5, 5, 0x10268, WRITE_MASK_VAL(4, 4, 1)), /* PWM10_M1 */
52584 +	RK_MUXROUTE_GRF(3, RK_PA7, 6, 0x10268, WRITE_MASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */
52585 +	RK_MUXROUTE_GRF(3, RK_PA1, 5, 0x10268, WRITE_MASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */
52587 +	RK_MUXROUTE_GRF(1, RK_PA5, 3, 0x10268, WRITE_MASK_VAL(8, 8, 0)), /* UART2_TX_M0 */
52588 +	RK_MUXROUTE_GRF(3, RK_PA2, 1, 0x10268, WRITE_MASK_VAL(8, 8, 1)), /* UART2_TX_M1 */
52590 +	RK_MUXROUTE_GRF(3, RK_PC6, 3, 0x10268, WRITE_MASK_VAL(11, 10, 0)), /* UART3_TX_M0 */
52591 +	RK_MUXROUTE_GRF(1, RK_PA7, 2, 0x10268, WRITE_MASK_VAL(11, 10, 1)), /* UART3_TX_M1 */
52592 +	RK_MUXROUTE_GRF(3, RK_PA0, 4, 0x10268, WRITE_MASK_VAL(11, 10, 2)), /* UART3_TX_M2 */
52594 +	RK_MUXROUTE_GRF(3, RK_PA4, 4, 0x10268, WRITE_MASK_VAL(13, 12, 0)), /* UART4_TX_M0 */
52595 +	RK_MUXROUTE_GRF(2, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(13, 12, 1)), /* UART4_TX_M1 */
52596 +	RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x10268, WRITE_MASK_VAL(13, 12, 2)), /* UART4_TX_M2 */
52598 +	RK_MUXROUTE_GRF(3, RK_PA6, 4, 0x10268, WRITE_MASK_VAL(15, 14, 0)), /* UART5_TX_M0 */
52599 +	RK_MUXROUTE_GRF(2, RK_PB0, 4, 0x10268, WRITE_MASK_VAL(15, 14, 1)), /* UART5_TX_M1 */
52600 +	RK_MUXROUTE_GRF(2, RK_PA0, 3, 0x10268, WRITE_MASK_VAL(15, 14, 2)), /* UART5_TX_M2 */
52602 +	RK_MUXROUTE_PMU(0, RK_PB6, 3, 0x0114, WRITE_MASK_VAL(0, 0, 0)), /* PWM0_M0 */
52603 +	RK_MUXROUTE_PMU(2, RK_PB3, 5, 0x0114, WRITE_MASK_VAL(0, 0, 1)), /* PWM0_M1 */
52605 +	RK_MUXROUTE_PMU(0, RK_PB7, 3, 0x0114, WRITE_MASK_VAL(2, 2, 0)), /* PWM1_M0 */
52606 +	RK_MUXROUTE_PMU(2, RK_PB2, 5, 0x0114, WRITE_MASK_VAL(2, 2, 1)), /* PWM1_M1 */
52608 +	RK_MUXROUTE_PMU(0, RK_PC0, 3, 0x0114, WRITE_MASK_VAL(4, 4, 0)), /* PWM2_M0 */
52609 +	RK_MUXROUTE_PMU(2, RK_PB1, 5, 0x0114, WRITE_MASK_VAL(4, 4, 1)), /* PWM2_M1 */
52611 +	RK_MUXROUTE_PMU(0, RK_PC1, 3, 0x0114, WRITE_MASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */
52612 +	RK_MUXROUTE_PMU(2, RK_PB0, 5, 0x0114, WRITE_MASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */
52614 +	RK_MUXROUTE_PMU(0, RK_PC2, 3, 0x0114, WRITE_MASK_VAL(8, 8, 0)), /* PWM4_M0 */
52615 +	RK_MUXROUTE_PMU(2, RK_PA7, 5, 0x0114, WRITE_MASK_VAL(8, 8, 1)), /* PWM4_M1 */
52617 +	RK_MUXROUTE_PMU(0, RK_PC3, 3, 0x0114, WRITE_MASK_VAL(10, 10, 0)), /* PWM5_M0 */
52618 +	RK_MUXROUTE_PMU(2, RK_PA6, 5, 0x0114, WRITE_MASK_VAL(10, 10, 1)), /* PWM5_M1 */
52620 +	RK_MUXROUTE_PMU(0, RK_PB2, 3, 0x0114, WRITE_MASK_VAL(12, 12, 0)), /* PWM6_M0 */
52621 +	RK_MUXROUTE_PMU(2, RK_PD4, 5, 0x0114, WRITE_MASK_VAL(12, 12, 1)), /* PWM6_M1 */
52623 +	RK_MUXROUTE_PMU(0, RK_PB1, 3, 0x0114, WRITE_MASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */
52624 +	RK_MUXROUTE_PMU(3, RK_PA0, 5, 0x0114, WRITE_MASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */
52626 +	RK_MUXROUTE_PMU(0, RK_PB0, 1, 0x0118, WRITE_MASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */
52627 +	RK_MUXROUTE_PMU(2, RK_PA1, 1, 0x0118, WRITE_MASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */
52628 +	RK_MUXROUTE_PMU(2, RK_PB2, 6, 0x0118, WRITE_MASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */
52630 +	RK_MUXROUTE_PMU(0, RK_PB6, 2, 0x0118, WRITE_MASK_VAL(2, 2, 0)), /* UART1_TX_M0 */
52631 +	RK_MUXROUTE_PMU(1, RK_PD0, 5, 0x0118, WRITE_MASK_VAL(2, 2, 1)), /* UART1_TX_M1 */
52642 +	RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x190, BIT(16 + 3)), /* i2c2m0_sda */
52643 +	RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x190, BIT(16 + 3) | BIT(3)), /* i2c2m1_sda */
52644 +	RK_MUXROUTE_SAME(1, RK_PA6, 2, 0x190, BIT(16 + 4)), /* spi2m0_miso */
52645 +	RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x190, BIT(16 + 4) | BIT(4)), /* spi2m1_miso */
52646 +	RK_MUXROUTE_SAME(4, RK_PB7, 2, 0x190, BIT(16 + 5)), /* spi1m0_miso */
52647 +	RK_MUXROUTE_SAME(3, RK_PD2, 3, 0x190, BIT(16 + 5) | BIT(5)), /* spi1m1_miso */
52648 +	RK_MUXROUTE_SAME(4, RK_PB0, 2, 0x190, BIT(16 + 13)), /* uart1_rxm0 */
52649 +	RK_MUXROUTE_SAME(1, RK_PB4, 3, 0x190, BIT(16 + 13) | BIT(13)), /* uart1_rxm1 */
52650 +	RK_MUXROUTE_SAME(4, RK_PA3, 2, 0x190, BIT(16 + 14) | BIT(16 + 15)), /* uart2_rxm0 */
52651 +	RK_MUXROUTE_SAME(2, RK_PD1, 2, 0x190, BIT(16 + 14) | BIT(16 + 15) | BIT(14)), /* uart2_rxm1 */
52652 +	RK_MUXROUTE_SAME(3, RK_PA4, 2, 0x190, BIT(16 + 14) | BIT(16 + 15) | BIT(15)), /* uart2_rxm2 */
52659 -		.pin = 0,
52661 -		.route_offset = 0x184,
52668 -		.route_offset = 0x184,
52675 -		.route_offset = 0x184,
52682 -		.route_offset = 0x184,
52689 -		.route_offset = 0x184,
52696 -		.route_offset = 0x184,
52700 -		.bank_num = 0,
52703 -		.route_offset = 0x184,
52710 -		.route_offset = 0x184,
52713 +	RK_MUXROUTE_SAME(2, RK_PA0, 1, 0x184, BIT(16 + 7)), /* cif-d2m0 */
52714 +	RK_MUXROUTE_SAME(3, RK_PA3, 3, 0x184, BIT(16 + 7) | BIT(7)), /* cif-d2m1 */
52715 +	RK_MUXROUTE_SAME(3, RK_PC6, 2, 0x184, BIT(16 + 8)), /* pdm-m0 */
52716 +	RK_MUXROUTE_SAME(2, RK_PC6, 1, 0x184, BIT(16 + 8) | BIT(8)), /* pdm-m1 */
52717 +	RK_MUXROUTE_SAME(1, RK_PD3, 2, 0x184, BIT(16 + 10)), /* uart2-rxm0 */
52718 +	RK_MUXROUTE_SAME(2, RK_PB6, 2, 0x184, BIT(16 + 10) | BIT(10)), /* uart2-rxm1 */
52719 +	RK_MUXROUTE_SAME(0, RK_PC1, 2, 0x184, BIT(16 + 9)), /* uart3-rxm0 */
52720 +	RK_MUXROUTE_SAME(1, RK_PB7, 2, 0x184, BIT(16 + 9) | BIT(9)), /* uart3-rxm1 */
52725 -		/* spi-0 */
52729 -		.route_offset = 0x144,
52736 -		.route_offset = 0x144,
52740 -		.bank_num = 0,
52743 -		.route_offset = 0x144,
52746 -		/* i2s-0 */
52750 -		.route_offset = 0x144,
52754 -		.bank_num = 0,
52757 -		.route_offset = 0x144,
52760 -		/* emmc-0 */
52764 -		.route_offset = 0x144,
52771 -		.route_offset = 0x144,
52774 +	RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x144, BIT(16 + 3) | BIT(16 + 4)), /* spi-0 */
52775 +	RK_MUXROUTE_SAME(1, RK_PD3, 3, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(3)), /* spi-1 */
52776 +	RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x144, BIT(16 + 3) | BIT(16 + 4) | BIT(4)), /* spi-2 */
52777 +	RK_MUXROUTE_SAME(1, RK_PA5, 1, 0x144, BIT(16 + 5)), /* i2s-0 */
52778 +	RK_MUXROUTE_SAME(0, RK_PB6, 1, 0x144, BIT(16 + 5) | BIT(5)), /* i2s-1 */
52779 +	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x144, BIT(16 + 6)), /* emmc-0 */
52780 +	RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x144, BIT(16 + 6) | BIT(6)), /* emmc-1 */
52786 -		.bank_num = 0,
52790 -		.route_offset = 0xa0,
52794 -		.bank_num = 0,
52798 -		.route_offset = 0xa0,
52801 +	RK_MUXROUTE_SAME(0, RK_PD0, 1, 0xa0, BIT(16 + 11)), /* non-iomuxed emmc/flash pins on flash-dqs */
52802 +	RK_MUXROUTE_SAME(0, RK_PD0, 2, 0xa0, BIT(16 + 11) | BIT(11)), /* non-iomuxed emmc/flash pins on e…
52807 -		/* pwm0-0 */
52808 -		.bank_num = 0,
52811 -		.route_offset = 0x50,
52818 -		.route_offset = 0x50,
52819 -		.route_val = BIT(16) | BIT(0),
52821 -		/* pwm1-0 */
52822 -		.bank_num = 0,
52825 -		.route_offset = 0x50,
52829 -		.bank_num = 0,
52832 -		.route_offset = 0x50,
52835 -		/* pwm2-0 */
52836 -		.bank_num = 0,
52839 -		.route_offset = 0x50,
52846 -		.route_offset = 0x50,
52849 -		/* pwm3-0 */
52853 -		.route_offset = 0x50,
52860 -		.route_offset = 0x50,
52863 -		/* sdio-0_d0 */
52867 -		.route_offset = 0x50,
52874 -		.route_offset = 0x50,
52877 -		/* spi-0_rx */
52878 -		.bank_num = 0,
52881 -		.route_offset = 0x50,
52886 -		.pin = 0,
52888 -		.route_offset = 0x50,
52891 -		/* emmc-0_cmd */
52895 -		.route_offset = 0x50,
52902 -		.route_offset = 0x50,
52905 -		/* uart2-0_rx */
52909 -		.route_offset = 0x50,
52916 -		.route_offset = 0x50,
52919 -		/* uart1-0_rx */
52923 -		.route_offset = 0x50,
52930 -		.route_offset = 0x50,
52933 +	RK_MUXROUTE_SAME(0, RK_PD2, 1, 0x50, BIT(16)), /* pwm0-0 */
52934 +	RK_MUXROUTE_SAME(3, RK_PC5, 1, 0x50, BIT(16) | BIT(0)), /* pwm0-1 */
52935 +	RK_MUXROUTE_SAME(0, RK_PD3, 1, 0x50, BIT(16 + 1)), /* pwm1-0 */
52936 +	RK_MUXROUTE_SAME(0, RK_PD6, 2, 0x50, BIT(16 + 1) | BIT(1)), /* pwm1-1 */
52937 +	RK_MUXROUTE_SAME(0, RK_PD4, 1, 0x50, BIT(16 + 2)), /* pwm2-0 */
52938 +	RK_MUXROUTE_SAME(1, RK_PB4, 2, 0x50, BIT(16 + 2) | BIT(2)), /* pwm2-1 */
52939 +	RK_MUXROUTE_SAME(3, RK_PD2, 1, 0x50, BIT(16 + 3)), /* pwm3-0 */
52940 +	RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 3) | BIT(3)), /* pwm3-1 */
52941 +	RK_MUXROUTE_SAME(1, RK_PA1, 1, 0x50, BIT(16 + 4)), /* sdio-0_d0 */
52942 +	RK_MUXROUTE_SAME(3, RK_PA2, 1, 0x50, BIT(16 + 4) | BIT(4)), /* sdio-1_d0 */
52943 +	RK_MUXROUTE_SAME(0, RK_PB5, 2, 0x50, BIT(16 + 5)), /* spi-0_rx */
52944 +	RK_MUXROUTE_SAME(2, RK_PA0, 2, 0x50, BIT(16 + 5) | BIT(5)), /* spi-1_rx */
52945 +	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x50, BIT(16 + 7)), /* emmc-0_cmd */
52946 +	RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x50, BIT(16 + 7) | BIT(7)), /* emmc-1_cmd */
52947 +	RK_MUXROUTE_SAME(1, RK_PC3, 2, 0x50, BIT(16 + 8)), /* uart2-0_rx */
52948 +	RK_MUXROUTE_SAME(1, RK_PB2, 2, 0x50, BIT(16 + 8) | BIT(8)), /* uart2-1_rx */
52949 +	RK_MUXROUTE_SAME(1, RK_PB2, 1, 0x50, BIT(16 + 11)), /* uart1-0_rx */
52950 +	RK_MUXROUTE_SAME(3, RK_PB5, 1, 0x50, BIT(16 + 11) | BIT(11)), /* uart1-1_rx */
52959 -		.route_offset = 0x264,
52966 -		.route_offset = 0x264,
52969 +	RK_MUXROUTE_SAME(7, RK_PC0, 2, 0x264, BIT(16 + 12) | BIT(12)), /* edphdmi_cecinoutt1 */
52970 +	RK_MUXROUTE_SAME(7, RK_PC7, 4, 0x264, BIT(16 + 12)), /* edphdmi_cecinout */
52976 -		.bank_num = 0,
52979 -		.route_offset = 0x314,
52980 -		.route_val = BIT(16 + 0) | BIT(0),
52986 -		.route_offset = 0x314,
52993 -		.route_offset = 0x314,
52997 -		.bank_num = 0,
53000 -		.route_offset = 0x608,
53007 -		.route_offset = 0x608,
53012 -		.pin = 0,
53014 -		.route_offset = 0x608,
53021 -		.route_offset = 0x308,
53028 -		.route_offset = 0x308,
53035 -		.route_offset = 0x308,
53042 -		.route_offset = 0x308,
53049 -		.route_offset = 0x308,
53056 -		.route_offset = 0x308,
53063 -		.route_offset = 0x308,
53070 -		.route_offset = 0x600,
53077 -		.route_offset = 0x314,
53084 -		.route_offset = 0x314,
53088 -		.bank_num = 0,
53091 -		.route_offset = 0x314,
53098 -		.route_offset = 0x314,
53105 -		.route_offset = 0x314,
53109 -		.bank_num = 0,
53112 -		.route_offset = 0x314,
53119 -		.route_offset = 0x314,
53126 -		.route_offset = 0x314,
53133 -		.route_offset = 0x314,
53140 -		.route_offset = 0x314,
53147 -		.route_offset = 0x314,
53151 -		.bank_num = 0,
53154 -		.route_offset = 0x314,
53157 +	RK_MUXROUTE_SAME(0, RK_PC3, 1, 0x314, BIT(16 + 0) | BIT(0)), /* rtc_clk */
53158 +	RK_MUXROUTE_SAME(1, RK_PC6, 2, 0x314, BIT(16 + 2) | BIT(16 + 3)), /* uart2_rxm0 */
53159 +	RK_MUXROUTE_SAME(4, RK_PD2, 2, 0x314, BIT(16 + 2) | BIT(16 + 3) | BIT(2)), /* uart2_rxm1 */
53160 +	RK_MUXROUTE_SAME(0, RK_PB7, 2, 0x608, BIT(16 + 8) | BIT(16 + 9)), /* i2c3_sdam0 */
53161 +	RK_MUXROUTE_SAME(3, RK_PB4, 2, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(8)), /* i2c3_sdam1 */
53162 +	RK_MUXROUTE_SAME(2, RK_PA0, 3, 0x608, BIT(16 + 8) | BIT(16 + 9) | BIT(9)), /* i2c3_sdam2 */
53163 +	RK_MUXROUTE_SAME(1, RK_PA3, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclktxm0 */
53164 +	RK_MUXROUTE_SAME(1, RK_PA4, 2, 0x308, BIT(16 + 3)), /* i2s-8ch-1-sclkrxm0 */
53165 +	RK_MUXROUTE_SAME(1, RK_PB5, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclktxm1 */
53166 +	RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x308, BIT(16 + 3) | BIT(3)), /* i2s-8ch-1-sclkrxm1 */
53167 +	RK_MUXROUTE_SAME(1, RK_PA4, 3, 0x308, BIT(16 + 12) | BIT(16 + 13)), /* pdm-clkm0 */
53168 +	RK_MUXROUTE_SAME(1, RK_PB6, 4, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* pdm-clkm1 */
53169 +	RK_MUXROUTE_SAME(2, RK_PA6, 2, 0x308, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* pdm-clkm2 */
53170 +	RK_MUXROUTE_SAME(2, RK_PA4, 3, 0x600, BIT(16 + 2) | BIT(2)), /* pdm-clkm-m2 */
53171 +	RK_MUXROUTE_SAME(3, RK_PB2, 3, 0x314, BIT(16 + 9)), /* spi1_miso */
53172 +	RK_MUXROUTE_SAME(2, RK_PA4, 2, 0x314, BIT(16 + 9) | BIT(9)), /* spi1_miso_m1 */
53173 +	RK_MUXROUTE_SAME(0, RK_PB3, 3, 0x314, BIT(16 + 10) | BIT(16 + 11)), /* owire_m0 */
53174 +	RK_MUXROUTE_SAME(1, RK_PC6, 7, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* owire_m1 */
53175 +	RK_MUXROUTE_SAME(2, RK_PA2, 5, 0x314, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* owire_m2 */
53176 +	RK_MUXROUTE_SAME(0, RK_PB3, 2, 0x314, BIT(16 + 12) | BIT(16 + 13)), /* can_rxd_m0 */
53177 +	RK_MUXROUTE_SAME(1, RK_PC6, 5, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(12)), /* can_rxd_m1 */
53178 +	RK_MUXROUTE_SAME(2, RK_PA2, 4, 0x314, BIT(16 + 12) | BIT(16 + 13) | BIT(13)), /* can_rxd_m2 */
53179 +	RK_MUXROUTE_SAME(1, RK_PC4, 3, 0x314, BIT(16 + 14)), /* mac_rxd0_m0 */
53180 +	RK_MUXROUTE_SAME(4, RK_PA2, 2, 0x314, BIT(16 + 14) | BIT(14)), /* mac_rxd0_m1 */
53181 +	RK_MUXROUTE_SAME(3, RK_PB4, 4, 0x314, BIT(16 + 15)), /* uart3_rx */
53182 +	RK_MUXROUTE_SAME(0, RK_PC1, 3, 0x314, BIT(16 + 15) | BIT(15)), /* uart3_rx_m1 */
53191 -		.route_offset = 0x50,
53198 -		.route_offset = 0x50,
53199 -		.route_val = BIT(16) | BIT(16 + 1) | BIT(0),
53205 -		.route_offset = 0x50,
53212 -		.route_offset = 0x50,
53219 -		.route_offset = 0x50,
53226 -		.route_offset = 0x50,
53233 -		.route_offset = 0x50,
53240 -		.route_offset = 0x50,
53247 -		.route_offset = 0x50,
53254 -		.route_offset = 0x50,
53261 -		.route_offset = 0x50,
53268 -		.route_offset = 0x50,
53271 +	RK_MUXROUTE_SAME(1, RK_PA1, 2, 0x50, BIT(16) | BIT(16 + 1)), /* uart2dbg_rxm0 */
53272 +	RK_MUXROUTE_SAME(2, RK_PA1, 1, 0x50, BIT(16) | BIT(16 + 1) | BIT(0)), /* uart2dbg_rxm1 */
53273 +	RK_MUXROUTE_SAME(1, RK_PB3, 2, 0x50, BIT(16 + 2) | BIT(2)), /* gmac-m1_rxd0 */
53274 +	RK_MUXROUTE_SAME(1, RK_PB6, 2, 0x50, BIT(16 + 10) | BIT(10)), /* gmac-m1-optimized_rxd3 */
53275 +	RK_MUXROUTE_SAME(2, RK_PC3, 2, 0x50, BIT(16 + 3)), /* pdm_sdi0m0 */
53276 +	RK_MUXROUTE_SAME(1, RK_PC7, 3, 0x50, BIT(16 + 3) | BIT(3)), /* pdm_sdi0m1 */
53277 +	RK_MUXROUTE_SAME(3, RK_PA2, 4, 0x50, BIT(16 + 4) | BIT(16 + 5) | BIT(5)), /* spi_rxdm2 */
53278 +	RK_MUXROUTE_SAME(1, RK_PD0, 1, 0x50, BIT(16 + 6)), /* i2s2_sdim0 */
53279 +	RK_MUXROUTE_SAME(3, RK_PA2, 6, 0x50, BIT(16 + 6) | BIT(6)), /* i2s2_sdim1 */
53280 +	RK_MUXROUTE_SAME(2, RK_PC6, 3, 0x50, BIT(16 + 7) | BIT(7)), /* card_iom1 */
53281 +	RK_MUXROUTE_SAME(2, RK_PC0, 3, 0x50, BIT(16 + 8) | BIT(8)), /* tsp_d5m1 */
53282 +	RK_MUXROUTE_SAME(2, RK_PC0, 4, 0x50, BIT(16 + 9) | BIT(9)), /* cif_data5m1 */
53291 -		.route_offset = 0xe21c,
53298 -		.route_offset = 0xe21c,
53305 -		.route_offset = 0xe21c,
53312 -		.route_offset = 0xe21c,
53319 -		.route_offset = 0xe21c,
53322 +	RK_MUXROUTE_SAME(4, RK_PB0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11)), /* uart2dbga_rx */
53323 +	RK_MUXROUTE_SAME(4, RK_PC0, 2, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(10)), /* uart2dbgb_rx */
53324 +	RK_MUXROUTE_SAME(4, RK_PC3, 1, 0xe21c, BIT(16 + 10) | BIT(16 + 11) | BIT(11)), /* uart2dbgc_rx */
53325 +	RK_MUXROUTE_SAME(2, RK_PD2, 2, 0xe21c, BIT(16 + 14)), /* pcie_clkreqn */
53326 +	RK_MUXROUTE_SAME(4, RK_PD0, 1, 0xe21c, BIT(16 + 14) | BIT(14)), /* pcie_clkreqnb */
53330 +	RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
53331 +	RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
53332 +	RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
53333 +	RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
53334 +	RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
53335 +	RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
53336 +	RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
53337 +	RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
53338 +	RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
53339 +	RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
53340 +	RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
53341 +	RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
53342 +	RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
53343 +	RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
53344 +	RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
53345 +	RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
53346 +	RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
53347 +	RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
53348 +	RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
53349 +	RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
53350 +	RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
53351 +	RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
53352 +	RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
53353 +	RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
53354 +	RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
53355 +	RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
53356 +	RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
53357 +	RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
53358 +	RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
53359 +	RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
53360 +	RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
53361 +	RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
53362 +	RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
53363 +	RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
53364 +	RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
53365 +	RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
53366 +	RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
53367 +	RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
53368 +	RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
53369 +	RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
53370 +	RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
53371 +	RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
53372 +	RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
53373 +	RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
53374 +	RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
53375 +	RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
53376 +	RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
53377 +	RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
53378 +	RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
53379 +	RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
53380 +	RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
53381 +	RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
53382 +	RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
53383 +	RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
53384 +	RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
53385 +	RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
53386 +	RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
53387 +	RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
53388 +	RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
53389 +	RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
53390 +	RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
53391 +	RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
53392 +	RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
53393 +	RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
53394 +	RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
53395 +	RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
53396 +	RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
53397 +	RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
53398 +	RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
53399 +	RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
53400 +	RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
53401 +	RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
53402 +	RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
53403 +	RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
53404 +	RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
53405 +	RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
53406 +	RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
53407 +	RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
53408 +	RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
53409 +	RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
53410 +	RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
53411 +	RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
53412 +	RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
53413 +	RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
53414 +	RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
53415 +	RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
53416 +	RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
53417 +	RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
53418 +	RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
53419 +	RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
53420 +	RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
53421 +	RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
53422 +	RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
53492  	return 0;
53495 +#define RV1126_PULL_PMU_OFFSET		0x40
53496 +#define RV1126_PULL_GRF_GPIO1A0_OFFSET		0x10108
53509 +	if (bank->bank_num == 0) {
53531 +#define RV1126_DRV_PMU_OFFSET		0x20
53532 +#define RV1126_DRV_GRF_GPIO1A0_OFFSET		0x10090
53544 +	if (bank->bank_num == 0) {
53549 +			*reg -= 0x4;
53567 +#define RV1126_SCHMITT_PMU_OFFSET		0x60
53568 +#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET		0x10188
53581 +	if (bank->bank_num == 0) {
53587 +			return 0;
53601 +	return 0;
53606  #define RK3308_SCHMITT_GRF_OFFSET		0x1a0
53608  	return 0;
53611 +#define RK1808_PULL_PMU_OFFSET		0x10
53612 +#define RK1808_PULL_GRF_OFFSET		0x80
53623 +	if (bank->bank_num == 0) {
53637 +#define RK1808_DRV_PMU_OFFSET		0x20
53638 +#define RK1808_DRV_GRF_OFFSET		0x140
53650 +	if (bank->bank_num == 0) {
53664 +#define RK1808_SR_PMU_OFFSET		0x0030
53665 +#define RK1808_SR_GRF_OFFSET		0x00c0
53676 +	if (bank->bank_num == 0) {
53687 +	return 0;
53690 +#define RK1808_SCHMITT_PMU_OFFSET		0x0040
53691 +#define RK1808_SCHMITT_GRF_OFFSET		0x0100
53702 +	if (bank->bank_num == 0) {
53713 +	return 0;
53716  #define RK2928_PULL_OFFSET		0x118
53723 +#define RK3568_SR_PMU_OFFSET		0x60
53724 +#define RK3568_SR_GRF_OFFSET		0x0180
53725 +#define RK3568_SR_BANK_STRIDE		0x10
53735 +	if (bank->bank_num == 0) {
53746 +	return 0;
53749 +#define RK3568_PULL_PMU_OFFSET		0x20
53750 +#define RK3568_PULL_GRF_OFFSET		0x80
53753 +#define RK3568_PULL_BANK_STRIDE		0x10
53761 +	if (bank->bank_num == 0) {
53780 +#define RK3568_DRV_PMU_OFFSET		0x70
53781 +#define RK3568_DRV_GRF_OFFSET		0x200
53784 +#define RK3568_DRV_BANK_STRIDE		0x40
53793 +	if (bank->bank_num == 0) {
53810 +	if (rockchip_get_cpu_version() == 0)
53835  	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
53851 +	if (ctrl->type == RK3568 && rockchip_get_cpu_version() == 0) {
53853 +			reg = 0x0840;
53855 +			reg = 0x0844;
53857 +			reg = 0x0848;
53858 +		else if (bank->bank_num == 3 && pin_num == 0)
53859 +			reg = 0x084c;
53861 +			reg = 0x0850;
53862 +		else if (bank->bank_num == 4 && pin_num == 0)
53863 +			reg = 0x0854;
53865 +			return 0;
53876 +	return 0;
53909  		for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
53918 +		if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
53923  		if (ret < 0) {
53926  	return 0;
53931 +#define RK3568_SCHMITT_BANK_STRIDE		0x10
53932 +#define RK3568_SCHMITT_GRF_OFFSET		0xc0
53933 +#define RK3568_SCHMITT_PMUGRF_OFFSET		0x30
53942 +	if (bank->bank_num == 0) {
53955 +	return 0;
53965 -	return data & 0x1;
53976 +	return data & 0x1;
53992 +		data |= ((enable ? 0x2 : 0x1) << bit);
54003 +#define PX30_SLEW_RATE_PMU_OFFSET		0x30
54004 +#define PX30_SLEW_RATE_GRF_OFFSET		0x90
54017 +	if (bank->bank_num == 0) {
54030 +	return 0;
54051 +	return data & 0x1;
54083 -		for (cnt--; cnt >= 0; cnt--)
54084 +		for (cnt--; cnt >= 0 && !data[cnt].func; cnt--)
54085  			rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
54089  	return 0;
54099 -	if (ret < 0) {
54129 -	if (ret < 0)
54136 -	/* set bit to 1 for output, 0 for input */
54146 -	return 0;
54215 +			if (rc != 0) {
54225  			if (rc < 0)
54234 +			if (rc < 0)
54256 +		if (rc != 0) {
54263  		if (rc < 0)
54267  		if (rc < 0)
54277 +		if (rc < 0)
54303 -	for (i = 0, j = 0; i < size; i += 4, j++) {
54326 -	return 0;
54338 -	u32 i = 0;
54347 -	if (func->ngroups <= 0)
54348 -		return 0;
54365 -	return 0;
54396 -	i = 0;
54410 -	return 0;
54438 -	for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
54440 -		for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
54458 -	for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
54469 -	return 0;
54697 -	if (ret < 0)
54769 -	return 0;
54796 +	for (i = 0, j = 0; i < size; i += 4, j++) {
54836 +	return 0;
54855 +	u32 i = 0;
54857 -	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
54884 +	if (func->ngroups <= 0)
54885 +		return 0;
54894 -					 clr, 0, 0);
54909 -		gc = irq_get_domain_generic_chip(bank->domain, 0);
54912 -		gc->chip_types[0].regs.mask = GPIO_INTMASK;
54913 -		gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
54914 -		gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
54915 -		gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
54916 -		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
54917 -		gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
54918 -		gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
54919 -		gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
54920 -		gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
54921 -		gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
54922 -		gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
54930 -		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
54931 -		writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
54932 -		gc->mask_cache = 0xffffffff;
54939  	return 0;
54956 -	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
54997 -	return 0;
54998 +	i = 0;
55001 -	for (--i, --bank; i >= 0; --i, --bank) {
55018 -	for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
55030  	return 0;
55046 -	if (of_address_to_resource(bank->of_node, 0, &res)) {
55074 -					"rockchip,pmu", 0);
55094 +	for (bank = 0, k = 0; bank < info->ctrl->nr_banks; bank++) {
55096 +		for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
55105 -	bank->irq = irq_of_parse_and_map(bank->of_node, 0);
55110 -	bank->clk = of_clk_get(bank->of_node, 0);
55120 +	return 0;
55141 -		for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
55159  			if (iom->offset >= 0) {
55188 +#define RK3308_GRF_SOC_CON13			0x608
55189 +#define RK3308_GRF_SOC_CON15			0x610
55257  	return 0;
55272 +	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
55282 +			     0x10010, 0x10018, 0x10020, 0x10028),
55294 +			     IOMUX_WIDTH_4BIT, 0, 0, 0),
55302 +	.grf_mux_offset		= 0x10004, /* mux offset from GPIO0_D0 */
55303 +	.pmu_mux_offset		= 0x0,
55314 +	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
55343 +	.grf_mux_offset		= 0x0,
55344 +	.pmu_mux_offset		= 0x0,
55352  	PIN_BANK(0, 32, "gpio0"),
55358 -	PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
55361 +	PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WRITABLE_32BIT,
55380 +	PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
55407 +	.grf_mux_offset		= 0x0,
55408 +	.pmu_mux_offset		= 0x0,
55409 +	.grf_drv_offset		= 0x0200,
55410 +	.pmu_drv_offset		= 0x0070,
55468 index 0aa46b451..4c43f58c7 100644
55541  #define PWM_OUTPUT_LEFT		(0 << 5)
55544  #define PWM_LP_DISABLE		(0 << 8)
55642 +	} else if (state->oneshot_count > 0) {
55715 +	.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
55726 +	.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
55737 +	.enable_conf_mask = GENMASK(2, 0) | BIT(5) | BIT(8),
55744  	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
55786  	if (ret < 0) {
55841 +	ret = kstrtouint(buf, 0, &val);
55977 +	int ret = 0;
55979 +	if (val > 0) {
56007 +		buf[count] = '\0';
56011 +		if (ret || min_uV < 0) {
56083 +	return 0;
56110 +	return 0;
56125 +	if (mode < 0) {
56132 +	return 0;
56165 +	return 0;
56240 +	mode = 0;
56251 +	mode = 0;
56262 +	mode = 0;
56273 +	mode = 0;
56330  #define FAN53555_VSEL0		0x00
56331  #define FAN53555_VSEL1		0x01
56333 +#define RK860X_VSEL0		0x06
56334 +#define RK860X_VSEL1		0x07
56335 +#define RK860X_MAX_SET		0x08
56337 +#define TCS452X_VSEL0		0x11
56338 +#define TCS452X_VSEL1		0x10
56339 +#define TCS452X_TIME		0x13
56340 +#define TCS452X_COMMAND		0x14
56341 +#define TCS452X_LIMCONF		0x16
56344  #define FAN53555_CONTROL	0x02
56350 +#define VSEL_NSEL_MASK	0x3F
56352  #define DIE_ID		0x0F	/* ID1 */
56353  #define DIE_REV		0x0F	/* ID2 */
56355  #define CTL_MODE_VSEL0_MODE	BIT(0)
56360 +#define RK_VSEL_NSEL_MASK	0xff
56362 +#define TCS_VSEL_NSEL_MASK	0x7f
56367 +#define TCS_SLEW_MASK		(0x3 < 3)
56374  	FAN53526_VENDOR_FAIRCHILD = 0,
56435 +		if (ret < 0)
56452  	if (ret < 0)
56458  	if (ret < 0)
56476 +				  VSEL_BUCK_EN, 0);
56485 +		return 0;
56498 +		return 0;
56502  				  VSEL_BUCK_EN, 0);
56509 +	int ret = 0;
56519 +	if (ret < 0)
56524 +		return 0;
56538 -		regmap_update_bits(rdev->regmap, di->vol_reg, di->mode_mask, 0);
56539 +		regmap_update_bits(di->regmap, di->mode_reg, di->mode_mask, 0);
56545  	int ret = 0;
56549  	if (ret < 0)
56570 -	for (i = 0; i < ARRAY_SIZE(slew_rates); i++) {
56587 +	for (i = 0; i < slew_rate_n; i++) {
56626  	return 0;
56641 +	return 0;
56647 +	int ret = 0, val;
56680 +		if (ret < 0) {
56686  	return 0;
56702 +	return 0;
56731  	return 0;
56839 +		devm_gpiod_get_index_optional(dev, "vsel", 0,
56916  	if (ret < 0) {
56924  	if (ret < 0) {
56937  	if (ret < 0)
56967 +			ret = 0;
56974 +	if (ret < 0)
57035  #define RK817_BOOST_VSEL_MASK		0x7
57036  #define RK817_BUCK_VSEL_MASK		0x7f
57043  #define RK818_BUCK_VSEL_MASK		0x3f
57044  #define RK818_BUCK4_VSEL_MASK		0x1f
57045  #define RK818_LDO_VSEL_MASK		0x1f
57070 -	_vmask, _ereg, _emask, 0, 0, _etime, &rk805_reg_ops)
57076  	_vmask, _ereg, _emask, 0, 0, _etime, &rk808_reg_ops)
57105 +	REGULATOR_LINEAR_RANGE(712500, 0, 59, 12500),	/* 0.7125v - 1.45v */
57107 +	REGULATOR_LINEAR_RANGE(2300000, 63, 63, 0),	/* 2.3v - 2.3v */
57111 +	REGULATOR_LINEAR_RANGE(800000, 0, 26, 100000),	/* 0.8v - 3.4v */
57112 +	REGULATOR_LINEAR_RANGE(3500000, 27, 31, 0),	/* 3.5v */
57116  	REGULATOR_LINEAR_RANGE(800000, 0, 13, 100000),
57117  	REGULATOR_LINEAR_RANGE(2500000, 15, 15, 0),
57121 +	REGULATOR_LINEAR_RANGE(712500, 0, 59, 12500),	/* 0.7125v - 1.45v */
57123 +	REGULATOR_LINEAR_RANGE(2300000, 63, 63, 0),	/* 2.3v - 2.3v */
57127 +	REGULATOR_LINEAR_RANGE(800000, 0, 26, 100000),	/* 0.8v - 3.4 */
57128 +	REGULATOR_LINEAR_RANGE(3500000, 27, 31, 0),	/* 3.5v */
57155 +	if ((rk816_type != RK816_TYPE_ES2) && (id == 0)) {
57182 +	} while ((sel != real_sel) && (delay > 0));
57184 +	if ((rk816_type != RK816_TYPE_ES2) && (id == 0))
57203 +	case 0 ... 3000:
57278  				  0);
57326 +				  0);
57378  	if (ret != 0)
57382 -	val |= (rdev->desc->enable_mask & 0xf0);
57388 -		return (val == 0);
57393  	return val != 0;
57481 -	REGULATOR_LINEAR_RANGE(712500, 0, 59, 12500),
57483 -	REGULATOR_LINEAR_RANGE(2300000, 63, 63, 0),
57547 -		.enable_mask = BIT(0),
57605 -		RK805_DCDC_EN_REG, BIT(3), 0),
57609 -		BIT(0), 400),
57610 +		ENABLE_MASK(0), DISABLE_VAL(0), 400),
57641 +		.enable_mask = BIT(4) | BIT(0),
57642 +		.enable_val = BIT(4) | BIT(0),
57703 +		   RK816_LDO_EN_REG1, ENABLE_MASK(0), DISABLE_VAL(0), 400),
57715 +		   RK816_LDO_EN_REG2, ENABLE_MASK(0), DISABLE_VAL(0), 400),
57726  		.enable_reg = RK817_POWER_EN_REG(0),
57735  		.enable_reg = RK817_POWER_EN_REG(0),
57744  		.enable_reg = RK817_POWER_EN_REG(0),
57753  		.enable_reg = RK817_POWER_EN_REG(0),
57771  		   RK817_LDO_ON_VSEL_REG(0), RK817_LDO_VSEL_MASK,
57772 -		   RK817_POWER_EN_REG(1), ENABLE_MASK(0),
57773 +		   RK817_POWER_EN_REG(1), ENABLE_MASK(0), BIT(0),
57774  		   DISABLE_VAL(0), 400),
57792 -		   RK817_POWER_EN_REG(2), ENABLE_MASK(0),
57793 +		   RK817_POWER_EN_REG(2), ENABLE_MASK(0), BIT(0),
57794  		   DISABLE_VAL(0), 400),
57812 -		   RK817_POWER_EN_REG(3), ENABLE_MASK(0),
57813 +		   RK817_POWER_EN_REG(3), ENABLE_MASK(0), BIT(0),
57814  		   DISABLE_VAL(0), 400),
57828  		   RK817_LDO_ON_VSEL_REG(0), RK817_LDO_VSEL_MASK,
57829 -		   RK817_POWER_EN_REG(1), ENABLE_MASK(0),
57830 +		   RK817_POWER_EN_REG(1), ENABLE_MASK(0), BIT(0),
57831  		   DISABLE_VAL(0), 400),
57849 -		   RK817_POWER_EN_REG(2), ENABLE_MASK(0),
57850 +		   RK817_POWER_EN_REG(2), ENABLE_MASK(0), BIT(0),
57851  		   DISABLE_VAL(0), 400),
57869 -		   RK817_POWER_EN_REG(3), ENABLE_MASK(0),
57870 +		   RK817_POWER_EN_REG(3), ENABLE_MASK(0), BIT(0),
57871  		   DISABLE_VAL(0), 400),
57920 index 0fb79c4af..b0f3c560c 100644
57925  	if (ret < 0)
57929  	if (buf[0] & HYM8563_SEC_VL) {
57936  	tm->tm_sec = bcd2bin(buf[0] & HYM8563_SEC_MASK);
57941  				alm_tm->tm_hour = 0;
57944 -					alm_tm->tm_mday = 0;
57947 +					alm_tm->tm_wday = 0;
57967 +					if (alm_tm->tm_year / 4 == 0) {
57980  	if (ret < 0)
57991 +		.tm_wday = 0,
57993 +		.tm_mon = 0,
57996 +		.tm_min = 0,
57997 +		.tm_sec = 0,
58015 +	if (client->irq > 0 ||
58022  	if (ret < 0)
58031 +	    (tm_read.tm_mon == -1) || (rtc_valid_tm(&tm_read) != 0))
58234 +#define PX30_GRF_SOC_CON5		0x414
58241 +	{ "jtag switching delay", PX30_GRF_SOC_CON5, 0x7270E00},
58249  #define RK3036_GRF_SOC_CON0		0x140
58256 +#define RK3308_GRF_SOC_CON3		0x30c
58259 +	{ "uart dma mask", RK3308_GRF_SOC_CON3, HIWORD_UPDATE(0, 0x1f, 10) },
58267  #define RK3368_GRF_SOC_CON15		0x43c
58274 +#define DELAY_ONE_SECOND		0x16E3600
58276 +#define RV1126_GRF1_SDDETFLT_CON	0x10254
58277 +#define RV1126_GRF1_UART2RX_LOW_CON	0x10258
58278 +#define RV1126_GRF1_IOFUNC_CON1		0x10264
58279 +#define RV1126_GRF1_IOFUNC_CON3		0x1026C
58280 +#define RV1126_JTAG_GROUP0		0x0      /* mux to sdmmc*/
58281 +#define RV1126_JTAG_GROUP1		0x1      /* mux to uart2 */
58282 +#define FORCE_JTAG_ENABLE		0x1
58283 +#define FORCE_JTAG_DISABLE		0x0
58329  	return 0;
58343 +#define RK3568_PMU_GRF_IO_VSEL0		(0x0140)
58344 +#define RK3568_PMU_GRF_IO_VSEL1		(0x0144)
58345 +#define RK3568_PMU_GRF_IO_VSEL2		(0x0148)
58366 +	case 0: /* pmuio1 */
58370 +		val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
58372 +		val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
58386 +		val0 = BIT(16 + b) | (is_3v3 ? 0 : BIT(b));
58387 +		val1 = BIT(16 + b) | (is_3v3 ? BIT(b) : 0);
58396 +	return 0;
58416 +	.grf_offset = 0x140,
58431  	.grf_offset = 0x404,
58438 +	.grf_offset = 0x140,
58673 +	DOMAIN_M_O(name, pwr, pwr, 0, req, idle, idle, r_offset, wakeup, false)
58722 +	u32 pd_req_offset = 0;
58727 +	int ret = 0;
58732  	if (pd_info->req_mask == 0)
58733  		return 0;
58741 -				   pd_info->req_mask, idle ? -1U : 0);
58744 +				   idle ? -1U : 0);
58749  					0, 10000);
58752 -			"failed to get ack on domain '%s', val=0x%x\n",
58755 +			"failed to get ack on domain '%s', target_idle = %d, target_ack = %d, val=0x%x\n",
58761  					is_idle, is_idle == idle, 0, 10000);
58772 -	return 0;
58805  	return 0;
58866  	if (pd->info->status_mask == 0)
58879 +	u32 pd_pwr_offset = 0;
58881 +	int ret = 0;
58886  	if (pd->info->pwr_mask == 0)
58888 +		return 0;
58896 -				   pd->info->pwr_mask, on ? 0 : -1U);
58899 +				   on ? 0 : -1U);
58904 -				      is_on == on, 0, 10000)) {
58906 +					is_on == on, 0, 10000);
58927 +	int ret = 0;
58932 +		return 0;
58944 +			if (ret < 0) {
58953  		if (ret < 0) {
59005 -	return 0;
59015 +		return 0;
59025 +		return 0;
59105 +	for (i = 0; i < pd->num_qos; i++) {
59106 +		if (qos_is_need_init[0][i])
59109 +				     pd->qos_save_regs[0][i]);
59142 +	int num_qos = 0, num_qos_reg = 0;
59157 +		return 0;
59169  	if (pd->num_clks > 0) {
59178 +	for (j = 0; j < num_qos; j++) {
59185  	if (pd->num_qos > 0) {
59191 -		for (j = 0; j < MAX_QOS_REGS_NUM; j++) {
59200 +		pd->qos_save_regs[0] = (u32 *)devm_kmalloc(pmu->dev,
59205 +		if (!pd->qos_save_regs[0]) {
59209 +		qos_is_need_init[0] = kzalloc(sizeof(bool) *
59213 +		if (!qos_is_need_init[0]) {
59223 -		for (j = 0; j < pd->num_qos; j++) {
59224 +		for (j = 0; j < num_qos; j++) {
59246 +					pd->qos_save_regs[0][j] = val;
59247 +					qos_is_need_init[0][j] = true;
59327 +		rockchip_pd_qos_init(pd, &qos_is_need_init[0]);
59329 +	kfree(qos_is_need_init[0]);
59334  	return 0;
59337 +	kfree(qos_is_need_init[0]);
59347  	pd->num_clks = 0;
59393 +			enable_count = 0;
59413 +		return 0;
59415 +	for (i = 0; i < g_pmu->genpd_data.num_domains; i++) {
59423 +	return 0;
59436 +			       0x100, false);
59467 +	reg_base = of_iomap(parent->of_node, 0);
59486  	return 0;
59533 -	[RK3066_PD_CPU]		= DOMAIN(0,      BIT(5), BIT(1), BIT(26), BIT(31), false),
59538 +	[RK3066_PD_CPU]		= DOMAIN("cpu",   0,      BIT(5), BIT(1), BIT(26), BIT(31), false, false),
59542 -	[RK3128_PD_CORE]	= DOMAIN_RK3288(BIT(0), BIT(0), BIT(4), false),
59543 -	[RK3128_PD_MSCH]	= DOMAIN_RK3288(0,      0,      BIT(6), true),
59547 +	[RK3128_PD_CORE]        = DOMAIN_RK3288("core",        BIT(0), BIT(0), BIT(4), false),
59548 +	[RK3128_PD_MSCH]        = DOMAIN_RK3288("msch",        0,      0,      BIT(6), true),
59568 -	[RK3228_PD_CORE]	= DOMAIN_RK3036(BIT(0),  BIT(0),  BIT(16), true),
59579 +	[RK3228_PD_CORE]	= DOMAIN_RK3036("core", BIT(0),  BIT(0),  BIT(16), true),
59604 -	[RK3328_PD_CORE]	= DOMAIN_RK3328(0, BIT(0), BIT(0), false),
59605 -	[RK3328_PD_GPU]		= DOMAIN_RK3328(0, BIT(1), BIT(1), false),
59606 -	[RK3328_PD_BUS]		= DOMAIN_RK3328(0, BIT(2), BIT(2), true),
59607 -	[RK3328_PD_MSCH]	= DOMAIN_RK3328(0, BIT(3), BIT(3), true),
59608 -	[RK3328_PD_PERI]	= DOMAIN_RK3328(0, BIT(4), BIT(4), true),
59609 -	[RK3328_PD_VIDEO]	= DOMAIN_RK3328(0, BIT(5), BIT(5), false),
59610 -	[RK3328_PD_HEVC]	= DOMAIN_RK3328(0, BIT(6), BIT(6), false),
59611 -	[RK3328_PD_VIO]		= DOMAIN_RK3328(0, BIT(8), BIT(8), false),
59612 -	[RK3328_PD_VPU]		= DOMAIN_RK3328(0, BIT(9), BIT(9), false),
59613 +	[RK3328_PD_CORE]	= DOMAIN_RK3328("core",  0, BIT(0), BIT(0), false),
59614 +	[RK3328_PD_GPU]		= DOMAIN_RK3328("gpu",   0, BIT(1), BIT(1), false),
59615 +	[RK3328_PD_BUS]		= DOMAIN_RK3328("bus",   0, BIT(2), BIT(2), true),
59616 +	[RK3328_PD_MSCH]	= DOMAIN_RK3328("msch",  0, BIT(3), BIT(3), true),
59617 +	[RK3328_PD_PERI]	= DOMAIN_RK3328("peri",  0, BIT(4), BIT(4), true),
59618 +	[RK3328_PD_VIDEO]	= DOMAIN_RK3328("video", 0, BIT(5), BIT(5), false),
59619 +	[RK3328_PD_HEVC]	= DOMAIN_RK3328("hevc",  0, BIT(6), BIT(6), false),
59620 +	[RK3328_PD_VIO]		= DOMAIN_RK3328("vio",   0, BIT(8), BIT(8), false),
59621 +	[RK3328_PD_VPU]		= DOMAIN_RK3328("vpu",   0, BIT(9), BIT(9), false),
59655 -	[RK3399_PD_TCPD0]	= DOMAIN_RK3399(BIT(8),  BIT(8),  0,	   false),
59656 -	[RK3399_PD_TCPD1]	= DOMAIN_RK3399(BIT(9),  BIT(9),  0,	   false),
59657 -	[RK3399_PD_CCI]		= DOMAIN_RK3399(BIT(10), BIT(10), 0,	   true),
59658 -	[RK3399_PD_CCI0]	= DOMAIN_RK3399(0,	 0,	  BIT(15), true),
59659 -	[RK3399_PD_CCI1]	= DOMAIN_RK3399(0,	 0,	  BIT(16), true),
59664 -	[RK3399_PD_GPU]		= DOMAIN_RK3399(BIT(15), BIT(15), BIT(0),  false),
59669 -	[RK3399_PD_VO]		= DOMAIN_RK3399(BIT(20), BIT(20), 0,	   false),
59670 -	[RK3399_PD_VOPB]	= DOMAIN_RK3399(0,	 0,	  BIT(7),  false),
59671 -	[RK3399_PD_VOPL]	= DOMAIN_RK3399(0, 	 0,	  BIT(8),  false),
59682 +	[RK3399_PD_TCPD0]	= DOMAIN_RK3399("tcpd0",        BIT(8),  BIT(8),  0,       false),
59683 +	[RK3399_PD_TCPD1]	= DOMAIN_RK3399("tcpd1",        BIT(9),  BIT(9),  0,       false),
59684 +	[RK3399_PD_CCI]		= DOMAIN_RK3399("cci",          BIT(10), BIT(10), 0,       true),
59685 +	[RK3399_PD_CCI0]	= DOMAIN_RK3399("cci0",         0,       0,       BIT(15), true),
59686 +	[RK3399_PD_CCI1]	= DOMAIN_RK3399("cci1",         0,       0,       BIT(16), true),
59691 +	[RK3399_PD_GPU]		= DOMAIN_RK3399("gpu",          BIT(15), BIT(15), BIT(0),  false),
59696 +	[RK3399_PD_VO]		= DOMAIN_RK3399_PROTECT("vo",   BIT(20), BIT(20), 0,       false),
59697 +	[RK3399_PD_VOPB]	= DOMAIN_RK3399_PROTECT("vopb", 0,       0,       BIT(7),  false),
59698 +	[RK3399_PD_VOPL]	= DOMAIN_RK3399_PROTECT("vopl", 0,       0,       BIT(8),  false),
59746  #define CR0_OPM_MASTER				0x0
59747  #define CR0_OPM_SLAVE				0x1
59751  #define CR0_MTM_OFFSET				0x21
59759 -#define SR_MASK						0x1f
59761 +#define SR_MASK						0x3f
59762  #define SR_BUSY						(1 << 0)
59770  #define INT_MASK					0x1f
59780  #define ICR_MASK					0x0f
59789   * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
59792  #define ROCKCHIP_SPI_MAX_TRANLEN		0xffff
59797  #define ROCKCHIP_SPI_VER2_TYPE1			0x05EC0002
59798  #define ROCKCHIP_SPI_VER2_TYPE2			0x00110002
59812  	writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR);
59870 +		writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
59871 +		writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
59882  		writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
59883 +		writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
59897  	rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0;
59913 +		writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
59929  	atomic_set(&rs->state, 0);
59962  	cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET;
60023 -	atomic_set(&rs->state, 0);
60024 +		atomic_set(&rs->state, 0);
60027 +			rs->xfer->len = 0;
60138  	if (ret < 0) {
60153 index 0e985823c..7f1eb0e16 100644
60196  	TSHUT_MODE_CRU = 0,
60254   * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
60255   * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
60294  #define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
60295 +#define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
60297  #define GRF_SARADC_TESTBIT			0x0e644
60298  #define GRF_TSADC_TESTBIT_L			0x0e648
60301  #define PX30_GRF_SOC_CON2			0x0408
60303 +#define RK1808_BUS_GRF_SOC_CON0			0x0400
60305 +#define RK3568_GRF_TSADC_CON			0x0600
60306 +#define RK3568_GRF_TSADC_ANA_REG0		(0x10001 << 0)
60307 +#define RK3568_GRF_TSADC_ANA_REG1		(0x10001 << 1)
60308 +#define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
60309 +#define RK3568_GRF_TSADC_TSEN			(0x10001 << 8)
60311 +#define RV1126_GRF0_TSADC_CON			0x0100
60313 +#define RV1126_GRF0_TSADC_TRM			(0xff0077 << 0)
60314 +#define RV1126_GRF0_TSADC_SHUT_2CRU		(0x30003 << 10)
60315 +#define RV1126_GRF0_TSADC_SHUT_2GPIO		(0x70007 << 12)
60317  #define GRF_SARADC_TESTBIT_ON			(0x10001 << 2)
60318  #define GRF_TSADC_TESTBIT_H_ON			(0x10001 << 2)
60319 +#define GRF_TSADC_BANDGAP_CHOPPER_EN		(0x10001 << 2)
60320  #define GRF_TSADC_VCM_EN_L			(0x10001 << 7)
60321  #define GRF_TSADC_VCM_EN_H			(0x10001 << 7)
60323  #define GRF_CON_TSADC_CH_INV			(0x10001 << 1)
60339  	{0, -40000},
60346 +	{0, -40000},
60355 +	{3519, 0},
60385  	{0, -40000},
60392 +	{0, -40000},
60401 +	{1856, 0},
60440  	low = 0;
60451 +		return 0;
60465 +		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
60468 +		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
60509 +		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
60512 +		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
60529  	return 0;
60598  	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
60601  	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
60614 +	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
60640 +	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
60664  	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
60713 +	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
60821 +	*value = buf[0];
60825 +	return 0;
60834 +	int trim_l = 0, trim_h = 0, trim_bsae = 0;
60874  	return 0;
60901 +	for (i = 0; i < thermal->chip->chn_num; i++) {
60913 +			       32, 4, thermal->regs, 0x88, false);
61012  	for (i = 0; i < thermal->chip->chn_num; i++) {
61044  	return 0;
61063  	return 0;
61071 +	for (i = 0; i < thermal->chip->chn_num; i++) {
61098  	return 0;
61118  	for (i = 0; i < thermal->chip->chn_num; i++) {
61127  	for (i = 0; i < thermal->chip->chn_num; i++)
61134  	return 0;
61225  	for (i = 0; i < nr_uarts; i++) {
61268 +#define UART_RFL_16550A		0x21
61286 +	unsigned int		count = 0, cur_index = 0;
61345 +	unsigned int rfl, i = 0, fcr = 0, cur_index = 0;
61372 +	return 0;
61393 +	dma->rx_index = 0;
61394 +	return 0;
61403  	return 0;
61514  	return 0;
61526 +	dma->rx_running = 0;
61534 -	dma->tx_running = 0;
61542 +		dma->tx_running = 0;
61554  #define DW_UART_USR	0x1f /* UART Status Register */
61555 +#define DW_UART_RFL	0x21 /* UART Receive Fifo Level Register */
61591 -	if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
61592 +	if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
61599 +		if (!(status & (UART_LSR_DR | UART_LSR_BI)) && !(usr & 0x1) && (rfl == 0))
61651  	if (rate > 0) {
61679 +		data->enable_wakeup = 0;
61706  	return 0;
61716 +		return 0;
61720  	return 0;
61730 +			data->irq_wake = 0;
61732 +		return 0;
61736  	return 0;
61749 +	 * The UART CPR may be 0 of some rockchip soc,
61752 +	if (reg == 0)
61753 +		reg = 0x00023ff2;
61791 +	if ((iir & 0xf) != UART_IIR_RX_TIMEOUT)
61792 +		return 0;
61796  	switch (iir & 0x3f) {
61816  		return 0;
61845 +	    ((iir & 0xf) == UART_IIR_THRI))
61914  	if ((termios->c_cflag & CREAD) == 0)
61928  		unsigned char efr = 0;
61935 +	serial_port_out(port, 0x88 >> 2, 0x7);
62013  	{ USB_DEVICE(0x058f, 0x9254), .driver_info = USB_QUIRK_RESET_RESUME },
62016 +	{ USB_DEVICE(0x05a3, 0x9230), .driver_info = USB_QUIRK_AUTO_SUSPEND },
62017 +	{ USB_DEVICE(0x05a3, 0x9320), .driver_info = USB_QUIRK_AUTO_SUSPEND },
62020  	{ USB_DEVICE(0x05ac, 0x021a), .driver_info = USB_QUIRK_RESET_RESUME },
62024  	{ USB_DEVICE(0x0bda, 0x8153), .driver_info = USB_QUIRK_NO_LPM },
62027 +	{ USB_DEVICE(0x0c45, 0x64ab), .driver_info = USB_QUIRK_AUTO_SUSPEND },
62028 +	{ USB_DEVICE(0x0c45, 0x64ac), .driver_info = USB_QUIRK_AUTO_SUSPEND },
62031  	{ USB_DEVICE(0x0c45, 0x7056), .driver_info =
62130  		ssp_cap->bReserved = 0;
62131  		ssp_cap->wReserved = 0;
62142 +			cpu_to_le16(FIELD_PREP(USB_SSP_MIN_SUBLINK_SPEED_ATTRIBUTE_ID, 0) |
62147 -		 * bmSublinkSpeedAttr[0]:
62153 -		ssp_cap->bmSublinkSpeedAttr[0] =
62154 -			cpu_to_le32((3 << 4) | (1 << 14) | (0xa << 16));
62163 +		 * - SSID 0 for symmetric RX/TX sublink speed of 10 Gbps.
62166 +		 * - SSID 0 for symmetric RX/TX sublink speed of 5 Gbps.
62169 +		 * - SSID 0 for symmetric RX/TX sublink speed of 5 Gbps.
62174 -				    (0xa << 16) | (1 << 7));
62175 +		for (i = 0; i < ssac + 1; i++) {
62220 +	usb_gadget_vbus_draw(gadget, 0);
62274 +			MKDEV(0, index++), NULL, name);
62302 +	if (!strlen(name) || strcmp(name, "none") == 0) {
62314  		c->next_interface_id = 0;
62315  		memset(c->interface, 0, sizeof(c->interface));
62328 +	/* 0-connected 1-configured 2-disconnected*/
62339 +			status[0] = true;
62346 +	if (status[0]) {
62348 +		pr_info("%s: sent uevent %s\n", __func__, connected[0]);
62354 +		pr_info("%s: sent uevent %s\n", __func__, configured[0]);
62360 +		pr_info("%s: sent uevent %s\n", __func__, disconnected[0]);
62398 +			if (value >= 0)
62404 +	if (value < 0)
62408 +	if (value < 0)
62455 +	gi->connected = 0;
62548 +			MKDEV(0, 0), NULL, "android%d", gadget_index++);
62568 +	return 0;
62584 +	return 0;
62599 +	if (android_device_create(gi) < 0)
62667 +			/* mult: bits 1:0 of bmAttributes */
62668 +			ep->mult = (ep_comp->bmAttributes & 0x3) + 1;
62737  	.iInterface		= 0,
62744 +	.bAlternateSetting	= 0,
62748 +	.bInterfaceProtocol	= 0x00,
62749 +	.iInterface		= 0,
62866  		uvc->event_setup_out = 0;
62891  		return 0;
62896  		return uvc->video.ep->enabled ? 1 : 0;
62905 +		return 0;
62928 +			memset(&v4l2_event, 0, sizeof(v4l2_event));
62931 +			uvc->event_suspend = 0;
62936  			memset(&v4l2_event, 0, sizeof(v4l2_event));
62944 -		return alt ? -EINVAL : 0;
62948 +		case 0:
62950 +				return 0;
62955 +			memset(&v4l2_event, 0, sizeof(v4l2_event));
62960 -	case 0:
62963  			return 0;
62969 +				return 0;
62971 -		memset(&v4l2_event, 0, sizeof(v4l2_event));
62978 -		return 0;
62984 -			return 0;
62992 +			memset(&v4l2_event, 0, sizeof(v4l2_event));
63018 +				memset(&v4l2_event, 0, sizeof(v4l2_event));
63024 +			return 0;
63030 +				INFO(cdev, "bulk streaming intf not support alt 0\n");
63031 +				return 0;
63046 -		memset(&v4l2_event, 0, sizeof(v4l2_event));
63050 +			memset(&v4l2_event, 0, sizeof(v4l2_event));
63054 +			return 0;
63073 +	memset(&v4l2_event, 0, sizeof(v4l2_event));
63085 +	memset(&v4l2_event, 0, sizeof(v4l2_event));
63088 +	uvc->event_suspend = 0;
63154  	control_size = 0;
63155  	streaming_size = 0;
63198  	/* For SS, wMaxPacketSize has to be 1024 if bMaxBurst is not 0 */
63262 +		uvc_ss_bulk_streaming_comp.wBytesPerInterval = 0;
63349  	if ((ret = usb_interface_id(c, f)) < 0)
63352  	if ((ret = usb_interface_id(c, f)) < 0)
63368  	if (ret < 0)
63375  	if (ret < 0) {
63386  	od->iTerminal			= 0;
63393 +	ed->guidExtensionCode[0] = 0xa2;
63394 +	ed->guidExtensionCode[1] = 0x9e;
63395 +	ed->guidExtensionCode[2] = 0x76;
63396 +	ed->guidExtensionCode[3] = 0x41;
63397 +	ed->guidExtensionCode[4] = 0xde;
63398 +	ed->guidExtensionCode[5] = 0x04;
63399 +	ed->guidExtensionCode[6] = 0x47;
63400 +	ed->guidExtensionCode[7] = 0xe3;
63401 +	ed->guidExtensionCode[8] = 0x8b;
63402 +	ed->guidExtensionCode[9] = 0x2b;
63403 +	ed->guidExtensionCode[10] = 0xf4;
63404 +	ed->guidExtensionCode[11] = 0x34;
63405 +	ed->guidExtensionCode[12] = 0x1a;
63406 +	ed->guidExtensionCode[13] = 0xff;
63407 +	ed->guidExtensionCode[14] = 0x00;
63408 +	ed->guidExtensionCode[15] = 0x3b;
63411 +	ed->baSourceID[0] = 2;
63413 +	ed->bmControls[0] = 7;
63414 +	ed->iExtension = 0;
63442 +	opts->pm_qos_latency = 0;
63445  	if (ret < 0) {
63506 index 6c4fc4913..0ea4405ff 100644
63554 index cab1e3046..0f5e6fb93 100644
63563 +	 * use bytesused == 0 as a way to indicate that the data
63587  	{ 0,  V4L2_PIX_FMT_MJPEG },
63588 +	{ 0,  V4L2_PIX_FMT_H264  },
63589 +	{ 0,  V4L2_PIX_FMT_H265  },
63617  	return 0;
63651  		video->payload_size = 0;
63672 -	for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
63676 +	for (i = 0; i < opts->uvc_num_request; ++i) {
63704 -	for (i = 0; i < UVC_NUM_REQUESTS; ++i) {
63705 +	for (i = 0; i < opts->uvc_num_request; ++i) {
63727  		uvcg_queue_cancel(&video->queue, 0);
63729 -		for (i = 0; i < UVC_NUM_REQUESTS; ++i)
63730 +		for (i = 0; i < opts->uvc_num_request; ++i)
63735  		uvcg_queue_enable(&video->queue, 0);
63738  		return 0;
63742  	if ((ret = uvcg_queue_enable(&video->queue, 1)) < 0)
63751  	int ret = 0;
63766 +		if (le16_to_cpu(us->pusb_dev->descriptor.idVendor) == 0x05e3 &&
63767 +		    le16_to_cpu(us->pusb_dev->descriptor.idProduct) == 0x0749)
63777 @@ -927,6 +927,12 @@ UNUSUAL_DEV(  0x05e3, 0x0723, 0x9451, 0x9451,
63781 +UNUSUAL_DEV(  0x05e3, 0x0749, 0x0000, 0xffff,
63794 @@ -76,6 +76,12 @@ UNUSUAL_DEV(0x0b05, 0x1932, 0x0000, 0x9999,
63798 +UNUSUAL_DEV(0x0bc2, 0x2321, 0x0000, 0x9999,
63805  UNUSUAL_DEV(0x0bc2, 0x331a, 0x0000, 0x9999,
63807 @@ -118,6 +124,12 @@ UNUSUAL_DEV(0x152d, 0x0578, 0x0000, 0x9999,
63811 +UNUSUAL_DEV(0x152d, 0x0583, 0x0000, 0x9999,
63818  UNUSUAL_DEV(0x154b, 0xf00b, 0x0000, 0x9999,
63820 @@ -139,6 +151,12 @@ UNUSUAL_DEV(0x17ef, 0x3899, 0x0000, 0x9999,
63824 +UNUSUAL_DEV(0x174c, 0x55aa, 0x0000, 0x9999,
63831  UNUSUAL_DEV(0x2109, 0x0711, 0x0000, 0x9999,