| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGSDNodes.h | 141 unsigned DefIdx; variable
|
| D | ScheduleDAGSDNodes.cpp | 651 unsigned DefIdx = Use->getOperand(OpIdx).getResNo(); in computeOperandLatency() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 181 bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, in hasPipelineForwarding()
202 int getOperandLatency(unsigned DefClass, unsigned DefIdx, in getOperandLatency()
|
| D | MCSubtargetInfo.h | 170 unsigned DefIdx) const { in getWriteLatencyEntry()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 620 int DefIdx = SwapMap[DefMI]; in formWebs() local
701 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs() local
777 int DefIdx = SwapMap[DefMI]; in markSwapsForRemoval() local
|
| D | PPCInstrInfo.h | 217 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
225 unsigned DefIdx) const override { in hasLowDefLatency()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 158 unsigned DefIdx = 0; in findDefIdx() local
218 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency() local
|
| D | TargetInstrInfo.cpp | 1037 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
1189 unsigned DefIdx, in getOperandLatency()
1214 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs()
1241 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs()
1266 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs()
|
| D | LiveRangeCalc.cpp | 67 SlotIndex DefIdx = in createDeadDef() local
199 unsigned DefIdx; in extendToUses() local
|
| D | LiveRangeEdit.cpp | 149 SlotIndex DefIdx; in canRematerializeAt() local
|
| D | RenameIndependentSubregs.cpp | 335 SlotIndex DefIdx = LIS->InsertMachineInstrInMaps(*ImpDef); in computeMainRangesFixFlags() local
|
| D | MachineCombiner.cpp | 194 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); in getDepth() local
|
| D | TargetRegisterInfo.cpp | 352 unsigned SrcIdx, DefIdx; in shareSameRegisterFile() local
|
| D | MachineVerifier.cpp | 1672 unsigned DefIdx; in visitMachineOperand() local
1892 unsigned MONum, SlotIndex DefIdx, const LiveRange &LR, unsigned VRegOrUnit, in checkLivenessAtDef()
2064 SlotIndex DefIdx = LiveInts->getInstructionIndex(*MI); in checkLiveness() local
|
| D | MachineInstr.cpp | 281 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO); in addOperand() local
846 unsigned DefIdx; in getRegClassConstraint() local
1050 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/ |
| D | MCSchedule.cpp | 43 for (unsigned DefIdx = 0, DefEnd = SCDesc.NumWriteLatencyEntries; in computeInstrLatency() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | LegalizationArtifactCombiner.h | 327 for (unsigned j = 0, DefIdx = Idx * NewNumDefs; j < NewNumDefs; in tryCombineMerges() local
363 for (unsigned DefIdx = 0; DefIdx < NumDefs; ++DefIdx) { in tryCombineMerges() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 3746 unsigned DefIdx, unsigned DefAlign) const { in getVLDMDefCycle()
3803 unsigned DefIdx, unsigned DefAlign) const { in getLDMDefCycle()
3906 unsigned DefIdx, unsigned DefAlign, in getOperandLatency()
4017 unsigned &DefIdx, unsigned &Dist) { in getBundledDefMI()
4250 unsigned DefIdx, in getOperandLatency()
4286 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj, in getOperandLatencyImpl()
4346 SDNode *DefNode, unsigned DefIdx, in getOperandLatency()
4692 unsigned DefIdx, in hasHighOperandLatency()
5245 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
5272 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregLikeInputs()
[all …]
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 204 unsigned DefIdx = 0; in tryInlineAsm() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1145 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceLikeInputs()
1159 unsigned DefIdx, in getExtractSubregLikeInputs()
1173 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, in getInsertSubregLikeInputs()
1498 const MachineInstr &DefMI, unsigned DefIdx, in hasHighOperandLatency()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64CollectLOH.cpp | 536 int DefIdx = mapRegToGPRIndex(Def.getReg()); in runOnMachineFunction() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 217 for (unsigned DefIdx = 0, DefEnd = SCDesc->NumWriteLatencyEntries; in getLatency() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 150 int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO); in constrainSelectedInstRegOperands() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonSubtarget.cpp | 424 int DefIdx = -1; in restoreLatency() local
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegStackify.cpp | 620 SlotIndex DefIdx = LIS.getInstructionIndex(*Def).getRegSlot(); in moveAndTeeForMultiUse() local
|