| /kernel/linux/linux-6.6/arch/arm/mach-imx/ |
| D | anatop.c | 16 #define REG_SET 0x4 macro
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| /kernel/linux/linux-5.10/arch/arm/mach-imx/ |
| D | anatop.c | 16 #define REG_SET 0x4 macro
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_reg.h | 61 #define REG_SET(reg_name, initial_val, field, val) \ macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dmub/src/ |
| D | dmub_reg.h | 61 #define REG_SET(reg_name, initial_val, field, val) \ macro
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| /kernel/linux/linux-6.6/drivers/phy/freescale/ |
| D | phy-fsl-imx8qm-lvds-phy.c | 18 #define REG_SET 0x4 macro
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| /kernel/linux/linux-6.6/drivers/gpu/drm/mxsfb/ |
| D | mxsfb_regs.h | 12 #define REG_SET 4 macro
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| D | lcdif_regs.h | 11 #define REG_SET 4 macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/mxsfb/ |
| D | mxsfb_regs.h | 12 #define REG_SET 4 macro
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| /kernel/linux/linux-6.6/drivers/thermal/ |
| D | imx_thermal.c | 20 #define REG_SET 0x4 macro
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| /kernel/linux/linux-5.10/drivers/thermal/ |
| D | imx_thermal.c | 20 #define REG_SET 0x4 macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 63 #define REG_SET(reg_name, initial_val, field, val) \ macro
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 63 #define REG_SET(reg_name, initial_val, field, val) \ macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu.h | 1072 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu.h | 1175 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro
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| /kernel/linux/linux-5.10/drivers/pinctrl/ |
| D | pinctrl-ingenic.c | 50 #define REG_SET(x) ((x) + 0x4) macro
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| /kernel/linux/linux-6.6/drivers/pinctrl/ |
| D | pinctrl-ingenic.c | 72 #define REG_SET(x) ((x) + 0x4) macro
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| /kernel/linux/linux-5.10/drivers/gpu/drm/radeon/ |
| D | radeon.h | 2524 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro
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| /kernel/linux/linux-6.6/drivers/gpu/drm/radeon/ |
| D | radeon.h | 2510 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro
|