| /third_party/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 87 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble()
98 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble()
114 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat()
125 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) { in UFixedToFloat()
141 SimFloat16 Simulator::FixedToFloat16(int64_t src, int fbits, FPRounding round) { in FixedToFloat16()
153 int fbits, in UFixedToFloat16()
5845 int fbits) { in fcvts()
5881 int fbits) { in fcvts()
5900 int fbits) { in fcvtu()
5936 int fbits) { in fcvtu()
[all …]
|
| D | assembler-aarch64.cc | 3178 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs()
3197 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu()
3211 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzu()
3229 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf()
3247 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in scvtf()
3266 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf()
3280 void Assembler::ucvtf(const VRegister& vd, const Register& rn, int fbits) { in ucvtf()
|
| D | simulator-aarch64.cc | 5855 int fbits = 64 - instr->GetFPScale(); in Simulator() local
|
| /third_party/node/deps/v8/src/execution/arm64/ |
| D | simulator-logic-arm64.cc | 41 double Simulator::FixedToDouble(int64_t src, int fbits, FPRounding round) { in FixedToDouble()
51 double Simulator::UFixedToDouble(uint64_t src, int fbits, FPRounding round) { in UFixedToDouble()
66 float Simulator::FixedToFloat(int64_t src, int fbits, FPRounding round) { in FixedToFloat()
76 float Simulator::UFixedToFloat(uint64_t src, int fbits, FPRounding round) { in UFixedToFloat()
3760 FPRounding rounding_mode, int fbits) { in fcvts()
3779 FPRounding rounding_mode, int fbits) { in fcvtu()
4196 const LogicVRegister& src, int fbits, in scvtf()
4212 const LogicVRegister& src, int fbits, in ucvtf()
|
| D | simulator-arm64.cc | 3013 int fbits = 64 - instr->FPScale(); in VisitFPFixedPointConvert() local
|
| /third_party/node/deps/v8/src/codegen/arm64/ |
| D | assembler-arm64.cc | 2826 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf()
2836 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf()
2846 void Assembler::ucvtf(const VRegister& fd, const Register& rn, int fbits) { in ucvtf()
2967 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) { in fcvtzs()
2978 void Assembler::fcvtzs(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzs()
2988 void Assembler::fcvtzu(const Register& rd, const VRegister& vn, int fbits) { in fcvtzu()
2999 void Assembler::fcvtzu(const VRegister& vd, const VRegister& vn, int fbits) { in fcvtzu()
|
| D | macro-assembler-arm64-inl.h | 912 unsigned fbits) { in Scvtf()
992 unsigned fbits) { in Ucvtf()
|
| /third_party/ffmpeg/libavcodec/ |
| D | opus_silk.c | 164 int fbits; // fractional bits used for the gain in silk_is_lpc_stable() local
|
| D | mlpenc.c | 68 uint8_t fbits[MAX_CHANNELS]; ///< fraction bits member
|
| /third_party/vixl/test/aarch64/ |
| D | test-assembler-fp-aarch64.cc | 4647 for (int fbits = 1; fbits <= 32; fbits++) { in TestUScvtfHelper() local
4660 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtfHelper() local
4675 for (int fbits = 0; fbits <= 32; fbits++) { in TestUScvtfHelper() local
4683 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtfHelper() local
4802 for (int fbits = 1; fbits <= 32; fbits++) { in TestUScvtf32Helper() local
4815 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtf32Helper() local
4830 for (int fbits = 0; fbits <= 32; fbits++) { in TestUScvtf32Helper() local
4838 for (int fbits = 33; fbits <= 64; fbits++) { in TestUScvtf32Helper() local
|
| D | test-simulator-aarch64.cc | 1014 for (unsigned fbits = 0; fbits <= d_size; ++fbits) { in TestFPToFixed_Helper() local
1323 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedS() local
1401 for (unsigned fbits = 0; fbits <= d_bits; ++fbits, d++) { in TestFPToFixedU() local
|
| /third_party/python/Objects/ |
| D | floatobject.c | 2181 unsigned int fbits; in PyFloat_Pack4() local
|
| /third_party/vixl/src/aarch32/ |
| D | disasm-aarch32.cc | 4428 int32_t fbits) { in vcvt()
4439 int32_t fbits) { in vcvt()
4450 int32_t fbits) { in vcvt()
23878 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
23956 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
24224 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
24302 uint32_t fbits = offset - (((instr >> 5) & 0x1) | in DecodeT32() local
36096 uint32_t fbits = in DecodeT32() local
38262 uint32_t fbits = in DecodeT32() local
47736 uint32_t fbits = 64 - ((instr >> 16) & 0x3f); in DecodeA32() local
[all …]
|
| D | macro-assembler-aarch32.h | 7691 int32_t fbits) { in Assembler()
7705 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in Assembler()
7714 int32_t fbits) { in Assembler()
7728 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in Assembler()
7737 int32_t fbits) { in Assembler()
7751 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { in Assembler()
|
| D | assembler-aarch32.h | 4247 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { in vcvt()
4258 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { in vcvt()
4269 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { in vcvt()
|
| D | assembler-aarch32.cc | 16315 int32_t fbits) { in vcvt()
16419 int32_t fbits) { in vcvt()
16455 int32_t fbits) { in vcvt()
|
| /third_party/skia/third_party/skcms/ |
| D | skcms.cc | 86 float fbits = (1.0f * (1<<23)) * (x + 121.274057500f in exp2f_() local
|