| /third_party/mesa3d/src/compiler/glsl/ |
| D | gl_nir_lower_packed_varyings.c | 398 unsigned writemask) in bitwise_assign_pack()
430 unsigned writemask = 0x3; in bitwise_assign_pack() local
484 nir_ssa_def *value, unsigned writemask) in bitwise_assign_unpack()
567 unsigned writemask, bool is_64bit) in create_store_deref()
619 nir_ssa_def *rhs_swizzle, unsigned writemask, in lower_arraylike()
683 nir_ssa_def *rhs_swizzle, unsigned writemask, in lower_varying()
852 unsigned writemask = ((1 << components) - 1) << location_frac; in lower_varying() local
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| D | ir_builder.h | 32 enum writemask { enum
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| D | gl_nir_lower_xfb_varying.c | 130 unsigned writemask = (1 << components) - 1; in copy_to_new_var() local
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| /third_party/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_opcodes.c | 486 unsigned int writemask, in rc_compute_sources_for_writemask()
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| D | radeon_pair_regalloc.c | 289 unsigned int writemask, in find_class()
332 unsigned int writemask = rc_variable_writemask_sum(variable); in variable_get_class() local
474 static int get_reg_id(unsigned int index, unsigned int writemask) in get_reg_id()
560 unsigned int chan, writemask = 0; in do_advanced_regalloc() local
628 unsigned int writemask = reg_get_writemask(reg); in do_advanced_regalloc() local
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| D | radeon_rename_regs.c | 74 unsigned writemask; in rc_rename_regs() local
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| D | radeon_variable.c | 302 unsigned int writemask; in get_variable_pair_helper() local
454 unsigned int writemask = 0; in rc_variable_writemask_sum() local
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| /third_party/mesa3d/src/compiler/nir/ |
| D | nir_lower_fragcolor.c | 81 nir_component_mask_t writemask = nir_intrinsic_write_mask(instr); in lower_fragcolor_instr() local
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| D | nir_opt_large_constants.c | 106 unsigned writemask, in handle_constant_store()
221 unsigned writemask = 0; in nir_opt_large_constants() local
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| D | nir_lower_const_arrays_to_uniforms.c | 56 nir_src *const_src, unsigned writemask) in set_const_initialiser()
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| D | nir_builder.h | 1388 nir_ssa_def *value, unsigned writemask, in nir_store_deref_with_access()
1398 nir_ssa_def *value, unsigned writemask) in nir_store_deref()
1450 unsigned writemask) in nir_store_var()
1480 nir_ssa_def *value, unsigned writemask) in nir_store_array_var()
1489 nir_ssa_def *value, unsigned writemask) in nir_store_array_var_imm()
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| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| D | sfn_instr_export.cpp | 36 static char *writemask_to_swizzle(int writemask, char *buf) in writemask_to_swizzle()
151 int align, int align_offset, int writemask, in ScratchIOInstr()
169 int align, int align_offset,int writemask, in ScratchIOInstr()
265 int writemask = 0; in from_string() local
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| /third_party/mesa3d/src/gallium/auxiliary/tgsi/ |
| D | tgsi_scan.c | 1034 unsigned writemask = 0; in get_inst_tessfactor_writemask() local
1058 unsigned writemask = 0; in get_block_tessfactor_writemask() local
1106 unsigned writemask; in get_if_block_tessfactor_writemask() local
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| D | tgsi_text.c | 443 uint *writemask ) in parse_opt_writemask()
812 uint writemask; in parse_dst_operand() local
1289 uint writemask; in parse_declaration() local
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| /third_party/mesa3d/src/gallium/frontends/d3d10umd/ |
| D | ShaderTGSI.c | 221 uint writemask; member
401 swizzle_reg(struct ureg_src src, uint writemask, in swizzle_reg()
427 unsigned writemask = in dcl_base_output() local
456 unsigned writemask = in dcl_base_input() local
709 unsigned writemask) in translate_operand()
821 unsigned writemask = in translate_dst_operand() local
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| /third_party/mesa3d/src/intel/compiler/ |
| D | brw_vec4.cpp | 106 unsigned writemask) in dst_reg()
117 unsigned writemask) in dst_reg()
406 unsigned writemask = 0; in opt_vector_float() local
2054 scalarize_predicate(brw_predicate predicate, unsigned writemask) in scalarize_predicate()
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| D | brw_vec4_nir.cpp | 347 unsigned writemask = 1 << i; in nir_emit_load_const() local
445 int writemask = WRITEMASK_X; in nir_emit_intrinsic() local
2153 int writemask = devinfo->ver == 4 ? WRITEMASK_W : WRITEMASK_X; in nir_emit_texture() local
2185 int mrf, writemask; in nir_emit_texture() local
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| D | brw_nir_lower_mem_access_bit_sizes.c | 173 nir_component_mask_t writemask = nir_intrinsic_write_mask(intrin); in lower_mem_store_bit_size() local
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| D | brw_vec4_tcs.cpp | 216 unsigned writemask, in emit_urb_write()
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| D | brw_ir_vec4.h | 205 writemask(dst_reg reg, unsigned mask) in writemask() function
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| /third_party/mesa3d/src/gallium/auxiliary/gallivm/ |
| D | lp_bld_nir_aos.c | 146 unsigned writemask, in emit_store_var()
183 unsigned writemask, in emit_store_reg()
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| D | lp_bld_nir.c | 1481 int writemask = instr->const_index[0]; in visit_store_var() local
1554 int writemask = instr->const_index[0]; in visit_store_ssbo() local
1826 int writemask = instr->const_index[1]; in visit_shared_store() local
1906 int writemask = instr->const_index[0]; in visit_store_global() local
1994 int writemask = instr->const_index[2]; in visit_store_scratch() local
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| /third_party/mesa3d/src/amd/vulkan/ |
| D | radv_nir_lower_ray_queries.c | 67 unsigned writemask) in nir_store_array()
84 unsigned writemask) in rq_store_var()
113 nir_ssa_def *value, unsigned writemask) in rq_store_array()
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| /third_party/mesa3d/src/gallium/drivers/i915/ |
| D | i915_state_emit.c | 125 uint32_t writemask = imm & S5_WRITEDISABLE_MASK; in emit_immediate_s5() local
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader_info.c | 72 unsigned writemask = nir_intrinsic_write_mask(intrin) << nir_intrinsic_component(intrin); in get_inst_tessfactor_writemask() local
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