| /kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | pllgt215.c | 36 *P = info->vco1.max_freq / freq; in gt215_pll_calc()
37 if (*P > info->max_p) in gt215_pll_calc()
38 *P = info->max_p; in gt215_pll_calc()
39 if (*P < info->min_p) in gt215_pll_calc()
40 *P = info->min_p; in gt215_pll_calc()
42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
43 lM = max(lM, (int)info->vco1.min_m); in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
45 hM = min(hM, (int)info->vco1.max_m); in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | pllgt215.c | 36 *P = info->vco1.max_freq / freq; in gt215_pll_calc()
37 if (*P > info->max_p) in gt215_pll_calc()
38 *P = info->max_p; in gt215_pll_calc()
39 if (*P < info->min_p) in gt215_pll_calc()
40 *P = info->min_p; in gt215_pll_calc()
42 lM = (info->refclk + info->vco1.max_inputfreq) / info->vco1.max_inputfreq; in gt215_pll_calc()
43 lM = max(lM, (int)info->vco1.min_m); in gt215_pll_calc()
44 hM = (info->refclk + info->vco1.min_inputfreq) / info->vco1.min_inputfreq; in gt215_pll_calc()
45 hM = min(hM, (int)info->vco1.max_m); in gt215_pll_calc()
50 N = tmp / info->refclk; in gt215_pll_calc()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | mediatek,mt7620-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7620-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
20 const: ralink,mt7620-pinctrl
23 '-pins$':
28 '^(.*-)?pinmux$':
31 $ref: pinmux-node.yaml#
[all …]
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| /kernel/linux/linux-6.6/drivers/phy/ti/ |
| D | phy-dm816x-usb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
47 struct clk *refclk; member
55 otg->host = host; in dm816x_usb_phy_set_host()
57 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_host()
65 otg->gadget = gadget; in dm816x_usb_phy_set_peripheral()
67 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_peripheral()
77 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
78 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
81 regmap_update_bits(phy->syscon, phy->usb_ctrl, in dm816x_usb_phy_init()
86 regmap_read(phy->syscon, phy->usb_ctrl, &val); in dm816x_usb_phy_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/phy/ti/ |
| D | phy-dm816x-usb.c | 56 struct clk *refclk; member
64 otg->host = host; in dm816x_usb_phy_set_host()
66 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_host()
74 otg->gadget = gadget; in dm816x_usb_phy_set_peripheral()
76 otg->state = OTG_STATE_UNDEFINED; in dm816x_usb_phy_set_peripheral()
86 if (clk_get_rate(phy->refclk) != 24000000) in dm816x_usb_phy_init()
87 dev_warn(phy->dev, "nonstandard phy refclk\n"); in dm816x_usb_phy_init()
90 regmap_update_bits(phy->syscon, phy->usb_ctrl, in dm816x_usb_phy_init()
95 regmap_read(phy->syscon, phy->usb_ctrl, &val); in dm816x_usb_phy_init()
97 dev_info(phy->dev, in dm816x_usb_phy_init()
[all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/usb/ |
| D | usb3503.txt | 1 SMSC USB3503 High-Speed Hub Controller
4 - compatible: Should be "smsc,usb3503" or "smsc,usb3503a".
7 - reg: Specifies the i2c slave address, it is required and should be 0x08
9 - connect-gpios: Should specify GPIO for connect.
10 - disabled-ports: Should specify the ports unused.
14 - intn-gpios: Should specify GPIO for interrupt.
15 - reset-gpios: Should specify GPIO for reset.
16 - initial-mode: Should specify initial mode.
18 - refclk: Clock used for driving REFCLK signal (optional, if not provided
22 clock-names in order to assign it
[all …]
|
| D | octeon-usb.txt | 7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
33 The main node must have one child node which describes the built-in
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| D | intel_cdclk.c | 2 * Copyright © 2006-2017 Intel Corporation
84 dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
91 dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
97 return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); in intel_cdclk_modeset_calc_cdclk()
103 return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk); in intel_cdclk_calc_voltage_level()
109 cdclk_config->cdclk = 133333; in fixed_133mhz_get_cdclk()
115 cdclk_config->cdclk = 200000; in fixed_200mhz_get_cdclk()
121 cdclk_config->cdclk = 266667; in fixed_266mhz_get_cdclk()
127 cdclk_config->cdclk = 333333; in fixed_333mhz_get_cdclk()
133 cdclk_config->cdclk = 400000; in fixed_400mhz_get_cdclk()
[all …]
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| D | intel_dpll.c | 1 // SPDX-License-Identifier: MIT
193 * the range value for them is (actual_value - 2).
234 /* LVDS 100mhz refclk limits. */
305 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
306 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
310 * divided-down version of it.
313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params() argument
315 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
316 clock->p = clock->p1 * clock->p2; in pnv_calc_dpll_params()
317 if (WARN_ON(clock->n == 0 || clock->p == 0)) in pnv_calc_dpll_params()
[all …]
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| D | intel_dpll.h | 1 /* SPDX-License-Identifier: MIT */
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
|
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/ |
| D | smsc,usb3503.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SMSC USB3503 High-Speed Hub Controller
10 - Dongjin Kim <tobetter@gmail.com>
15 - smsc,usb3503
16 - smsc,usb3503a
17 - smsc,usb3803
22 connect-gpios:
27 intn-gpios:
[all …]
|
| D | octeon-usb.txt | 7 - compatible: must be "cavium,octeon-5750-usbn"
9 - reg: specifies the physical base address of the USBN block and
12 - #address-cells: specifies the number of cells needed to encode an
15 - #size-cells: specifies the number of cells used to represent the size
18 - ranges: specifies the translation between child address space and parent
21 - clock-frequency: speed of the USB reference clock. Allowed values are
24 - cavium,refclk-type: type of the USB reference clock. Allowed values are
27 - refclk-frequency: deprecated, use "clock-frequency".
29 - refclk-type: deprecated, use "cavium,refclk-type".
33 The main node must have one child node which describes the built-in
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/gma500/ |
| D | gma_display.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2006-2011 Intel Corporation
44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
83 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
84 extern void gma_clock(int refclk, struct gma_clock_t *clock);
89 struct drm_crtc *crtc, int target, int refclk,
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/ |
| D | dcn32_dccg.c | 34 (dccg_dcn->regs->reg)
38 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
41 dccg_dcn->base.ctx
43 dccg->ctx->logger
161 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg32_set_dtbclk_p_src()
203 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
210 int req_dtbclk_khz = params->pixclk_khz / 4; in dccg32_set_dtbclk_dto()
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/phy/ |
| D | fsl,imx8-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
[all …]
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/gma500/ |
| D | gma_display.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2006-2011 Intel Corporation
44 int target, int refclk,
49 void (*clock)(int refclk, struct gma_clock_t *clock);
50 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk);
91 extern const struct gma_limit_t *gma_limit(struct drm_crtc *crtc, int refclk);
92 extern void gma_clock(int refclk, struct gma_clock_t *clock);
97 struct drm_crtc *crtc, int target, int refclk,
|
| /kernel/linux/linux-5.10/drivers/net/ethernet/arc/ |
| D | emac_rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emac-rockchip.c - Rockchip EMAC specific glue layer
32 struct clk *refclk; member
39 u32 speed_offset = emac->soc_data->grf_speed_offset; in emac_rockchip_set_mac_speed()
55 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data); in emac_rockchip_set_mac_speed()
77 .compatible = "rockchip,rk3036-emac",
81 .compatible = "rockchip,rk3066-emac",
85 .compatible = "rockchip,rk3188-emac",
95 struct device *dev = &pdev->dev; in emac_rockchip_probe()
103 if (!pdev->dev.of_node) in emac_rockchip_probe()
[all …]
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| /kernel/linux/linux-6.6/drivers/net/ethernet/arc/ |
| D | emac_rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emac-rockchip.c - Rockchip EMAC specific glue layer
32 struct clk *refclk; member
39 u32 speed_offset = emac->soc_data->grf_speed_offset; in emac_rockchip_set_mac_speed()
55 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data); in emac_rockchip_set_mac_speed()
77 .compatible = "rockchip,rk3036-emac",
81 .compatible = "rockchip,rk3066-emac",
85 .compatible = "rockchip,rk3188-emac",
95 struct device *dev = &pdev->dev; in emac_rockchip_probe()
103 if (!pdev->dev.of_node) in emac_rockchip_probe()
[all …]
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/loongson/ |
| D | lsdc_pixpll.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
14 * refclk: reference frequency, 100 MHz from external oscillator
19 * refclk +-----------+ +------------------+ +---------+ outclk
20 * ---+---> | Prescaler | ---> | Clock Multiplier | ---> | divider | -------->
21 * | +-----------+ +------------------+ +---------+ ^
27 * +---- bypass (bypass above software configurable clock if set) ----+
29 * outclk = refclk / div_ref * loopc / div_out;
38 * 1) 20 MHz <= refclk / div_ref <= 40Mhz
39 * 2) 1.2 GHz <= refclk /div_out * loopc <= 3.2 Ghz
|
| /kernel/linux/linux-5.10/drivers/phy/xilinx/ |
| D | phy-zynqmp.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
103 /* Refclk selection parameters */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185 * struct xpsgtr_phy - representation of a lane
192 * @refclk: reference clock index
201 unsigned int refclk; member
[all …]
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| /kernel/linux/linux-6.6/arch/mips/bcm63xx/ |
| D | clk.c | 33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
403 return clk->rate; in clk_get_rate()
423 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
424 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
440 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
441 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
[all …]
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| /kernel/linux/linux-5.10/arch/mips/bcm63xx/ |
| D | clk.c | 33 if (clk->set && (clk->usage++) == 0) in clk_enable_unlocked()
34 clk->set(clk, 1); in clk_enable_unlocked()
39 if (clk->set && (--clk->usage) == 0) in clk_disable_unlocked()
40 clk->set(clk, 0); in clk_disable_unlocked()
92 if (clk->id == 0) in enetx_set()
403 return clk->rate; in clk_get_rate()
423 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
424 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
440 CLKDEV_INIT("bcm63xx_uart.0", "refclk", &clk_periph),
441 CLKDEV_INIT("bcm63xx_uart.1", "refclk", &clk_periph),
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/mips/cavium/ |
| D | uctl.txt | 4 - compatible: "cavium,octeon-6335-uctl"
8 - reg: The base address of the UCTL register bank.
10 - #address-cells: Must be <2>.
12 - #size-cells: Must be <2>.
14 - ranges: Empty to signify direct mapping of the children.
16 - refclk-frequency: A single cell containing the reference clock
19 - refclk-type: A string describing the reference clock connection
24 compatible = "cavium,octeon-6335-uctl";
27 #address-cells = <2>;
28 #size-cells = <2>;
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn314/ |
| D | dcn314_dccg.c | 1 // SPDX-License-Identifier: MIT
37 (dccg_dcn->regs->reg)
41 dccg_dcn->dccg_shift->field_name, dccg_dcn->dccg_mask->field_name
44 dccg_dcn->base.ctx
46 dccg->ctx->logger
161 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
170 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
179 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
188 if (src == REFCLK) in dccg314_set_dtbclk_p_src()
203 /* Controls the generation of pixel valid for OTG in (OTG -> HPO case) */
[all …]
|