Searched +full:0 +full:x004a8000 (Results 1 – 12 of 12) sorted by relevance
133 reg = <0x4a9000 0x1000>, /* TM */134 <0x4a8000 0x1000>; /* SROT */151 reg = <0x004a9000 0x1000>, /* TM */152 <0x004a8000 0x1000>; /* SROT */169 reg = <0xc263000 0x1ff>,170 <0xc222000 0x1ff>;
123 - pattern: '^s[0-9]+_p1$'124 - pattern: '^s[0-9]+_p2$'125 - pattern: '^s[0-9]+_p1$'126 - pattern: '^s[0-9]+_p2$'127 - pattern: '^s[0-9]+_p1$'128 - pattern: '^s[0-9]+_p2$'129 - pattern: '^s[0-9]+_p1$'130 - pattern: '^s[0-9]+_p2$'131 - pattern: '^s[0-9]+_p1$'132 - pattern: '^s[0-9]+_p2$'[all …]
23 #clock-cells = <0>;28 #clock-cells = <0>;34 #size-cells = <0>;36 CPU0: cpu@0 {39 reg = <0x0>;52 reg = <0x1>;65 reg = <0x2>;78 reg = <0x3>;98 qcom,dload-mode = <&tcsr 0x6100>;105 reg = <0x0 0x40000000 0x0 0x0>;[all …]
26 #clock-cells = <0>;32 #size-cells = <0>;34 CPU0: cpu@0 {37 reg = <0x0>;48 reg = <0x1>;59 reg = <0x2>;70 reg = <0x3>;81 reg = <0x100>;92 reg = <0x101>;103 reg = <0x102>;[all …]
24 #clock-cells = <0>;30 #clock-cells = <0>;37 #size-cells = <0>;42 reg = <0x100>;56 reg = <0x101>;70 reg = <0x102>;84 reg = <0x103>;104 CPU_SLEEP_0: cpu-sleep-0 {107 arm,psci-suspend-param = <0x40000003>;161 reg = <0 0x80000000 0 0>;[all …]
25 #clock-cells = <0>;31 #clock-cells = <0>;39 #size-cells = <0>;41 CPU0: cpu@0 {44 reg = <0x0>;54 reg = <0x1>;64 reg = <0x2>;74 reg = <0x3>;84 reg = <0x100>;94 reg = <0x101>;[all …]
29 #clock-cells = <0>;35 #clock-cells = <0>;42 #size-cells = <0>;48 reg = <0x100>;66 reg = <0x101>;79 reg = <0x102>;92 reg = <0x103>;101 CPU4: cpu@0 {105 reg = <0x0>;123 reg = <0x1>;[all …]
26 reg = <0 0x80000000 0 0>;35 reg = <0x0 0x86000000 0x0 0x300000>;41 reg = <0x0 0x86300000 0x0 0x100000>;49 reg = <0x0 0x86400000 0x0 0x100000>;54 reg = <0x0 0x86500000 0x0 0x180000>;59 reg = <0x0 0x86680000 0x0 0x80000>;65 reg = <0x0 0x86700000 0x0 0xe0000>;72 reg = <0x0 0x867e0000 0x0 0x20000>;77 reg = <0x0 0x86800000 0x0 0x2b00000>;82 reg = <0x0 0x89300000 0x0 0x600000>;[all …]
28 #clock-cells = <0>;35 #clock-cells = <0>;43 #size-cells = <0>;45 CPU0: cpu@0 {48 reg = <0x0 0x0>;52 clocks = <&kryocc 0>;67 reg = <0x0 0x1>;71 clocks = <&kryocc 0>;81 reg = <0x0 0x100>;100 reg = <0x0 0x101>;[all …]
22 #clock-cells = <0>;28 #clock-cells = <0>;35 #size-cells = <0>;40 reg = <0x100>;54 reg = <0x101>;68 reg = <0x102>;82 reg = <0x103>;101 CPU_SLEEP_0: cpu-sleep-0 {104 arm,psci-suspend-param = <0x40000003>;158 reg = <0 0x80000000 0 0>;[all …]
30 reg = <0 0 0 0>;39 reg = <0x0 0x86000000 0x0 0x300000>;44 reg = <0x0 0x86300000 0x0 0x100000>;49 reg = <0x0 0x86400000 0x0 0x100000>;54 reg = <0x0 0x86500000 0x0 0x180000>;59 reg = <0x0 0x86680000 0x0 0x80000>;65 reg = <0x0 0x86700000 0x0 0xe0000>;72 reg = <0x0 0x867e0000 0x0 0x20000>;77 reg = <0x0 0x86800000 0x0 0x2b00000>;82 reg = <0x0 0x89300000 0x0 0x600000>;[all …]
22 #clock-cells = <0>;29 #clock-cells = <0>;37 #size-cells = <0>;39 CPU0: cpu@0 {42 reg = <0x0 0x0>;56 reg = <0x0 0x1>;66 reg = <0x0 0x100>;80 reg = <0x0 0x101>;112 CPU_SLEEP_0: cpu-sleep-0 {115 arm,psci-suspend-param = <0x00000004>;[all …]