Searched +full:0 +full:x008c0000 (Results 1 – 23 of 23) sorted by relevance
| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.yaml | 65 "spi@[0-9a-f]+$": 73 "i2c@[0-9a-f]+$": 78 "serial@[0-9a-f]+$": 102 "spi@[0-9a-f]+$": false 103 "serial@[0-9a-f]+$": false 129 reg = <0 0x008c0000 0 0x6000>; 139 reg = <0 0xa94000 0 0x4000>; 144 pinctrl-0 = <&qup_1_i2c_5_active>; 147 #size-cells = <0>; 152 reg = <0 0xa88000 0 0x7000>; [all …]
|
| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,geni-se.yaml | 64 "^.*@[0-9a-f]+$": 97 "spi@[0-9a-f]+$": 117 const: 0 125 "i2c@[0-9a-f]+$": 142 const: 0 154 "serial@[0-9a-f]+$": 189 reg = <0 0x008c0000 0 0x6000>; 199 reg = <0 0xa94000 0 0x4000>; 204 pinctrl-0 = <&qup_1_i2c_5_active>; 207 #size-cells = <0>; [all …]
|
| /kernel/linux/linux-5.10/drivers/media/platform/exynos4-is/ |
| D | fimc-is.h | 42 #define FIMC_IS_CPU_MEM_SIZE (0xa00000) 44 #define FIMC_IS_REGION_SIZE 0x5000 46 #define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000 47 #define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000 55 FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000) 56 #define FIMC_IS_EXTRA_FW_SIZE 0x180000 57 #define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000 112 FIMC_IS_AF_IDLE = 0, 121 FIMC_IS_AF_UNLOCKED = 0, 126 FIMC_IS_AE_UNLOCKED = 0, [all …]
|
| /kernel/linux/linux-6.6/drivers/media/platform/samsung/exynos4-is/ |
| D | fimc-is.h | 41 #define FIMC_IS_CPU_MEM_SIZE (0xa00000) 43 #define FIMC_IS_REGION_SIZE 0x5000 45 #define FIMC_IS_DEBUG_REGION_OFFSET 0x0084b000 46 #define FIMC_IS_SHARED_REGION_OFFSET 0x008c0000 54 FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000) 55 #define FIMC_IS_EXTRA_FW_SIZE 0x180000 56 #define FIMC_IS_EXTRA_SETFILE_SIZE 0x4b000 111 FIMC_IS_AF_IDLE = 0, 120 FIMC_IS_AF_UNLOCKED = 0, 125 FIMC_IS_AE_UNLOCKED = 0, [all …]
|
| /kernel/linux/linux-5.10/crypto/ |
| D | aes_generic.c | 67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6, 68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591, 69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56, 70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec, 71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa, 72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb, 73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45, 74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b, 75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c, 76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83, [all …]
|
| /kernel/linux/linux-6.6/crypto/ |
| D | aes_generic.c | 67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6, 68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591, 69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56, 70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec, 71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa, 72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb, 73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45, 74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b, 75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c, 76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83, [all …]
|
| /kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/ |
| D | sdm670.dtsi | 32 #size-cells = <0>; 34 CPU0: cpu@0 { 37 reg = <0x0 0x0>; 41 qcom,freq-domain = <&cpufreq_hw 0>; 64 reg = <0x0 0x100>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 86 reg = <0x0 0x200>; 90 qcom,freq-domain = <&cpufreq_hw 0>; 108 reg = <0x0 0x300>; 112 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | sa8775p.dtsi | 25 #clock-cells = <0>; 30 #clock-cells = <0>; 36 #size-cells = <0>; 38 CPU0: cpu@0 { 41 reg = <0x0 0x0>; 43 qcom,freq-domain = <&cpufreq_hw 0>; 61 reg = <0x0 0x100>; 63 qcom,freq-domain = <&cpufreq_hw 0>; 76 reg = <0x0 0x200>; 78 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | sm6350.dtsi | 31 #clock-cells = <0>; 39 #clock-cells = <0>; 45 #size-cells = <0>; 47 CPU0: cpu@0 { 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 80 reg = <0x0 0x100>; 81 clocks = <&cpufreq_hw 0>; 86 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | msm8996.dtsi | 28 #clock-cells = <0>; 35 #clock-cells = <0>; 43 #size-cells = <0>; 45 CPU0: cpu@0 { 48 reg = <0x0 0x0>; 52 clocks = <&kryocc 0>; 67 reg = <0x0 0x1>; 71 clocks = <&kryocc 0>; 81 reg = <0x0 0x100>; 100 reg = <0x0 0x101>; [all …]
|
| D | sc8180x.dtsi | 27 #clock-cells = <0>; 33 #clock-cells = <0>; 41 #size-cells = <0>; 43 CPU0: cpu@0 { 46 reg = <0x0 0x0>; 50 qcom,freq-domain = <&cpufreq_hw 0>; 57 clocks = <&cpufreq_hw 0>; 75 reg = <0x0 0x100>; 79 qcom,freq-domain = <&cpufreq_hw 0>; 86 clocks = <&cpufreq_hw 0>; [all …]
|
| D | sm8350.dtsi | 36 #clock-cells = <0>; 44 #clock-cells = <0>; 50 #size-cells = <0>; 52 CPU0: cpu@0 { 55 reg = <0x0 0x0>; 56 clocks = <&cpufreq_hw 0>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | sc7180.dtsi | 62 #clock-cells = <0>; 68 #clock-cells = <0>; 74 #size-cells = <0>; 76 CPU0: cpu@0 { 79 reg = <0x0 0x0>; 80 clocks = <&cpufreq_hw 0>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 108 reg = <0x0 0x100>; 109 clocks = <&cpufreq_hw 0>; 120 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | sm8150.dtsi | 30 #clock-cells = <0>; 37 #clock-cells = <0>; 45 #size-cells = <0>; 47 CPU0: cpu@0 { 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 79 reg = <0x0 0x100>; 80 clocks = <&cpufreq_hw 0>; [all …]
|
| D | sm8550.dtsi | 36 #clock-cells = <0>; 41 #clock-cells = <0>; 45 #clock-cells = <0>; 53 #clock-cells = <0>; 62 #clock-cells = <0>; 68 #size-cells = <0>; 70 CPU0: cpu@0 { 73 reg = <0 0>; 74 clocks = <&cpufreq_hw 0>; 79 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | sm8450.dtsi | 36 #clock-cells = <0>; 42 #clock-cells = <0>; 49 #size-cells = <0>; 51 CPU0: cpu@0 { 54 reg = <0x0 0x0>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 61 clocks = <&cpufreq_hw 0>; 78 reg = <0x0 0x100>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 85 clocks = <&cpufreq_hw 0>; [all …]
|
| D | sc8280xp.dtsi | 32 #clock-cells = <0>; 37 #clock-cells = <0>; 44 #size-cells = <0>; 46 CPU0: cpu@0 { 49 reg = <0x0 0x0>; 50 clocks = <&cpufreq_hw 0>; 56 qcom,freq-domain = <&cpufreq_hw 0>; 76 reg = <0x0 0x100>; 77 clocks = <&cpufreq_hw 0>; 83 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | sdm845.dtsi | 76 #clock-cells = <0>; 83 #clock-cells = <0>; 90 #size-cells = <0>; 92 CPU0: cpu@0 { 95 reg = <0x0 0x0>; 96 clocks = <&cpufreq_hw 0>; 100 qcom,freq-domain = <&cpufreq_hw 0>; 124 reg = <0x0 0x100>; 125 clocks = <&cpufreq_hw 0>; 129 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | sm8250.dtsi | 81 #clock-cells = <0>; 89 #clock-cells = <0>; 95 #size-cells = <0>; 97 CPU0: cpu@0 { 100 reg = <0x0 0x0>; 101 clocks = <&cpufreq_hw 0>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 116 cache-size = <0x20000>; 122 cache-size = <0x400000>; [all …]
|
| /kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/ |
| D | msm8996.dtsi | 22 #clock-cells = <0>; 29 #clock-cells = <0>; 37 #size-cells = <0>; 39 CPU0: cpu@0 { 42 reg = <0x0 0x0>; 56 reg = <0x0 0x1>; 66 reg = <0x0 0x100>; 80 reg = <0x0 0x101>; 112 CPU_SLEEP_0: cpu-sleep-0 { 115 arm,psci-suspend-param = <0x00000004>; [all …]
|
| D | sm8250.dtsi | 71 #clock-cells = <0>; 79 #clock-cells = <0>; 85 #size-cells = <0>; 87 CPU0: cpu@0 { 90 reg = <0x0 0x0>; 93 qcom,freq-domain = <&cpufreq_hw 0>; 107 reg = <0x0 0x100>; 110 qcom,freq-domain = <&cpufreq_hw 0>; 121 reg = <0x0 0x200>; 124 qcom,freq-domain = <&cpufreq_hw 0>; [all …]
|
| D | sc7180.dtsi | 60 #clock-cells = <0>; 66 #clock-cells = <0>; 76 reg = <0x0 0x80000000 0x0 0x600000>; 81 reg = <0x0 0x80600000 0x0 0x200000>; 86 reg = <0x0 0x80800000 0x0 0x20000>; 91 reg = <0x0 0x80820000 0x0 0x20000>; 97 reg = <0x0 0x808ff000 0x0 0x1000>; 102 reg = <0x0 0x80900000 0x0 0x200000>; 107 reg = <0x0 0x80b00000 0x0 0x3900000>; 113 reg = <0x0 0x84400000 0x0 0x200000>; [all …]
|
| D | sdm845.dtsi | 73 reg = <0 0x80000000 0 0>; 82 reg = <0 0x85700000 0 0x600000>; 87 reg = <0 0x85e00000 0 0x100000>; 92 reg = <0 0x85fc0000 0 0x20000>; 98 reg = <0x0 0x85fe0000 0 0x20000>; 103 reg = <0x0 0x86000000 0 0x200000>; 108 reg = <0 0x86200000 0 0x2d00000>; 114 reg = <0 0x88f00000 0 0x200000>; 122 reg = <0 0x8ab00000 0 0x1400000>; 127 reg = <0 0x8bf00000 0 0x500000>; [all …]
|