Searched +full:0 +full:x0118 (Results 1 – 25 of 449) sorted by relevance
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/ |
| D | imx7ulp-pinfunc.h | 15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
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| D | imx6ul-pinfunc.h | 13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx7ulp-pinfunc.h | 15 #define IMX7ULP_PAD_PTC0__PTC0 0x0000 0x0000 0x1 0x0
16 #define IMX7ULP_PAD_PTC0__TRACE_D15 0x0000 0x0000 0xa 0x0
17 #define IMX7ULP_PAD_PTC0__LPUART4_CTS_B 0x0000 0x0244 0x4 0x1
18 #define IMX7ULP_PAD_PTC0__LPI2C4_SCL 0x0000 0x0278 0x5 0x1
19 #define IMX7ULP_PAD_PTC0__TPM4_CLKIN 0x0000 0x0298 0x6 0x1
20 #define IMX7ULP_PAD_PTC0__FB_AD0 0x0000 0x0000 0x9 0x0
21 #define IMX7ULP_PAD_PTC1__PTC1 0x0004 0x0000 0x1 0x0
22 #define IMX7ULP_PAD_PTC1__TRACE_D14 0x0004 0x0000 0xa 0x0
23 #define IMX7ULP_PAD_PTC1__LPUART4_RTS_B 0x0004 0x0000 0x4 0x0
24 #define IMX7ULP_PAD_PTC1__LPI2C4_SDA 0x0004 0x027c 0x5 0x1
[all …]
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| D | imx6ul-pinfunc.h | 13 #define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0
14 #define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0
16 #define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0
17 #define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0
18 #define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0
19 #define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0
20 #define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0
21 #define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0
22 #define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0
23 #define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0
[all …]
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| D | imx6sll-pinfunc.h | 15 #define MX6SLL_PAD_WDOG_B__WDOG1_B 0x0014 0x02DC 0x0000 0x0 0x0
16 #define MX6SLL_PAD_WDOG_B__WDOG1_RESET_B_DEB 0x0014 0x02DC 0x0000 0x1 0x0
17 #define MX6SLL_PAD_WDOG_B__UART5_RI_B 0x0014 0x02DC 0x0000 0x2 0x0
18 #define MX6SLL_PAD_WDOG_B__GPIO3_IO18 0x0014 0x02DC 0x0000 0x5 0x0
19 #define MX6SLL_PAD_REF_CLK_24M__XTALOSC_REF_CLK_24M 0x0018 0x02E0 0x0000 0x0 0x0
20 #define MX6SLL_PAD_REF_CLK_24M__I2C3_SCL 0x0018 0x02E0 0x068C 0x1 0x0
21 #define MX6SLL_PAD_REF_CLK_24M__PWM3_OUT 0x0018 0x02E0 0x0000 0x2 0x0
22 #define MX6SLL_PAD_REF_CLK_24M__USB_OTG2_ID 0x0018 0x02E0 0x0560 0x3 0x0
23 #define MX6SLL_PAD_REF_CLK_24M__CCM_PMIC_READY 0x0018 0x02E0 0x05AC 0x4 0x0
24 #define MX6SLL_PAD_REF_CLK_24M__GPIO3_IO21 0x0018 0x02E0 0x0000 0x5 0x0
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8ulp-pinfunc.h | 13 #define MX8ULP_PAD_PTD0__PTD0 0x0000 0x0000 0x1 0x0
14 #define MX8ULP_PAD_PTD0__I2S6_RX_BCLK 0x0000 0x0B44 0x7 0x1
15 #define MX8ULP_PAD_PTD0__SDHC0_RESET_B 0x0000 0x0000 0x8 0x0
16 #define MX8ULP_PAD_PTD0__FLEXSPI2_B_DQS 0x0000 0x0974 0x9 0x1
17 #define MX8ULP_PAD_PTD0__CLKOUT2 0x0000 0x0000 0xa 0x0
18 #define MX8ULP_PAD_PTD0__EPDC0_SDCLK_B 0x0000 0x0000 0xb 0x0
19 #define MX8ULP_PAD_PTD0__LP_APD_DBG_MUX_0 0x0000 0x0000 0xc 0x0
20 #define MX8ULP_PAD_PTD0__CLKOUT1 0x0000 0x0000 0xd 0x0
21 #define MX8ULP_PAD_PTD0__DEBUG_MUX0_0 0x0000 0x0000 0xe 0x0
22 #define MX8ULP_PAD_PTD0__DEBUG_MUX1_0 0x0000 0x0000 0xf 0x0
[all …]
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| /kernel/linux/linux-5.10/arch/arm/mach-omap2/ |
| D | scrm44xx.h | 19 #define OMAP4_SCRM_BASE 0x4a30a000
25 #define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000
26 #define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000)
27 #define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100
28 #define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100)
29 #define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104
30 #define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104)
31 #define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110
32 #define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110)
33 #define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118
[all …]
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| D | cm2_7xx.h | 23 #define DRA7XX_CM_CORE_BASE 0x4a008000
29 #define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_CKGEN_INST 0x0104
31 #define DRA7XX_CM_CORE_COREAON_INST 0x0600
32 #define DRA7XX_CM_CORE_CORE_INST 0x0700
33 #define DRA7XX_CM_CORE_IVA_INST 0x0f00
34 #define DRA7XX_CM_CORE_CAM_INST 0x1000
35 #define DRA7XX_CM_CORE_DSS_INST 0x1100
36 #define DRA7XX_CM_CORE_GPU_INST 0x1200
37 #define DRA7XX_CM_CORE_L3INIT_INST 0x1300
[all …]
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| D | scrm54xx.h | 19 #define OMAP5_SCRM_BASE 0x4ae0a000
27 #define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000
28 #define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000)
29 #define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100
30 #define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100)
31 #define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104
32 #define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104)
33 #define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110
34 #define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110)
35 #define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118
[all …]
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| D | cm1_7xx.h | 23 #define DRA7XX_CM_CORE_AON_BASE 0x4a005000
29 #define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
30 #define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
31 #define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
32 #define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
33 #define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
34 #define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
35 #define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
36 #define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
37 #define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
[all …]
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| /kernel/linux/linux-6.6/arch/arm/mach-mvebu/ |
| D | kirkwood.h | 9 #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
10 #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
11 #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
13 #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
15 #define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
16 #define CPU_CONFIG_ERROR_PROP 0x00000004
18 #define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
19 #define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118)
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| /kernel/linux/linux-5.10/arch/arm/mach-mvebu/ |
| D | kirkwood.h | 12 #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
13 #define DDR_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x00000)
14 #define BRIDGE_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
16 #define DDR_OPERATION_BASE (DDR_PHYS_BASE + 0x1418)
18 #define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
19 #define CPU_CONFIG_ERROR_PROP 0x00000004
21 #define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
22 #define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x0118)
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| /kernel/linux/linux-5.10/arch/arm/include/debug/ |
| D | sirf.S | 8 #define SIRF_LLUART_TXFIFO_STATUS 0x0114
9 #define SIRF_LLUART_TXFIFO_DATA 0x0118
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | amlogic,meson-pinctrl-a1.yaml | 26 "^bank@[0-9a-z]+$":
57 reg = <0x0400 0x003c>,
58 <0x0480 0x0118>;
62 gpio-ranges = <&periphs_pinctrl 0 0 62>;
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| /kernel/linux/linux-6.6/drivers/clk/mediatek/ |
| D | clk-mt8186-topckgen.c | 22 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2, "mainpll_d2", "mainpll", 1, 2, 0),
23 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D2, "mainpll_d2_d2", "mainpll_d2", 1, 2, 0),
24 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D4, "mainpll_d2_d4", "mainpll_d2", 1, 4, 0),
25 FACTOR_FLAGS(CLK_TOP_MAINPLL_D2_D16, "mainpll_d2_d16", "mainpll_d2", 1, 16, 0),
26 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3, 0),
27 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D2, "mainpll_d3_d2", "mainpll_d3", 1, 2, 0),
28 FACTOR_FLAGS(CLK_TOP_MAINPLL_D3_D4, "mainpll_d3_d4", "mainpll_d3", 1, 4, 0),
29 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5, 0),
30 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll_d5", 1, 2, 0),
31 FACTOR_FLAGS(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll_d5", 1, 4, 0),
[all …]
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| /kernel/linux/linux-6.6/arch/s390/include/asm/ |
| D | lowcore.h | 25 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
26 __u32 ipl_parmblock_ptr; /* 0x0014 */
27 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
28 __u32 ext_params; /* 0x0080 */
31 __u16 ext_cpu_addr; /* 0x0084 */
32 __u16 ext_int_code; /* 0x0086 */
36 __u32 svc_int_code; /* 0x0088 */
39 __u16 pgm_ilc; /* 0x008c */
40 __u16 pgm_code; /* 0x008e */
44 __u32 data_exc_code; /* 0x0090 */
[all …]
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| /kernel/linux/linux-5.10/arch/s390/include/asm/ |
| D | lowcore.h | 21 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
22 __u32 ipl_parmblock_ptr; /* 0x0014 */
23 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
24 __u32 ext_params; /* 0x0080 */
25 __u16 ext_cpu_addr; /* 0x0084 */
26 __u16 ext_int_code; /* 0x0086 */
27 __u16 svc_ilc; /* 0x0088 */
28 __u16 svc_code; /* 0x008a */
29 __u16 pgm_ilc; /* 0x008c */
30 __u16 pgm_code; /* 0x008e */
[all …]
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| /kernel/linux/patches/linux-4.19/prebuilts/usr/include/scsi/fc/ |
| D | fc_ns.h | 11 FC_NS_GA_NXT = 0x0100,
12 FC_NS_GI_A = 0x0101,
13 FC_NS_GPN_ID = 0x0112,
14 FC_NS_GNN_ID = 0x0113,
15 FC_NS_GSPN_ID = 0x0118,
16 FC_NS_GID_PN = 0x0121,
17 FC_NS_GID_NN = 0x0131,
18 FC_NS_GID_FT = 0x0171,
19 FC_NS_GPN_FT = 0x0172,
20 FC_NS_GID_PT = 0x01a1,
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/rockchip/ |
| D | rockchip_vop_reg.h | 11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
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| /kernel/linux/linux-6.6/drivers/media/dvb-frontends/ |
| D | si2165_priv.h | 15 * possible values: 0x64,0x65,0x66,0x67
34 #define REG_CHIP_MODE 0x0000
35 #define REG_CHIP_REVCODE 0x0023
36 #define REV_CHIP_TYPE 0x0118
37 #define REG_CHIP_INIT 0x0050
38 #define REG_INIT_DONE 0x0054
39 #define REG_START_INIT 0x0096
40 #define REG_PLL_DIVL 0x00a0
41 #define REG_RST_ALL 0x00c0
42 #define REG_LOCK_TIMEOUT 0x00c4
[all …]
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| /kernel/linux/linux-5.10/drivers/media/dvb-frontends/ |
| D | si2165_priv.h | 15 * possible values: 0x64,0x65,0x66,0x67
34 #define REG_CHIP_MODE 0x0000
35 #define REG_CHIP_REVCODE 0x0023
36 #define REV_CHIP_TYPE 0x0118
37 #define REG_CHIP_INIT 0x0050
38 #define REG_INIT_DONE 0x0054
39 #define REG_START_INIT 0x0096
40 #define REG_PLL_DIVL 0x00a0
41 #define REG_RST_ALL 0x00c0
42 #define REG_LOCK_TIMEOUT 0x00c4
[all …]
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| /kernel/linux/linux-6.6/drivers/media/cec/platform/s5p/ |
| D | regs-cec.h | 16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
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| /kernel/linux/linux-5.10/drivers/media/cec/platform/s5p/ |
| D | regs-cec.h | 16 #define S5P_CEC_STATUS_0 (0x0000)
17 #define S5P_CEC_STATUS_1 (0x0004)
18 #define S5P_CEC_STATUS_2 (0x0008)
19 #define S5P_CEC_STATUS_3 (0x000C)
20 #define S5P_CEC_IRQ_MASK (0x0010)
21 #define S5P_CEC_IRQ_CLEAR (0x0014)
22 #define S5P_CEC_LOGIC_ADDR (0x0020)
23 #define S5P_CEC_DIVISOR_0 (0x0030)
24 #define S5P_CEC_DIVISOR_1 (0x0034)
25 #define S5P_CEC_DIVISOR_2 (0x0038)
[all …]
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| /kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/ |
| D | sdio.h | 12 #define MCR_WCIR 0x0000
13 #define MCR_WHLPCR 0x0004
18 #define WHLPCR_INT_EN_SET BIT(0)
20 #define MCR_WSDIOCSR 0x0008
21 #define MCR_WHCR 0x000C
27 #define MCR_WHISR 0x0010
28 #define MCR_WHIER 0x0014
34 #define WHIER_TX_DONE_INT_EN BIT(0)
41 #define MCR_WASR 0x0020
42 #define MCR_WSICR 0x0024
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/rockchip/ |
| D | rockchip_vop_reg.h | 11 #define RK3288_REG_CFG_DONE 0x0000
12 #define RK3288_VERSION_INFO 0x0004
13 #define RK3288_SYS_CTRL 0x0008
14 #define RK3288_SYS_CTRL1 0x000c
15 #define RK3288_DSP_CTRL0 0x0010
16 #define RK3288_DSP_CTRL1 0x0014
17 #define RK3288_DSP_BG 0x0018
18 #define RK3288_MCU_CTRL 0x001c
19 #define RK3288_INTR_CTRL0 0x0020
20 #define RK3288_INTR_CTRL1 0x0024
[all …]
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