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/kernel/linux/linux-6.6/arch/arm/mach-pxa/
Dpxa-regs.h14 #define UNCACHED_PHYS_0 0xfe000000
15 #define UNCACHED_PHYS_0_SIZE 0x00100000
20 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
21 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
22 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
23 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
24 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
25 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
26 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
31 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/kernel/linux/linux-5.10/drivers/video/fbdev/riva/
Driva_tbl.h55 {0x00000050, 0x00000000},
56 {0x00000080, 0xFFFF00FF},
57 {0x00000080, 0xFFFFFFFF}
61 {0x00000080, 0x00000008},
62 {0x00000084, 0x00000003},
63 {0x00000050, 0x00000000},
64 {0x00000040, 0xFFFFFFFF}
68 {0x00000000, 0x80000000},
69 {0x00000800, 0x80000001},
70 {0x00001000, 0x80000002},
[all …]
/kernel/linux/linux-6.6/drivers/video/fbdev/riva/
Driva_tbl.h55 {0x00000050, 0x00000000},
56 {0x00000080, 0xFFFF00FF},
57 {0x00000080, 0xFFFFFFFF}
61 {0x00000080, 0x00000008},
62 {0x00000084, 0x00000003},
63 {0x00000050, 0x00000000},
64 {0x00000040, 0xFFFFFFFF}
68 {0x00000000, 0x80000000},
69 {0x00000800, 0x80000001},
70 {0x00001000, 0x80000002},
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/
Dezx-pcap.h40 #define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT 0x00000000
43 #define PCAP_REGISTER_VALUE_MASK 0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
47 #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
51 #define PCAP_REG_ISR 0x0 /* Interrupt Status */
52 #define PCAP_REG_MSR 0x1 /* Interrupt Mask */
53 #define PCAP_REG_PSTAT 0x2 /* Processor Status */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/
Dezx-pcap.h40 #define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT 0x00000000
43 #define PCAP_REGISTER_VALUE_MASK 0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
47 #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
51 #define PCAP_REG_ISR 0x0 /* Interrupt Status */
52 #define PCAP_REG_MSR 0x1 /* Interrupt Mask */
53 #define PCAP_REG_PSTAT 0x2 /* Processor Status */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
[all …]
/kernel/linux/linux-5.10/Documentation/gpu/
Dkms-properties.csv7 ,,“left margin”,RANGE,"Min=0, Max=100",Connector,TBD
8 ,,“right margin”,RANGE,"Min=0, Max=100",Connector,TBD
9 ,,“top margin”,RANGE,"Min=0, Max=100",Connector,TBD
10 ,,“bottom margin”,RANGE,"Min=0, Max=100",Connector,TBD
11 ,,“brightness”,RANGE,"Min=0, Max=100",Connector,TBD
12 ,,“contrast”,RANGE,"Min=0, Max=100",Connector,TBD
13 ,,“flicker reduction”,RANGE,"Min=0, Max=100",Connector,TBD
14 ,,“overscan”,RANGE,"Min=0, Max=100",Connector,TBD
15 ,,“saturation”,RANGE,"Min=0, Max=100",Connector,TBD
16 ,,“hue”,RANGE,"Min=0, Max=100",Connector,TBD
[all …]
/kernel/linux/linux-6.6/Documentation/gpu/
Dkms-properties.csv7 ,,“left margin”,RANGE,"Min=0, Max=100",Connector,TBD
8 ,,“right margin”,RANGE,"Min=0, Max=100",Connector,TBD
9 ,,“top margin”,RANGE,"Min=0, Max=100",Connector,TBD
10 ,,“bottom margin”,RANGE,"Min=0, Max=100",Connector,TBD
11 ,,“brightness”,RANGE,"Min=0, Max=100",Connector,TBD
12 ,,“contrast”,RANGE,"Min=0, Max=100",Connector,TBD
13 ,,“flicker reduction”,RANGE,"Min=0, Max=100",Connector,TBD
14 ,,“overscan”,RANGE,"Min=0, Max=100",Connector,TBD
15 ,,“saturation”,RANGE,"Min=0, Max=100",Connector,TBD
16 ,,“hue”,RANGE,"Min=0, Max=100",Connector,TBD
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw89/
Drtw8852a_rfk_table.c8 RTW89_DECL_RFK_WM(0x12a8, 0x00000001, 0x00000001),
9 RTW89_DECL_RFK_WM(0x12a8, 0x0000000e, 0x00000002),
10 RTW89_DECL_RFK_WM(0x32a8, 0x00000001, 0x00000001),
11 RTW89_DECL_RFK_WM(0x32a8, 0x0000000e, 0x00000002),
12 RTW89_DECL_RFK_WM(0x12bc, 0x000000f0, 0x00000005),
13 RTW89_DECL_RFK_WM(0x12bc, 0x00000f00, 0x00000005),
14 RTW89_DECL_RFK_WM(0x12bc, 0x000f0000, 0x00000005),
15 RTW89_DECL_RFK_WM(0x12bc, 0x0000f000, 0x00000005),
16 RTW89_DECL_RFK_WM(0x120c, 0x000000ff, 0x00000033),
17 RTW89_DECL_RFK_WM(0x12c0, 0x0ff00000, 0x00000033),
[all …]
/kernel/linux/linux-5.10/drivers/scsi/
Dgvp11.c43 static int gvp11_xfer_mask = 0;
59 static int scsi_alloc_out_of_range = 0; in dma_setup()
63 wh->dma_bounce_len = (cmd->SCp.this_residual + 511) & ~0x1ff; in dma_setup()
78 wh->dma_bounce_len = 0; in dma_setup()
102 wh->dma_bounce_len = 0; in dma_setup()
135 bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; in dma_setup()
143 return 0; in dma_setup()
170 wh->dma_bounce_len = 0; in dma_stop()
215 if (q & 0x08) /* bit 3 should always be clear */ in check_wd33c93()
226 if (*scmd_3393 != q) /* and so should the image at 0x1f */ in check_wd33c93()
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/
Dhardware.h19 #define UNCACHED_PHYS_0 0xfe000000
20 #define UNCACHED_PHYS_0_SIZE 0x00100000
25 * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
26 * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
27 * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
28 * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
29 * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
30 * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
31 * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
36 #define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
[all …]
/kernel/linux/linux-6.6/drivers/scsi/
Dgvp11.c33 #define TO_DMA_MASK(m) (~((unsigned long long)m & 0xffffffff))
51 static int gvp11_xfer_mask = 0;
64 static int scsi_alloc_out_of_range = 0; in dma_setup()
83 wh->dma_bounce_len = (scsi_pointer->this_residual + 511) & ~0x1ff; in dma_setup()
98 wh->dma_bounce_len = 0; in dma_setup()
144 wh->dma_bounce_len = 0; in dma_setup()
175 bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0; in dma_setup()
183 return 0; in dma_setup()
216 wh->dma_bounce_len = 0; in dma_stop()
262 if (q & 0x08) /* bit 3 should always be clear */ in check_wd33c93()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/watchdog/
Dsnps,dw-wdt.yaml52 default: [0x0001000 0x0002000 0x0004000 0x0008000
53 0x0010000 0x0020000 0x0040000 0x0080000
54 0x0100000 0x0200000 0x0400000 0x0800000
55 0x1000000 0x2000000 0x4000000 0x8000000]
70 reg = <0xffd02000 0x1000>;
71 interrupts = <0 171 4>;
79 reg = <0xffd02000 0x1000>;
80 interrupts = <0 171 4>;
83 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
84 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/
Dsnps,dw-wdt.yaml69 default: [0x0001000 0x0002000 0x0004000 0x0008000
70 0x0010000 0x0020000 0x0040000 0x0080000
71 0x0100000 0x0200000 0x0400000 0x0800000
72 0x1000000 0x2000000 0x4000000 0x8000000]
87 reg = <0xffd02000 0x1000>;
88 interrupts = <0 171 4>;
96 reg = <0xffd02000 0x1000>;
97 interrupts = <0 171 4>;
100 snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
101 0x000007FF 0x0000FFFF 0x0001FFFF
[all …]
/kernel/linux/linux-5.10/arch/mips/alchemy/common/
Dvss.c14 #define VSS_GATE 0x00 /* gate wait timers */
15 #define VSS_CLKRST 0x04 /* clock/block control */
16 #define VSS_FTR 0x08 /* footers */
18 #define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
[all …]
/kernel/linux/linux-6.6/arch/mips/alchemy/common/
Dvss.c14 #define VSS_GATE 0x00 /* gate wait timers */
15 #define VSS_CLKRST 0x04 /* clock/block control */
16 #define VSS_FTR 0x08 /* footers */
18 #define VSS_ADDR(blk) (KSEG1ADDR(AU1300_VSS_PHYS_ADDR) + (blk * 0x0c))
30 __raw_writel(0x01fffffe, base + VSS_GATE); /* maximum setup time */ in __enable_block()
34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
[all …]
/kernel/linux/linux-6.6/arch/mips/cobalt/
Dsetup.c51 .start = 0x00,
52 .end = 0x1f,
57 .start = 0x60,
58 .end = 0x6f,
63 .start = 0x80,
64 .end = 0x8f,
69 .start = 0xc0,
70 .end = 0xdf,
87 ioport_resource.end = 0x01ffffff; in plat_mem_setup()
90 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) in plat_mem_setup()
[all …]
/kernel/linux/linux-5.10/arch/mips/cobalt/
Dsetup.c51 .start = 0x00,
52 .end = 0x1f,
57 .start = 0x60,
58 .end = 0x6f,
63 .start = 0x80,
64 .end = 0x8f,
69 .start = 0xc0,
70 .end = 0xdf,
87 ioport_resource.end = 0x01ffffff; in plat_mem_setup()
90 for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++) in plat_mem_setup()
[all …]
/kernel/linux/linux-5.10/arch/m68k/mm/
Dcache.c24 "1: plpar (%0)\n" in virt_to_phys_slow()
29 "3: sub.l %0,%0\n" in virt_to_phys_slow()
37 : "0" (vaddr)); in virt_to_phys_slow()
44 "movec %%mmusr, %0\n\t" in virt_to_phys_slow()
55 asm volatile ("ptestr %3,%2@,#7,%0\n\t" in virt_to_phys_slow()
60 return 0; in virt_to_phys_slow()
64 return (*descaddr & 0xfe000000) | (vaddr & 0x01ffffff); in virt_to_phys_slow()
66 return (*descaddr & 0xfffc0000) | (vaddr & 0x0003ffff); in virt_to_phys_slow()
71 return 0; in virt_to_phys_slow()
83 flush_cf_icache(0, end); in flush_icache_user_range()
[all …]
/kernel/linux/linux-6.6/arch/sh/boards/mach-se/7343/
Dsetup.c32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
/kernel/linux/linux-5.10/arch/sh/boards/mach-se/7343/
Dsetup.c32 .offset = 0x00000000,
54 [0] = {
55 .start = 0x00000000,
56 .end = 0x01ffffff,
73 [0] = {
75 .mapbase = 0x16000000,
82 .mapbase = 0x17000000,
104 [0] = {
105 .start = 0x11800000,
106 .end = 0x11800001,
[all …]
/kernel/linux/linux-5.10/drivers/media/platform/ti-vpe/
Dsc.h13 #define CFG_SC0 0x0
14 #define CFG_INTERLACE_O (1 << 0)
30 #define CFG_SC1 0x4
31 #define CFG_ROW_ACC_INC_MASK 0x07ffffff
32 #define CFG_ROW_ACC_INC_SHIFT 0
34 #define CFG_SC2 0x08
35 #define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff
36 #define CFG_ROW_ACC_OFFSET_SHIFT 0
38 #define CFG_SC3 0x0c
39 #define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff
[all …]
/kernel/linux/linux-6.6/drivers/media/platform/ti/vpe/
Dsc.h13 #define CFG_SC0 0x0
14 #define CFG_INTERLACE_O (1 << 0)
30 #define CFG_SC1 0x4
31 #define CFG_ROW_ACC_INC_MASK 0x07ffffff
32 #define CFG_ROW_ACC_INC_SHIFT 0
34 #define CFG_SC2 0x08
35 #define CFG_ROW_ACC_OFFSET_MASK 0x0fffffff
36 #define CFG_ROW_ACC_OFFSET_SHIFT 0
38 #define CFG_SC3 0x0c
39 #define CFG_ROW_ACC_OFFSET_B_MASK 0x0fffffff
[all …]
/kernel/linux/linux-5.10/drivers/scsi/arm/
Doak.c51 while (((status = readw(base + STAT)) & 0x100)==0); in oakscsi_pwrite()
53 return 0; in oakscsi_pwrite()
62 while(len > 0) in oakscsi_pread()
67 timeout = 0x01FFFFFF; in oakscsi_pread()
69 while (((status = readw(base + STAT)) & 0x100)==0) in oakscsi_pread()
72 if(status & 0x200 || !timeout) in oakscsi_pread()
95 return 0; in oakscsi_pread()
185 { 0xffff, 0xffff }
/kernel/linux/linux-6.6/drivers/scsi/arm/
Doak.c51 while (((status = readw(base + STAT)) & 0x100)==0); in oakscsi_pwrite()
53 return 0; in oakscsi_pwrite()
62 while(len > 0) in oakscsi_pread()
67 timeout = 0x01FFFFFF; in oakscsi_pread()
69 while (((status = readw(base + STAT)) & 0x100)==0) in oakscsi_pread()
72 if(status & 0x200 || !timeout) in oakscsi_pread()
95 return 0; in oakscsi_pread()
185 { 0xffff, 0xffff }
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dnislands_smc.h125 #define NISLANDS_SMC_STROBE_RATIO 0x0F
126 #define NISLANDS_SMC_STROBE_ENABLE 0x10
128 #define NISLANDS_SMC_MC_EDC_RD_FLAG 0x01
129 #define NISLANDS_SMC_MC_EDC_WR_FLAG 0x02
130 #define NISLANDS_SMC_MC_RTT_ENABLE 0x04
131 #define NISLANDS_SMC_MC_STUTTER_EN 0x08
146 #define NISLANDS_SMC_VOLTAGEMASK_VDDC 0
180 #define NI_SMC_SOFT_REGISTERS_START 0x108
182 #define NI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0
183 #define NI_SMC_SOFT_REGISTER_delay_bbias 0xC
[all …]

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