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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/watchdog/
Dqcom-wdt.yaml14 pattern: "^(watchdog|timer)@[0-9a-f]+$"
72 facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
122 reg = <0x17c10000 0x1000>;
124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
138 reg = <0x0200a000 0x100>;
142 cpu-offset = <0x80000>;
/kernel/linux/linux-5.10/arch/arm64/boot/dts/qcom/
Dsm8150.dtsi28 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #size-cells = <0>;
45 CPU0: cpu@0 {
48 reg = <0x0 0x0>;
51 qcom,freq-domain = <&cpufreq_hw 0>;
65 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x200>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8250.dtsi71 #clock-cells = <0>;
79 #clock-cells = <0>;
85 #size-cells = <0>;
87 CPU0: cpu@0 {
90 reg = <0x0 0x0>;
93 qcom,freq-domain = <&cpufreq_hw 0>;
107 reg = <0x0 0x100>;
110 qcom,freq-domain = <&cpufreq_hw 0>;
121 reg = <0x0 0x200>;
124 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi60 #clock-cells = <0>;
66 #clock-cells = <0>;
76 reg = <0x0 0x80000000 0x0 0x600000>;
81 reg = <0x0 0x80600000 0x0 0x200000>;
86 reg = <0x0 0x80800000 0x0 0x20000>;
91 reg = <0x0 0x80820000 0x0 0x20000>;
97 reg = <0x0 0x808ff000 0x0 0x1000>;
102 reg = <0x0 0x80900000 0x0 0x200000>;
107 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 reg = <0x0 0x84400000 0x0 0x200000>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/qcom/
Dsa8775p.dtsi25 #clock-cells = <0>;
30 #clock-cells = <0>;
36 #size-cells = <0>;
38 CPU0: cpu@0 {
41 reg = <0x0 0x0>;
43 qcom,freq-domain = <&cpufreq_hw 0>;
61 reg = <0x0 0x100>;
63 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x200>;
78 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm6350.dtsi31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
80 reg = <0x0 0x100>;
81 clocks = <&cpufreq_hw 0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7180.dtsi62 #clock-cells = <0>;
68 #clock-cells = <0>;
74 #size-cells = <0>;
76 CPU0: cpu@0 {
79 reg = <0x0 0x0>;
80 clocks = <&cpufreq_hw 0>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
108 reg = <0x0 0x100>;
109 clocks = <&cpufreq_hw 0>;
120 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsm8150.dtsi30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
47 CPU0: cpu@0 {
50 reg = <0x0 0x0>;
51 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
58 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
79 reg = <0x0 0x100>;
80 clocks = <&cpufreq_hw 0>;
[all …]
Dsc8280xp.dtsi32 #clock-cells = <0>;
37 #clock-cells = <0>;
44 #size-cells = <0>;
46 CPU0: cpu@0 {
49 reg = <0x0 0x0>;
50 clocks = <&cpufreq_hw 0>;
56 qcom,freq-domain = <&cpufreq_hw 0>;
76 reg = <0x0 0x100>;
77 clocks = <&cpufreq_hw 0>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
[all …]
Dsc7280.dtsi77 #clock-cells = <0>;
83 #clock-cells = <0>;
94 reg = <0x0 0x004cd000 0x0 0x1000>;
98 reg = <0x0 0x80000000 0x0 0x600000>;
103 reg = <0x0 0x80600000 0x0 0x200000>;
108 reg = <0x0 0x80800000 0x0 0x60000>;
113 reg = <0x0 0x80860000 0x0 0x20000>;
119 reg = <0x0 0x80884000 0x0 0x10000>;
124 reg = <0x0 0x808ff000 0x0 0x1000>;
129 reg = <0x0 0x80900000 0x0 0x200000>;
[all …]
Dsm8250.dtsi81 #clock-cells = <0>;
89 #clock-cells = <0>;
95 #size-cells = <0>;
97 CPU0: cpu@0 {
100 reg = <0x0 0x0>;
101 clocks = <&cpufreq_hw 0>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
116 cache-size = <0x20000>;
122 cache-size = <0x400000>;
[all …]