Searched +full:0 +full:x17d41000 (Results 1 – 5 of 5) sorted by relevance
54 #define RPMH_CXO_CLK 058 reg = <0x17d41000 0x1400>;
67 #define RPMH_CXO_CLK 071 reg = <0x17d41000 0x1400>;
32 #size-cells = <0>;34 CPU0: cpu@0 {37 reg = <0x0 0x0>;41 qcom,freq-domain = <&cpufreq_hw 0>;64 reg = <0x0 0x100>;68 qcom,freq-domain = <&cpufreq_hw 0>;86 reg = <0x0 0x200>;90 qcom,freq-domain = <&cpufreq_hw 0>;108 reg = <0x0 0x300>;112 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
76 #clock-cells = <0>;83 #clock-cells = <0>;90 #size-cells = <0>;92 CPU0: cpu@0 {95 reg = <0x0 0x0>;96 clocks = <&cpufreq_hw 0>;100 qcom,freq-domain = <&cpufreq_hw 0>;124 reg = <0x0 0x100>;125 clocks = <&cpufreq_hw 0>;129 qcom,freq-domain = <&cpufreq_hw 0>;[all …]
73 reg = <0 0x80000000 0 0>;82 reg = <0 0x85700000 0 0x600000>;87 reg = <0 0x85e00000 0 0x100000>;92 reg = <0 0x85fc0000 0 0x20000>;98 reg = <0x0 0x85fe0000 0 0x20000>;103 reg = <0x0 0x86000000 0 0x200000>;108 reg = <0 0x86200000 0 0x2d00000>;114 reg = <0 0x88f00000 0 0x200000>;122 reg = <0 0x8ab00000 0 0x1400000>;127 reg = <0 0x8bf00000 0 0x500000>;[all …]