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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/nvmem/
Dmediatek,efuse.yaml22 pattern: "^efuse@[0-9a-f]+$"
55 reg = <0x11c10000 0x1000>;
60 reg = <0x184 0x1>;
61 bits = <0 5>;
64 reg = <0x184 0x2>;
68 reg = <0x185 0x1>;
72 reg = <0x186 0x1>;
73 bits = <0 5>;
76 reg = <0x186 0x2>;
80 reg = <0x187 0x1>;
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_d.h27 #define ixTHM_TCON_CSR_CONFIG 0xd82014a4
28 #define ixTHM_TCON_CSR_DATA 0xd82014a8
29 #define ixTHM_TCON_HTC 0xd8200c64
30 #define ixTHM_TCON_CUR_TMP 0xd8200ca4
31 #define ixTHM_TCON_THERM_TRIP 0xd8200ce4
32 #define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00
33 #define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04
34 #define ixTHM_THERMAL_INT_ENA 0xd8200d10
35 #define ixTHM_THERMAL_INT_CTRL 0xd8200d14
36 #define ixTHM_THERMAL_INT_STATUS 0xd8200d18
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/smu/
Dsmu_8_0_d.h27 #define ixTHM_TCON_CSR_CONFIG 0xd82014a4
28 #define ixTHM_TCON_CSR_DATA 0xd82014a8
29 #define ixTHM_TCON_HTC 0xd8200c64
30 #define ixTHM_TCON_CUR_TMP 0xd8200ca4
31 #define ixTHM_TCON_THERM_TRIP 0xd8200ce4
32 #define ixTHM_GPIO_PROCHOT_CTRL 0xd8200d00
33 #define ixTHM_GPIO_THERMTRIP_CTRL 0xd8200d04
34 #define ixTHM_THERMAL_INT_ENA 0xd8200d10
35 #define ixTHM_THERMAL_INT_CTRL 0xd8200d14
36 #define ixTHM_THERMAL_INT_STATUS 0xd8200d18
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/marvell/mwifiex/
Dcfp.c28 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 };
30 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
31 0xb0, 0x48, 0x60, 0x6c, 0 };
33 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96,
34 0x0c, 0x12, 0x18, 0x24,
35 0x30, 0x48, 0x60, 0x6c, 0 };
37 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
38 0xb0, 0x48, 0x60, 0x6c, 0 };
39 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24,
40 0xb0, 0x48, 0x60, 0x6c, 0 };
[all …]
D11ac.c18 {0x124, 0x15F, 0x186}, /* NSS = 1 */
19 {0x249, 0x2BE, 0x30C}, /* NSS = 2 */
20 {0x36D, 0x41D, 0x492}, /* NSS = 3 */
21 {0x492, 0x57C, 0x618}, /* NSS = 4 */
22 {0x5B6, 0x6DB, 0x79E}, /* NSS = 5 */
23 {0x6DB, 0x83A, 0x0}, /* NSS = 6 */
24 {0x7FF, 0x999, 0xAAA}, /* NSS = 7 */
25 {0x924, 0xAF8, 0xC30} /* NSS = 8 */
29 {0x249, 0x2BE, 0x30C}, /* NSS = 1 */
30 {0x492, 0x57C, 0x618}, /* NSS = 2 */
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/marvell/mwifiex/
Dcfp.c40 static u8 adhoc_rates_b[B_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96, 0 };
42 static u8 adhoc_rates_g[G_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
43 0xb0, 0x48, 0x60, 0x6c, 0 };
45 static u8 adhoc_rates_bg[BG_SUPPORTED_RATES] = { 0x82, 0x84, 0x8b, 0x96,
46 0x0c, 0x12, 0x18, 0x24,
47 0x30, 0x48, 0x60, 0x6c, 0 };
49 static u8 adhoc_rates_a[A_SUPPORTED_RATES] = { 0x8c, 0x12, 0x98, 0x24,
50 0xb0, 0x48, 0x60, 0x6c, 0 };
51 static u8 supported_rates_a[A_SUPPORTED_RATES] = { 0x0c, 0x12, 0x18, 0x24,
52 0xb0, 0x48, 0x60, 0x6c, 0 };
[all …]
D11ac.c30 {0x124, 0x15F, 0x186}, /* NSS = 1 */
31 {0x249, 0x2BE, 0x30C}, /* NSS = 2 */
32 {0x36D, 0x41D, 0x492}, /* NSS = 3 */
33 {0x492, 0x57C, 0x618}, /* NSS = 4 */
34 {0x5B6, 0x6DB, 0x79E}, /* NSS = 5 */
35 {0x6DB, 0x83A, 0x0}, /* NSS = 6 */
36 {0x7FF, 0x999, 0xAAA}, /* NSS = 7 */
37 {0x924, 0xAF8, 0xC30} /* NSS = 8 */
41 {0x249, 0x2BE, 0x30C}, /* NSS = 1 */
42 {0x492, 0x57C, 0x618}, /* NSS = 2 */
[all …]
/kernel/linux/linux-5.10/drivers/media/pci/tw686x/
Dtw686x-regs.h6 a0 + 8, a0 + 0xa, a0 + 0xc, a0 + 0xe})
7 #define REG8_8(a0) ((const u16[8]) { a0, a0 + 8, a0 + 0x10, a0 + 0x18, \
8 a0 + 0x20, a0 + 0x28, a0 + 0x30, \
9 a0 + 0x38})
10 #define INT_STATUS 0x00
11 #define PB_STATUS 0x01
12 #define DMA_CMD 0x02
13 #define VIDEO_FIFO_STATUS 0x03
14 #define VIDEO_CHANNEL_ID 0x04
15 #define VIDEO_PARSER_STATUS 0x05
[all …]
/kernel/linux/linux-6.6/drivers/media/pci/tw686x/
Dtw686x-regs.h6 a0 + 8, a0 + 0xa, a0 + 0xc, a0 + 0xe})
7 #define REG8_8(a0) ((const u16[8]) { a0, a0 + 8, a0 + 0x10, a0 + 0x18, \
8 a0 + 0x20, a0 + 0x28, a0 + 0x30, \
9 a0 + 0x38})
10 #define INT_STATUS 0x00
11 #define PB_STATUS 0x01
12 #define DMA_CMD 0x02
13 #define VIDEO_FIFO_STATUS 0x03
14 #define VIDEO_CHANNEL_ID 0x04
15 #define VIDEO_PARSER_STATUS 0x05
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/
Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/legacy-dpm/
Dppsmc.h28 #define PPSMC_SWSTATE_FLAG_DC 0x01
29 #define PPSMC_SWSTATE_FLAG_UVD 0x02
30 #define PPSMC_SWSTATE_FLAG_VCE 0x04
31 #define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
33 #define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
34 #define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
35 #define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
37 #define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
38 #define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
39 #define PPSMC_SYSTEMFLAG_GDDR5 0x04
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtw88/
Drtw8821c.h13 u8 mac_addr[ETH_ALEN]; /* 0xd0 */
21 u8 ltr_cap; /* 0xe3 */
26 u8 res0:2; /* 0xf4 */
50 u8 res0[0x0e];
55 u8 channel_plan; /* 0xb8 */
59 u8 pa_type; /* 0xbc */
60 u8 lna_type_2g[2]; /* 0xbd */
70 u8 rf_antenna_option; /* 0xc9 */
82 /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */ in _rtw_write32s_mask()
84 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); in _rtw_write32s_mask()
[all …]
/kernel/linux/linux-6.6/tools/perf/pmu-events/arch/arm64/fujitsu/a64fx/
Dother.json4 "EventCode": "0x139",
10 "EventCode": "0x180",
16 "EventCode": "0x181",
22 "EventCode": "0x182",
28 "EventCode": "0x183",
34 "EventCode": "0x184",
40 "EventCode": "0x185",
46 "EventCode": "0x186",
52 "EventCode": "0x187",
58 "EventCode": "0x188",
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
Dintel_rc6.c20 * low-voltage mode when idle, using down to 0V while at this stage. This
75 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); in gen11_rc6_enable()
77 set(uncore, GEN6_RC_SLEEP, 0); in gen11_rc6_enable()
114 for (i = 0; i < I915_MAX_VCS; i++) in gen11_rc6_enable()
148 set(uncore, GUC_MAX_IDLE_COUNT, 0xA); in gen9_rc6_enable()
150 set(uncore, GEN6_RC_SLEEP, 0); in gen9_rc6_enable()
206 set(uncore, GEN6_RC_SLEEP, 0); in gen8_rc6_enable()
234 set(uncore, GEN6_RC_SLEEP, 0); in gen6_rc6_enable()
251 rc6vids = 0; in gen6_rc6_enable()
257 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { in gen6_rc6_enable()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtw88/
Drtw8821c.h13 u8 res4[4]; /* 0xd0 */
15 u8 res5[0x1e];
17 u8 serial[0x0b]; /* 0xf5 */
18 u8 vid; /* 0x100 */
22 u8 mac_addr[ETH_ALEN]; /* 0x107 */
24 u8 vendor_name[0x07];
26 u8 device_name[0x14];
27 u8 res11[0xcf];
28 u8 package_type; /* 0x1fb */
29 u8 res12[0x4];
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/mediatek/mt76/mt7615/
Deeprom.c20 val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf); in mt7615_efuse_read()
24 if (!mt76_poll(dev, base + MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000)) in mt7615_efuse_read()
32 memset(data, 0x0, 16); in mt7615_efuse_read()
33 return 0; in mt7615_efuse_read()
36 for (i = 0; i < 4; i++) { in mt7615_efuse_read()
41 return 0; in mt7615_efuse_read()
52 return 0; in mt7615_efuse_init()
60 for (i = 0; i + 16 <= len; i += 16) { in mt7615_efuse_init()
68 return 0; in mt7615_efuse_init()
76 if (ret < 0) in mt7615_eeprom_load()
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7615/
Deeprom.c20 val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf); in mt7615_efuse_read()
24 if (!mt76_poll(dev, base + MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000)) in mt7615_efuse_read()
32 memset(data, 0x0, 16); in mt7615_efuse_read()
33 return 0; in mt7615_efuse_read()
36 for (i = 0; i < 4; i++) { in mt7615_efuse_read()
41 return 0; in mt7615_efuse_read()
55 return 0; in mt7615_efuse_init()
63 for (i = 0; i + 16 <= len; i += 16) { in mt7615_efuse_init()
71 return 0; in mt7615_efuse_init()
81 if (ret < 0) in mt7615_eeprom_load()
[all …]
/kernel/linux/linux-6.6/drivers/leds/rgb/
Dleds-mt6370-rgb.c27 MT6370_LED_ISNK1 = 0,
35 MT6370_LED_PWM_MODE = 0,
42 F_RGB_EN = 0,
64 R_LED123_CURR = 0,
72 P_LED_TR1 = 0,
81 #define MT6370_REG_DEV_INFO 0x100
82 #define MT6370_REG_RGB1_DIM 0x182
83 #define MT6370_REG_RGB2_DIM 0x183
84 #define MT6370_REG_RGB3_DIM 0x184
85 #define MT6370_REG_RGB_EN 0x185
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
Dintel_rc6.c24 * low-voltage mode when idle, using down to 0V while at this stage. This
78 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA); in gen11_rc6_enable()
80 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); in gen11_rc6_enable()
139 for (i = 0; i < I915_MAX_VCS; i++) in gen11_rc6_enable()
173 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA); in gen9_rc6_enable()
175 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); in gen9_rc6_enable()
230 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); in gen8_rc6_enable()
258 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0); in gen6_rc6_enable()
275 rc6vids = 0; in gen6_rc6_enable()
280 (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { in gen6_rc6_enable()
[all …]
/kernel/linux/linux-5.10/include/linux/mfd/
Dintel_msic.h13 #define INTEL_MSIC_ID0 0x000 /* RO */
14 #define INTEL_MSIC_ID1 0x001 /* RO */
17 #define INTEL_MSIC_IRQLVL1 0x002
18 #define INTEL_MSIC_ADC1INT 0x003
19 #define INTEL_MSIC_CCINT 0x004
20 #define INTEL_MSIC_PWRSRCINT 0x005
21 #define INTEL_MSIC_PWRSRCINT1 0x006
22 #define INTEL_MSIC_CHRINT 0x007
23 #define INTEL_MSIC_CHRINT1 0x008
24 #define INTEL_MSIC_RTCIRQ 0x009
[all …]
/kernel/linux/linux-6.6/drivers/mfd/
Drz-mtu3.c28 /******* MTU3 registers (original offset is +0x1200) *******/
30 [RZ_MTU3_CHAN_0] = MTU_8BIT_CH_0(0x104, 0x090, 0x100, 0x128, 0x101, 0x102, 0x103, 0x126),
31 [RZ_MTU3_CHAN_1] = MTU_8BIT_CH_1_2(0x184, 0x091, 0x185, 0x180, 0x194, 0x181, 0x182),
32 [RZ_MTU3_CHAN_2] = MTU_8BIT_CH_1_2(0x204, 0x092, 0x205, 0x200, 0x20c, 0x201, 0x202),
33 …[RZ_MTU3_CHAN_3] = MTU_8BIT_CH_3_4_6_7(0x008, 0x093, 0x02c, 0x000, 0x04c, 0x002, 0x004, 0x005, 0x0…
34 …[RZ_MTU3_CHAN_4] = MTU_8BIT_CH_3_4_6_7(0x009, 0x094, 0x02d, 0x001, 0x04d, 0x003, 0x006, 0x007, 0x0…
35 …[RZ_MTU3_CHAN_5] = MTU_8BIT_CH_5(0xab2, 0x1eb, 0xab4, 0xab6, 0xa84, 0xa85, 0xa86, 0xa94, 0xa95, 0x…
36 …[RZ_MTU3_CHAN_6] = MTU_8BIT_CH_3_4_6_7(0x808, 0x893, 0x82c, 0x800, 0x84c, 0x802, 0x804, 0x805, 0x8…
37 …[RZ_MTU3_CHAN_7] = MTU_8BIT_CH_3_4_6_7(0x809, 0x894, 0x82d, 0x801, 0x84d, 0x803, 0x806, 0x807, 0x8…
38 [RZ_MTU3_CHAN_8] = MTU_8BIT_CH_8(0x404, 0x098, 0x400, 0x406, 0x401, 0x402, 0x403)
[all …]
/kernel/linux/linux-5.10/arch/x86/include/asm/
Dperf_event.h15 #define MSR_ARCH_PERFMON_PERFCTR0 0xc1
16 #define MSR_ARCH_PERFMON_PERFCTR1 0xc2
18 #define MSR_ARCH_PERFMON_EVENTSEL0 0x186
19 #define MSR_ARCH_PERFMON_EVENTSEL1 0x187
21 #define ARCH_PERFMON_EVENTSEL_EVENT 0x000000FFULL
22 #define ARCH_PERFMON_EVENTSEL_UMASK 0x0000FF00ULL
31 #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL
44 (0xFULL << AMD64_EVENTSEL_INT_CORE_SEL_SHIFT)
47 (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
53 (0xFULL << AMD64_L3_SLICE_SHIFT)
[all …]
/kernel/linux/linux-6.6/include/linux/mfd/mt6331/
Dregisters.h10 #define MT6331_STRUP_CON0 0x0
11 #define MT6331_STRUP_CON2 0x2
12 #define MT6331_STRUP_CON3 0x4
13 #define MT6331_STRUP_CON4 0x6
14 #define MT6331_STRUP_CON5 0x8
15 #define MT6331_STRUP_CON6 0xA
16 #define MT6331_STRUP_CON7 0xC
17 #define MT6331_STRUP_CON8 0xE
18 #define MT6331_STRUP_CON9 0x10
19 #define MT6331_STRUP_CON10 0x12
[all …]

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