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/kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/
Duniphier-pcie.txt52 reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
53 <0x2fff0000 0x10000>;
60 bus-range = <0x0 0xff>;
64 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000
66 0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
69 interrupts = <0 224 4>, <0 225 4>;
70 interrupt-map-mask = <0 0 0 7>;
71 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
72 <0 0 0 2 &pcie_intc 1>, /* INTB */
73 <0 0 0 3 &pcie_intc 2>, /* INTC */
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/
Dsocionext,uniphier-pcie.yaml88 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
95 bus-range = <0x0 0xff>;
97 ranges = <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>,
98 <0x82000000 0 0x00000000 0x20000000 0 0x0ffe0000>;
104 interrupts = <0 224 4>, <0 225 4>;
105 interrupt-map-mask = <0 0 0 7>;
106 interrupt-map = <0 0 0 1 &pcie_intc 0>,
107 <0 0 0 2 &pcie_intc 1>,
108 <0 0 0 3 &pcie_intc 2>,
109 <0 0 0 4 &pcie_intc 3>;
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-u300/
Dcore.c29 #define U300_NAND_CS0_PHYS_BASE 0x80000000
31 #define U300_NAND_IF_PHYS_BASE 0x9f800000
36 #define U300_AHB_PER_PHYS_BASE 0xa0000000
37 #define U300_AHB_PER_VIRT_BASE 0xff010000
39 #define U300_FAST_PER_PHYS_BASE 0xc0000000
40 #define U300_FAST_PER_VIRT_BASE 0xff020000
42 #define U300_SLOW_PER_PHYS_BASE 0xc0010000
43 #define U300_SLOW_PER_VIRT_BASE 0xff000000
45 #define U300_BOOTROM_PHYS_BASE 0xffff0000
46 #define U300_BOOTROM_VIRT_BASE 0xffff0000
[all …]
/kernel/linux/linux-5.10/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi20 #size-cells = <0>;
39 cpu0: cpu@0 {
42 reg = <0 0x000>;
52 reg = <0 0x001>;
62 reg = <0 0x002>;
72 reg = <0 0x003>;
126 #clock-cells = <0>;
181 reg = <0x0 0x81000000 0x0 0x01000000>;
186 soc@0 {
190 ranges = <0 0 0 0xffffffff>;
[all …]
Duniphier-ld20.dtsi20 #size-cells = <0>;
42 cpu0: cpu@0 {
45 reg = <0 0x000>;
55 reg = <0 0x001>;
65 reg = <0 0x100>;
75 reg = <0 0x101>;
167 #clock-cells = <0>;
222 reg = <0x0 0x81000000 0x0 0x01000000>;
227 soc@0 {
231 ranges = <0 0 0 0xffffffff>;
[all …]
/kernel/linux/linux-6.6/arch/arm64/boot/dts/socionext/
Duniphier-pxs3.dtsi21 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0 0x000>;
54 reg = <0 0x001>;
65 reg = <0 0x002>;
76 reg = <0 0x003>;
135 #clock-cells = <0>;
190 reg = <0x0 0x81000000 0x0 0x01000000>;
195 soc@0 {
199 ranges = <0 0 0 0xffffffff>;
[all …]
Duniphier-ld20.dtsi21 #size-cells = <0>;
43 cpu0: cpu@0 {
46 reg = <0 0x000>;
57 reg = <0 0x001>;
68 reg = <0 0x100>;
79 reg = <0 0x101>;
96 cluster0_opp: opp-table-0 {
180 #clock-cells = <0>;
235 reg = <0x0 0x81000000 0x0 0x01000000>;
240 soc@0 {
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/nvidia/
Dtegra20-asus-tf101.dts38 memory@0 {
39 reg = <0x00000000 0x40000000>;
49 reg = <0x2ffe0000 0x10000>; /* 64kB */
50 console-size = <0x8000>; /* 32kB */
51 record-size = <0x400>; /* 1kB */
57 alloc-ranges = <0x30000000 0x10000000>;
58 size = <0x10000000>; /* 256MiB */
69 port@0 {
101 pinctrl-0 = <&state_default>;
482 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
[all …]
Dtegra20-acer-a500-picasso.dts37 memory@0 {
38 reg = <0x00000000 0x40000000>;
48 reg = <0x2ffe0000 0x10000>; /* 64kB */
49 console-size = <0x8000>; /* 32kB */
50 record-size = <0x400>; /* 1kB */
56 alloc-ranges = <0x30000000 0x10000000>;
57 size = <0x10000000>; /* 256MiB */
68 port@0 {
92 pinctrl-0 = <&state_default>;
425 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dtegra20-acer-a500-picasso.dts36 memory@0 {
37 reg = <0x00000000 0x40000000>;
47 reg = <0x2ffe0000 0x10000>; /* 64kB */
48 console-size = <0x8000>; /* 32kB */
49 record-size = <0x400>; /* 1kB */
55 alloc-ranges = <0x30000000 0x10000000>;
56 size = <0x10000000>; /* 256MiB */
67 port@0 {
91 pinctrl-0 = <&state_default>;
406 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
[all …]