| /kernel/linux/linux-5.10/drivers/vfio/pci/ |
| D | vfio_pci_rdwr.c | 57 return 0; \
84 return 0; \
102 ssize_t done = 0; in do_io_rw()
113 fillable = 0; in do_io_rw()
185 u8 val = 0xFF; in do_io_rw()
188 for (i = 0; i < filled; i++) in do_io_rw()
210 return 0; in vfio_pci_setup_barmap()
216 io = pci_iomap(pdev, bar, 0); in vfio_pci_setup_barmap()
224 return 0; in vfio_pci_setup_barmap()
233 size_t x_start = 0, x_end = 0; in vfio_pci_bar_rw()
[all …]
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| /kernel/linux/linux-6.6/drivers/vfio/pci/ |
| D | vfio_pci_rdwr.c | 57 return 0; \
84 return 0; \
102 ssize_t done = 0; in do_io_rw()
113 fillable = 0; in do_io_rw()
185 u8 val = 0xFF; in do_io_rw()
188 for (i = 0; i < filled; i++) in do_io_rw()
210 return 0; in vfio_pci_setup_barmap()
216 io = pci_iomap(pdev, bar, 0); in vfio_pci_setup_barmap()
224 return 0; in vfio_pci_setup_barmap()
233 size_t x_start = 0, x_end = 0; in vfio_pci_bar_rw()
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/vboxvideo/ |
| D | vboxvideo_vbe.h | 9 #define VBE_DISPI_BANK_ADDRESS 0xA0000
16 #define VBE_DISPI_IOPORT_INDEX 0x01CE
17 #define VBE_DISPI_IOPORT_DATA 0x01CF
19 #define VBE_DISPI_IOPORT_DAC_WRITE_INDEX 0x03C8
20 #define VBE_DISPI_IOPORT_DAC_DATA 0x03C9
22 #define VBE_DISPI_INDEX_ID 0x0
23 #define VBE_DISPI_INDEX_XRES 0x1
24 #define VBE_DISPI_INDEX_YRES 0x2
25 #define VBE_DISPI_INDEX_BPP 0x3
26 #define VBE_DISPI_INDEX_ENABLE 0x4
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/vboxvideo/ |
| D | vboxvideo_vbe.h | 9 #define VBE_DISPI_BANK_ADDRESS 0xA0000
16 #define VBE_DISPI_IOPORT_INDEX 0x01CE
17 #define VBE_DISPI_IOPORT_DATA 0x01CF
19 #define VBE_DISPI_IOPORT_DAC_WRITE_INDEX 0x03C8
20 #define VBE_DISPI_IOPORT_DAC_DATA 0x03C9
22 #define VBE_DISPI_INDEX_ID 0x0
23 #define VBE_DISPI_INDEX_XRES 0x1
24 #define VBE_DISPI_INDEX_YRES 0x2
25 #define VBE_DISPI_INDEX_BPP 0x3
26 #define VBE_DISPI_INDEX_ENABLE 0x4
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hwio.h | 13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define INTR2_CLEAR 0x02c
20 #define HIST_INTR_EN 0x01c
21 #define HIST_INTR_STATUS 0x020
22 #define HIST_INTR_CLEAR 0x024
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_hwio.h | 13 #define DISP_INTF_SEL 0x004
14 #define INTR_EN 0x010
15 #define INTR_STATUS 0x014
16 #define INTR_CLEAR 0x018
17 #define INTR2_EN 0x008
18 #define INTR2_STATUS 0x00c
19 #define SSPP_SPARE 0x028
20 #define INTR2_CLEAR 0x02c
21 #define HIST_INTR_EN 0x01c
22 #define HIST_INTR_STATUS 0x020
[all …]
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| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 33 reg = <0xe0700000 0x1000>;
34 st-spics,peripcfg-reg = <0x3b0>;
46 cs-gpios = <&gpio1 7 0>, <&spics 0>,
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/gpio/ |
| D | spear_spics.txt | 33 reg = <0xe0700000 0x1000>;
34 st-spics,peripcfg-reg = <0x3b0>;
46 cs-gpios = <&gpio1 7 0>, <&spics 0>,
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pinctrl/ |
| D | fsl,imxrt1170.yaml | 71 reg = <0x400e8000 0x4000>;
74 <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
75 <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
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| /kernel/linux/linux-6.6/arch/alpha/include/asm/ |
| D | vga.h | 57 (((a) >= 0x3b0) && ((a) < 0x3e0) && \
58 ((a) != 0x3b3) && ((a) != 0x3d3))
61 (((a) >= 0xa0000) && ((a) <= 0xc0000))
66 } while(0)
71 } while(0)
74 # define pci_vga_hose 0
75 # define __is_port_vga(a) 0
76 # define __is_mem_vga(a) 0
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| /kernel/linux/linux-5.10/arch/alpha/include/asm/ |
| D | vga.h | 57 (((a) >= 0x3b0) && ((a) < 0x3e0) && \
58 ((a) != 0x3b3) && ((a) != 0x3d3))
61 (((a) >= 0xa0000) && ((a) <= 0xc0000))
66 } while(0)
71 } while(0)
74 # define pci_vga_hose 0
75 # define __is_port_vga(a) 0
76 # define __is_mem_vga(a) 0
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| /kernel/linux/linux-6.6/drivers/video/ |
| D | vgastate.c | 37 vga_w(regbase, iobase + 0x4, reg); in vga_rcrtcs()
38 return vga_r(regbase, iobase + 0x5); in vga_rcrtcs()
44 vga_w(regbase, iobase + 0x4, reg); in vga_wcrtcs()
45 vga_w(regbase, iobase + 0x5, val); in vga_wcrtcs()
57 iobase = (misc & 1) ? 0x3d0 : 0x3b0; in save_vga_text()
59 vga_r(state->vgabase, iobase + 0xa); in save_vga_text()
60 vga_w(state->vgabase, VGA_ATT_W, 0x00); in save_vga_text()
61 attr10 = vga_rattr(state->vgabase, 0x10); in save_vga_text()
62 vga_r(state->vgabase, iobase + 0xa); in save_vga_text()
63 vga_w(state->vgabase, VGA_ATT_W, 0x20); in save_vga_text()
[all …]
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| /kernel/linux/linux-5.10/drivers/video/ |
| D | vgastate.c | 37 vga_w(regbase, iobase + 0x4, reg); in vga_rcrtcs()
38 return vga_r(regbase, iobase + 0x5); in vga_rcrtcs()
44 vga_w(regbase, iobase + 0x4, reg); in vga_wcrtcs()
45 vga_w(regbase, iobase + 0x5, val); in vga_wcrtcs()
57 iobase = (misc & 1) ? 0x3d0 : 0x3b0; in save_vga_text()
59 vga_r(state->vgabase, iobase + 0xa); in save_vga_text()
60 vga_w(state->vgabase, VGA_ATT_W, 0x00); in save_vga_text()
61 attr10 = vga_rattr(state->vgabase, 0x10); in save_vga_text()
62 vga_r(state->vgabase, iobase + 0xa); in save_vga_text()
63 vga_w(state->vgabase, VGA_ATT_W, 0x20); in save_vga_text()
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/nxp/imx/ |
| D | imxrt1050-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000
17 #define MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00 0x014 0x204 0x000 0x0 0x0
18 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXPWM4_PWM0_A 0x014 0x204 0x494 0x1 0x0
19 #define MXRT1050_IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x014 0x204 0x500 0x2 0x1
20 #define MXRT1050_IOMUXC_GPIO_EMC_00_XBAR_INOUT2 0x014 0x204 0x60C 0x3 0x0
21 #define MXRT1050_IOMUXC_GPIO_EMC_00_FLEXIO1_D00 0x014 0x204 0x000 0x4 0x0
22 #define MXRT1050_IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x014 0x204 0x000 0x5 0x0
24 #define MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01 0x018 0x208 0x000 0x0 0x0
25 #define MXRT1050_IOMUXC_GPIO_EMC_01_FLEXPWM4_PWM0_B 0x018 0x208 0x000 0x1 0x0
26 #define MXRT1050_IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x018 0x208 0x4FC 0x2 0x1
[all …]
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| D | imxrt1170-pinfunc.h | 10 #define IMX_PAD_SION 0x40000000
17 #define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x000 0x040 0x0 0x0 0x0
18 #define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x000 0x040 0x0 0x1 0x0
19 #define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x000 0x040 0x0 0x2 0x0
20 #define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x000 0x040 0x0 0x3 0x0
21 #define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x000 0x040 0x0 0x5 0x0
22 #define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x000 0x040 0x0B0 0x6 0x0
23 #define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x000 0x040 0x0C8 0x7 0x0
24 #define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x000 0x040 0x0 0xA 0x0
26 #define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x004 0x044 0x080 0x0 0x0
[all …]
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| D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
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| D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | hgafb.c | 23 * module parameter 'nologo={0|1}'
25 * - Revision 0.1.0 (6 Dec 1999): faster scrolling and minor fixes
47 #if 0
53 #if 0
65 #define HGA_TXT 0
73 static int hga_mode = -1; /* 0 = txt, 1 = gfx mode */
78 #define HGA_INDEX_PORT 0x3b4 /* Register select port */
79 #define HGA_VALUE_PORT 0x3b5 /* Register value port */
80 #define HGA_MODE_PORT 0x3b8 /* Mode control port */
81 #define HGA_STATUS_PORT 0x3ba /* Status and Config port */
[all …]
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| /kernel/linux/linux-6.6/drivers/video/fbdev/ |
| D | hgafb.c | 23 * module parameter 'nologo={0|1}'
25 * - Revision 0.1.0 (6 Dec 1999): faster scrolling and minor fixes
47 #if 0
53 #if 0
65 #define HGA_TXT 0
73 static int hga_mode = -1; /* 0 = txt, 1 = gfx mode */
78 #define HGA_INDEX_PORT 0x3b4 /* Register select port */
79 #define HGA_VALUE_PORT 0x3b5 /* Register value port */
80 #define HGA_MODE_PORT 0x3b8 /* Mode control port */
81 #define HGA_STATUS_PORT 0x3ba /* Status and Config port */
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | imx25-pinfunc.h | 16 #define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
17 #define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
19 #define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
20 #define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
21 #define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
23 #define MX25_PAD_A14__A14 0x010 0x230 0x000 0x00 0x000
24 #define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x05 0x000
25 #define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x06 0x000
26 #define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x07 0x000
28 #define MX25_PAD_A15__A15 0x014 0x234 0x000 0x00 0x000
[all …]
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| D | imx6q-pinfunc.h | 13 #define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
14 #define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
15 #define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
16 #define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
17 #define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
18 #define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
19 #define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
20 #define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
21 #define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
22 #define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
[all …]
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| /kernel/linux/linux-5.10/arch/sh/include/mach-sdk7786/mach/ |
| D | fpga.h | 9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
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| /kernel/linux/linux-6.6/arch/sh/include/mach-sdk7786/mach/ |
| D | fpga.h | 9 #define SRSTR 0x000
10 #define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
12 #define INTASR 0x010
13 #define INTAMR 0x020
14 #define MODSWR 0x030
15 #define INTTESTR 0x040
16 #define SYSSR 0x050
17 #define NRGPR 0x060
19 #define NMISR 0x070
20 #define NMISR_MAN_NMI BIT(0)
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/freescale/ |
| D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/freescale/ |
| D | imx8mp-pinfunc.h | 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0
14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0
15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0
16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0
17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0
18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0
19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0
20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0
21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0
22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0
[all …]
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