Searched +full:0 +full:x40300 (Results 1 – 9 of 9) sorted by relevance
12 - #address-cells: must be 033 reg = <0x403c0 0x8 0x40300 0x18>;36 #address-cells = <0>;39 phy@0 {41 reg = <0>;
25 - brcm,asp-v2.0-mdio78 reg = <0x403c0 0x8>, <0x40300 0x18>;81 #size-cells = <0>;83 ethernet-phy@0 {85 reg = <0>;
22 #define mmMME1_RTR_HBW_RD_RQ_E_ARB 0x4010024 #define mmMME1_RTR_HBW_RD_RQ_W_ARB 0x4010426 #define mmMME1_RTR_HBW_RD_RQ_N_ARB 0x4010828 #define mmMME1_RTR_HBW_RD_RQ_S_ARB 0x4010C30 #define mmMME1_RTR_HBW_RD_RQ_L_ARB 0x4011032 #define mmMME1_RTR_HBW_E_ARB_MAX 0x4012034 #define mmMME1_RTR_HBW_W_ARB_MAX 0x4012436 #define mmMME1_RTR_HBW_N_ARB_MAX 0x4012838 #define mmMME1_RTR_HBW_S_ARB_MAX 0x4012C40 #define mmMME1_RTR_HBW_L_ARB_MAX 0x40130[all …]
14 #define uPD98401_PORTS 0x24 /* probably more ? */21 #define uPD98401_OPEN_CHAN 0x20000000 /* open channel */22 #define uPD98401_CHAN_ADDR 0x0003fff8 /* channel address */24 #define uPD98401_CLOSE_CHAN 0x24000000 /* close channel */25 #define uPD98401_CHAN_RT 0x02000000 /* RX/TX (0 TX, 1 RX) */26 #define uPD98401_DEACT_CHAN 0x28000000 /* deactivate channel */27 #define uPD98401_TX_READY 0x30000000 /* TX ready */28 #define uPD98401_ADD_BAT 0x34000000 /* add batches */29 #define uPD98401_POOL 0x000f0000 /* pool number */31 #define uPD98401_POOL_NUMBAT 0x0000ffff /* number of batches */[all …]
57 static int vid_cap_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };61 static int vid_out_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };65 static int vbi_cap_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };69 static int vbi_out_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };73 static int sdr_cap_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };77 static int radio_rx_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };81 static int radio_tx_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };85 static int meta_cap_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };89 static int meta_out_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };93 static int touch_cap_nr[VIVID_MAX_DEVS] = { [0 ... (VIVID_MAX_DEVS - 1)] = -1 };[all …]
54 * at the time it indicated completion is stored there. Returns 0 if the66 return 0; in t4_wait_op_done_val()68 if (--attempts == 0) in t4_wait_op_done_val()167 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a in t4_hw_pci_read_cfg4()169 * ENABLE is 0 so a simple register write is easier than a in t4_hw_pci_read_cfg4()172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()247 log->cursor = 0; in t4_record_mbox()249 for (i = 0; i < size / 8; i++) in t4_record_mbox()252 entry->cmd[i++] = 0; in t4_record_mbox()277 * The return value is 0 on success or a negative errno on failure. A[all …]