| /kernel/linux/linux-5.10/Documentation/devicetree/bindings/pci/ |
| D | faraday,ftpci100.txt | 9 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10 Technology) and product ID 0x4321.
23 - bus-range: set to <0x00 0xff>
45 - #address-cells: set to <0>
64 interrupt-map-mask = <0xf800 0 0 7>;
66 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67 <0x4800 0 0 2 &pci_intc 1>,
68 <0x4800 0 0 3 &pci_intc 2>,
69 <0x4800 0 0 4 &pci_intc 3>,
70 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
[all …]
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| D | v3-v360epc-pci.txt | 18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
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| /kernel/linux/linux-6.6/Documentation/devicetree/bindings/pci/ |
| D | faraday,ftpci100.yaml | 18 The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
19 Technology) and product ID 0x4321.
34 interrupt-map-mask = <0xf800 0 0 7>;
36 <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
37 <0x4800 0 0 2 &pci_intc 1>,
38 <0x4800 0 0 3 &pci_intc 2>,
39 <0x4800 0 0 4 &pci_intc 3>,
40 <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
41 <0x5000 0 0 2 &pci_intc 2>,
42 <0x5000 0 0 3 &pci_intc 3>,
[all …]
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| D | v3-v360epc-pci.txt | 18 each be exactly 256MB (0x10000000) in size.
38 reg = <0x62000000 0x10000>, <0x61000000 0x01000000>;
42 bus-range = <0x00 0xff>;
43 ranges = 0x01000000 0 0x00000000 /* I/O space @00000000 */
44 0x60000000 0 0x01000000 /* 16 MiB @ LB 60000000 */
45 0x02000000 0 0x40000000 /* non-prefectable memory @40000000 */
46 0x40000000 0 0x10000000 /* 256 MiB @ LB 40000000 1:1 */
47 0x42000000 0 0x50000000 /* prefetchable memory @50000000 */
48 0x50000000 0 0x10000000>; /* 256 MiB @ LB 50000000 1:1 */
49 dma-ranges = <0x02000000 0 0x20000000 /* EBI memory space */
[all …]
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| /kernel/linux/linux-5.10/arch/arm/boot/dts/ |
| D | gemini-wbd111.dts | 17 memory@0 {
20 reg = <0x00000000 0x8000000>;
76 #size-cells = <0>;
88 reg = <0x30000000 0x00800000>;
90 partition@0 {
92 reg = <0x00000000 0x00020000>;
97 reg = <0x00020000 0x00100000>;
101 reg = <0x00120000 0x006a0000>;
105 reg = <0x007c0000 0x00010000>;
110 reg = <0x007d0000 0x00010000>;
[all …]
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| D | gemini-wbd222.dts | 17 memory@0 { /* 128 MB */
19 reg = <0x00000000 0x8000000>;
75 #size-cells = <0>;
92 reg = <0x30000000 0x00800000>;
94 partition@0 {
96 reg = <0x00000000 0x00020000>;
101 reg = <0x00020000 0x00100000>;
105 reg = <0x00120000 0x006a0000>;
109 reg = <0x007c0000 0x00010000>;
114 reg = <0x007d0000 0x00010000>;
[all …]
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| D | gemini-sq201.dts | 17 memory@0 { /* 128 MB */
19 reg = <0x00000000 0x8000000>;
62 #size-cells = <0>;
73 #size-cells = <0>;
81 switch@0 {
83 reg = <0>;
91 #size-cells = <0>;
93 port@0 {
94 reg = <0>;
129 pinctrl-0 = <&pflash_default_pins>;
[all …]
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| D | gemini-sl93512r.dts | 20 memory@0 {
23 reg = <0x00000000 0x4000000>;
40 gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
77 #size-cells = <0>;
88 #size-cells = <0>;
96 switch@0 {
98 reg = <0>;
106 #size-cells = <0>;
108 port@0 {
109 reg = <0>;
[all …]
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| D | integratorap.dts | 17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
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| D | gemini-dlink-dir-685.dts | 16 memory@0 {
19 reg = <0x00000000 0x8000000>;
35 /* Collides with LPC_LAD[0], UART DCD, SSP 97RST */
61 #size-cells = <0>;
70 panel: display@0 {
72 reg = <0>;
130 gpio-fan,speed-map = <0 0>, <10000 1>;
178 #size-cells = <0>;
182 reg = <0x26>;
203 #address-cells = <0>;
[all …]
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| D | alpine.dtsi | 37 reg = <0 0 0 0>;
43 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
97 #size-cells = <0>;
98 #address-cells = <0>;
100 reg = <0x0 0xfb001000 0x0 0x1000>,
101 <0x0 0xfb002000 0x0 0x2000>,
102 <0x0 0xfb004000 0x0 0x2000>,
103 <0x0 0xfb006000 0x0 0x2000>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/arm/ |
| D | integratorap.dts | 17 #size-cells = <0>;
19 cpu@0 {
28 reg = <0>;
37 operating-points = <71000 0
38 66000 0
39 60000 0
40 48000 0
41 36000 0
42 24000 0
43 12000 0>;
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/gemini/ |
| D | gemini.dtsi | 23 pinctrl-0 = <&pflash_default_pins>;
31 reg = <0x40000000 0x1000>;
39 offset = <0x0c>;
41 mask = <0xC0000000>;
49 pinctrl-0 = <&dram_default_pins>, <&system_default_pins>,
159 reg = <0x41000000 0x1000>;
168 reg = <0x42000000 0x100>;
173 pinctrl-0 = <&uart_default_pins>;
179 reg = <0x43000000 0x1000>;
193 reg = <0x45000000 0x100>;
[all …]
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| /kernel/linux/linux-6.6/drivers/cpufreq/ |
| D | ti-cpufreq.c | 20 #define REVISION_MASK 0xF
23 #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
24 #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
32 #define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
37 #define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
38 #define OMAP3_CONTROL_IDCODE 0x4830A204
39 #define OMAP34xx_ProdID_SKUID 0x4830A20C
40 #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
46 #define AM625_SUPPORT_K_MPU_OPP BIT(0)
137 .efuse_offset = 0x07fc,
[all …]
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| /kernel/linux/linux-5.10/drivers/cpufreq/ |
| D | ti-cpufreq.c | 20 #define REVISION_MASK 0xF
23 #define AM33XX_800M_ARM_MPU_MAX_FREQ 0x1E2F
24 #define AM43XX_600M_ARM_MPU_MAX_FREQ 0xFFA
32 #define DRA7_EFUSE_NOM_MPU_OPP BIT(0)
37 #define OMAP3_CONTROL_DEVICE_STATUS 0x4800244C
38 #define OMAP3_CONTROL_IDCODE 0x4830A204
39 #define OMAP34xx_ProdID_SKUID 0x4830A20C
40 #define OMAP3_SYSCON_BASE (0x48000000 + 0x2000 + 0x270)
111 .efuse_offset = 0x07fc,
112 .efuse_mask = 0x1fff,
[all …]
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| /kernel/linux/linux-6.6/drivers/regulator/ |
| D | qcom_spmi-regulator.c | 25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
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| /kernel/linux/linux-6.6/drivers/video/fbdev/ |
| D | hpfb.c | 34 #define TC_NBLANK 0x4080
35 #define TC_WEN 0x4088
36 #define TC_REN 0x408c
37 #define TC_FBEN 0x4090
38 #define TC_PRR 0x40ea
41 #define RR_CLEAR 0x0
42 #define RR_COPY 0x3
43 #define RR_NOOP 0x5
44 #define RR_XOR 0x6
45 #define RR_INVERT 0xa
[all …]
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| /kernel/linux/linux-5.10/drivers/video/fbdev/ |
| D | hpfb.c | 34 #define TC_NBLANK 0x4080
35 #define TC_WEN 0x4088
36 #define TC_REN 0x408c
37 #define TC_FBEN 0x4090
38 #define TC_PRR 0x40ea
41 #define RR_CLEAR 0x0
42 #define RR_COPY 0x3
43 #define RR_NOOP 0x5
44 #define RR_XOR 0x6
45 #define RR_INVERT 0xa
[all …]
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| /kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/ |
| D | a2xx_gpu.c | 18 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
42 OUT_RING(ring, 0x00000000); in a2xx_submit()
49 OUT_RING(ring, 0x80000000); in a2xx_submit()
58 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
62 /* All fields present (bits 9:0) */ in a2xx_me_init()
63 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
65 OUT_RING(ring, 0x00000000); in a2xx_me_init()
67 OUT_RING(ring, 0x00000000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
70 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
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| /kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
| D | a2xx_gpu.c | 19 for (i = 0; i < submit->nr_cmds; i++) { in a2xx_submit()
43 OUT_RING(ring, 0x00000000); in a2xx_submit()
50 OUT_RING(ring, 0x80000000); in a2xx_submit()
57 struct msm_ringbuffer *ring = gpu->rb[0]; in a2xx_me_init()
61 /* All fields present (bits 9:0) */ in a2xx_me_init()
62 OUT_RING(ring, 0x000003ff); in a2xx_me_init()
64 OUT_RING(ring, 0x00000000); in a2xx_me_init()
66 OUT_RING(ring, 0x00000000); in a2xx_me_init()
68 OUT_RING(ring, REG_A2XX_RB_SURFACE_INFO - 0x2000); in a2xx_me_init()
69 OUT_RING(ring, REG_A2XX_PA_SC_WINDOW_OFFSET - 0x2000); in a2xx_me_init()
[all …]
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| /kernel/linux/linux-6.6/arch/arm/boot/dts/amazon/ |
| D | alpine.dtsi | 37 reg = <0 0 0 0>;
43 #size-cells = <0>;
46 cpu@0 {
49 reg = <0>;
97 #size-cells = <0>;
98 #address-cells = <0>;
100 reg = <0x0 0xfb001000 0x0 0x1000>,
101 <0x0 0xfb002000 0x0 0x2000>,
102 <0x0 0xfb004000 0x0 0x2000>,
103 <0x0 0xfb006000 0x0 0x2000>;
[all …]
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| /kernel/linux/linux-6.6/drivers/media/i2c/ |
| D | ov5647.c | 42 #define MIPI_CTRL00_CLOCK_LANE_DISABLE BIT(0)
44 #define OV5647_SW_STANDBY 0x0100
45 #define OV5647_SW_RESET 0x0103
46 #define OV5647_REG_CHIPID_H 0x300a
47 #define OV5647_REG_CHIPID_L 0x300b
48 #define OV5640_REG_PAD_OUT 0x300d
49 #define OV5647_REG_EXP_HI 0x3500
50 #define OV5647_REG_EXP_MID 0x3501
51 #define OV5647_REG_EXP_LO 0x3502
52 #define OV5647_REG_AEC_AGC 0x3503
[all …]
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| /kernel/linux/linux-6.6/arch/arm64/boot/dts/amazon/ |
| D | alpine-v2.dtsi | 47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0x0 0x0>;
59 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
73 reg = <0x0 0x3>;
81 cpu_suspend = <0x84000001>;
82 cpu_off = <0x84000002>;
83 cpu_on = <0x84000003>;
88 #clock-cells = <0>;
[all …]
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| /kernel/linux/linux-5.10/arch/arm64/boot/dts/amazon/ |
| D | alpine-v2.dtsi | 47 #size-cells = <0>;
49 cpu@0 {
52 reg = <0x0 0x0>;
59 reg = <0x0 0x1>;
66 reg = <0x0 0x2>;
73 reg = <0x0 0x3>;
81 cpu_suspend = <0x84000001>;
82 cpu_off = <0x84000002>;
83 cpu_on = <0x84000003>;
88 #clock-cells = <0>;
[all …]
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| /kernel/linux/linux-5.10/drivers/regulator/ |
| D | qcom_spmi-regulator.c | 24 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
32 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
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