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/kernel/linux/linux-6.6/arch/arm/mach-omap2/
Domap54xx.h17 #define L4_54XX_BASE 0x4a000000
18 #define L4_WK_54XX_BASE 0x4ae00000
19 #define L4_PER_54XX_BASE 0x48000000
20 #define L3_54XX_BASE 0x44000000
21 #define OMAP54XX_32KSYNCT_BASE 0x4ae04000
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
23 #define OMAP54XX_CM_CORE_BASE 0x4a008000
24 #define OMAP54XX_PRM_BASE 0x4ae06000
25 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
26 #define OMAP54XX_SCM_BASE 0x4a002000
[all …]
Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-omap2/
Domap54xx.h17 #define L4_54XX_BASE 0x4a000000
18 #define L4_WK_54XX_BASE 0x4ae00000
19 #define L4_PER_54XX_BASE 0x48000000
20 #define L3_54XX_BASE 0x44000000
21 #define OMAP54XX_32KSYNCT_BASE 0x4ae04000
22 #define OMAP54XX_CM_CORE_AON_BASE 0x4a004000
23 #define OMAP54XX_CM_CORE_BASE 0x4a008000
24 #define OMAP54XX_PRM_BASE 0x4ae06000
25 #define OMAP54XX_PRCM_MPU_BASE 0x48243000
26 #define OMAP54XX_SCM_BASE 0x4a002000
[all …]
Diomap.h33 #define OMAP2_L3_IO_OFFSET 0x90000000
36 #define OMAP2_L4_IO_OFFSET 0xb2000000
39 #define OMAP4_L3_IO_OFFSET 0xb4000000
42 #define AM33XX_L4_WK_IO_OFFSET 0xb5000000
45 #define OMAP4_L3_PER_IO_OFFSET 0xb1100000
48 #define OMAP2_EMU_IO_OFFSET 0xaa800000 /* Emulation */
58 #define L3_24XX_PHYS L3_24XX_BASE /* 0x68000000 --> 0xf8000000*/
61 #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 --> 0xfa000000 */
65 #define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 --> 0xfb000000 */
70 /* 0x6e000000 --> 0xfe000000 */
[all …]
Domap44xx.h17 #define L4_44XX_BASE 0x4a000000
18 #define L4_WK_44XX_BASE 0x4a300000
19 #define L4_PER_44XX_BASE 0x48000000
20 #define L4_EMU_44XX_BASE 0x54000000
21 #define L3_44XX_BASE 0x44000000
22 #define OMAP44XX_EMIF1_BASE 0x4c000000
23 #define OMAP44XX_EMIF2_BASE 0x4d000000
24 #define OMAP44XX_DMM_BASE 0x4e000000
25 #define OMAP4430_32KSYNCT_BASE 0x4a304000
26 #define OMAP4430_CM1_BASE 0x4a004000
[all …]
/kernel/linux/linux-6.6/arch/arm/mach-pxa/
Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
Dsmemc.h11 #define PXA2XX_SMEMC_BASE 0x48000000
12 #define PXA3XX_SMEMC_BASE 0x4a000000
13 #define SMEMC_VIRT IOMEM(0xf6000000)
15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
17 #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */
18 #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */
19 #define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */
20 #define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/
Daddr-map.h8 #define PXA_CS0_PHYS 0x00000000
9 #define PXA_CS1_PHYS 0x04000000
10 #define PXA_CS2_PHYS 0x08000000
11 #define PXA_CS3_PHYS 0x0C000000
12 #define PXA_CS4_PHYS 0x10000000
13 #define PXA_CS5_PHYS 0x14000000
15 #define PXA300_CS0_PHYS 0x00000000 /* PXA300/PXA310 _only_ */
16 #define PXA300_CS1_PHYS 0x30000000 /* PXA300/PXA310 _only_ */
17 #define PXA3xx_CS2_PHYS 0x10000000
18 #define PXA3xx_CS3_PHYS 0x14000000
[all …]
Dsmemc.h11 #define PXA2XX_SMEMC_BASE 0x48000000
12 #define PXA3XX_SMEMC_BASE 0x4a000000
13 #define SMEMC_VIRT IOMEM(0xf6000000)
15 #define MDCNFG (SMEMC_VIRT + 0x00) /* SDRAM Configuration Register 0 */
16 #define MDREFR (SMEMC_VIRT + 0x04) /* SDRAM Refresh Control Register */
17 #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */
18 #define MSC1 (SMEMC_VIRT + 0x0C) /* Static Memory Control Register 1 */
19 #define MSC2 (SMEMC_VIRT + 0x10) /* Static Memory Control Register 2 */
20 #define MECR (SMEMC_VIRT + 0x14) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
21 #define SXLCR (SMEMC_VIRT + 0x18) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/interrupt-controller/
Dsamsung,s3c24xx-irq.txt22 - 0 ... main controller
34 reg = <0x4a000000 0x100>;
43 reg = <0x50000000 0x4000>;
45 interrupts = <1 28 0 4>, <1 28 1 4>;
50 reg = <0x57000000 0x100>;
52 interrupts = <0 30 0 3>, <0 8 0 3>;
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Ds3c24xx.dtsi23 reg = <0x4a000000 0x100>;
29 reg = <0x56000000 0x1000>;
33 interrupts = <0 0 0 3>,
34 <0 0 1 3>,
35 <0 0 2 3>,
36 <0 0 3 3>,
37 <0 0 4 4>,
38 <0 0 5 4>;
44 reg = <0x51000000 0x1000>;
45 interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>;
[all …]
Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
3 reg = <0x44c00000 0x800>,
4 <0x44c00800 0x800>,
5 <0x44c01000 0x400>,
6 <0x44c01400 0x400>;
10 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
11 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
12 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
14 segment@0 { /* 0x44c00000 */
18 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
9 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
10 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
11 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
12 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
13 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
14 <0x00280000 0x4a280000 0x080000>, /* segment 5 */
[all …]
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
Dmap-s3c24xx.h19 #define S3C2410_PA_IRQ (0x4A000000)
23 #define S3C2410_PA_MEMCTRL (0x48000000)
27 #define S3C2410_PA_TIMER (0x51000000)
34 #define S3C2410_PA_USBDEV (0x52000000)
38 #define S3C2410_PA_WATCHDOG (0x53000000)
52 #define S3C2410_PA_USBHOST (0x49000000)
55 #define S3C2416_PA_HSUDC (0x49800000)
59 #define S3C2410_PA_DMA (0x4B000000)
63 #define S3C2410_PA_CLKPWR (0x4C000000)
66 #define S3C2410_PA_LCD (0x4D000000)
[all …]
Dirq-s3c24xx.c36 #define S3C_IRQTYPE_NONE 0
72 * [0] ... main_intc
155 return 0; in s3c_irq_type()
164 unsigned long newvalue = 0, value; in s3c_irqext_type_set()
168 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); in s3c_irqext_type_set()
207 return 0; in s3c_irqext_type_set()
306 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0; in s3c_irq_demux()
338 intc_offset = 0; in s3c24xx_handle_intc()
367 * s3c_intc[0] = s3c24xx_init_intc() in s3c24xx_handle_irq()
372 * setting s3c_intc[0] only if it was called with num_ctrl=0. There is no in s3c24xx_handle_irq()
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/bus/
Dti-sysc.txt101 using offsets from l4_cfg second segment (0x4a000000 + 0x80000 = 0x4a0ab000):
103 target-module@2b000 { /* 0x4a0ab000, ap 84 12.0 */
106 reg = <0x2b400 0x4>,
107 <0x2b404 0x4>,
108 <0x2b408 0x4>;
110 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
125 ranges = <0 0x2b000 0x1000>;
127 usb_otg_hs: otg@0 {
129 reg = <0x0 0x7ff>;
/kernel/linux/linux-6.6/arch/powerpc/lib/
Dtest-code-patching.c17 return 0; in instr_is_branch_to_addr()
28 } while (0)
39 check(instr_is_branch_iform(ppc_inst(0x48000000))); in test_branch_iform()
41 check(instr_is_branch_iform(ppc_inst(0x4bffffff))); in test_branch_iform()
43 check(!instr_is_branch_iform(ppc_inst(0xcbffffff))); in test_branch_iform()
45 check(!instr_is_branch_iform(ppc_inst(0x7bffffff))); in test_branch_iform()
48 check(instr_is_branch_iform(ppc_inst(0x48000001))); in test_branch_iform()
50 check(instr_is_branch_iform(ppc_inst(0x4bfffffd))); in test_branch_iform()
52 check(instr_is_branch_iform(ppc_inst(0x4bff00fd))); in test_branch_iform()
54 check(!instr_is_branch_iform(ppc_inst(0x7bfffffd))); in test_branch_iform()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Dimu_v11_0_3.c31 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_RD_COMBINE_FLUSH, 0x00055555, 0xe0000000),
32 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_IO_WR_COMBINE_FLUSH, 0x00055555, 0xe0000000),
33 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_DRAM_COMBINE_FLUSH, 0x00555555, 0xe0000000),
34 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_MISC2, 0x00001ffe, 0xe0000000),
35 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_CREDITS, 0x003f3fff, 0xe0000000),
36 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_TAG_RESERVE1, 0x00000000, 0xe0000000),
37 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE0, 0x00041000, 0xe0000000),
38 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCC_RESERVE1, 0x00000000, 0xe0000000),
39 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE0, 0x00040000, 0xe0000000),
40 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regGUS_SDP_VCD_RESERVE1, 0x00000000, 0xe0000000),
[all …]
/kernel/linux/linux-5.10/arch/powerpc/lib/
Dcode-patching.c29 asm ("dcbst 0, %0; sync; icbi 0,%1; sync; isync" :: "r" (patch_addr), in __patch_instruction()
32 return 0; in __patch_instruction()
58 return 0; in text_area_cpu_up()
64 return 0; in text_area_cpu_down()
81 return 0; in setup_text_poke_area()
104 return 0; in map_patch_area()
143 return 0; in unmap_patch_area()
196 pr_debug("Skipping init section patching addr: 0x%px\n", addr); in patch_instruction()
197 return 0; in patch_instruction()
216 * 0 6 30 31 in is_offset_in_branch_range()
[all …]
/kernel/linux/linux-6.6/Documentation/devicetree/bindings/usb/
Dsnps,dwc3.yaml188 - 0 # -6dB de-emphasis
264 quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
299 minimum: 0
300 maximum: 0x3f
393 port@0:
417 reg = <0x4a030000 0xcfff>;
418 interrupts = <0 92 4>;
425 reg = <0x4a000000 0xcfff>;
426 interrupts = <0 92 4>;
/kernel/linux/linux-5.10/arch/arm64/include/asm/
Dinsn.h22 * 0 0 - - Unallocated
23 * 1 0 0 - Data processing, immediate
24 * 1 0 1 - Branch, exception generation and system instructions
25 * - 1 - 0 Loads and stores
26 * - 1 0 1 Data processing - register
27 * 0 1 1 1 Data processing - SIMD and floating point
42 AARCH64_INSN_HINT_NOP = 0x0 << 5,
43 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
44 AARCH64_INSN_HINT_WFE = 0x2 << 5,
45 AARCH64_INSN_HINT_WFI = 0x3 << 5,
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/ti/omap/
Dam33xx-l4.dtsi1 &l4_wkup { /* 0x44c00000 */
4 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
6 reg = <0x44c00000 0x800>,
7 <0x44c00800 0x800>,
8 <0x44c01000 0x400>,
9 <0x44c01400 0x400>;
13 ranges = <0x00000000 0x44c00000 0x100000>, /* segment 0 */
14 <0x00100000 0x44d00000 0x100000>, /* segment 1 */
15 <0x00200000 0x44e00000 0x100000>; /* segment 2 */
17 segment@0 { /* 0x44c00000 */
[all …]
Domap5-l4.dtsi1 &l4_cfg { /* 0x4a000000 */
4 clocks = <&l4cfg_clkctrl OMAP5_L4_CFG_CLKCTRL 0>;
6 reg = <0x4a000000 0x800>,
7 <0x4a000800 0x800>,
8 <0x4a001000 0x1000>;
12 ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
13 <0x00080000 0x4a080000 0x080000>, /* segment 1 */
14 <0x00100000 0x4a100000 0x080000>, /* segment 2 */
15 <0x00180000 0x4a180000 0x080000>, /* segment 3 */
16 <0x00200000 0x4a200000 0x080000>, /* segment 4 */
[all …]
/kernel/linux/linux-6.6/arch/arm64/include/asm/
Dinsn.h18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
[all …]

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