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/kernel/linux/linux-6.6/drivers/pinctrl/mediatek/
Dpinctrl-mt2712.c20 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
21 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
22 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
23 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
24 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
25 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
27 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
28 MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
29 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
30 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
[all …]
Dpinctrl-mt8127.c19 /* 0E4E8SR 4/8/12/16 */
21 /* 0E2E4SR 2/4/6/8 */
24 MTK_DRV_GRP(2, 16, 0, 2, 2)
28 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
29 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
Dpinctrl-mt8173.c18 #define DRV_BASE 0xb00
21 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
22 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
23 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
24 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
25 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
26 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
28 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
29 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
30 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
[all …]
Dpinctrl-mt6795.c11 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
12 _x_bits, 15, 0)
15 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
16 _x_bits, 16, 0)
19 PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \
23 PIN_FIELD16(0, 196, 0x0, 0x10, 0, 1),
27 PIN_FIELD16(0, 196, 0x100, 0x10, 0, 1),
31 PIN_FIELD16(0, 196, 0x200, 0x10, 0, 1),
35 PIN_FIELD16(0, 196, 0x400, 0x10, 0, 1),
39 PIN_FIELD16(0, 196, 0x500, 0x10, 0, 1),
[all …]
/kernel/linux/linux-5.10/drivers/pinctrl/mediatek/
Dpinctrl-mt2712.c21 MTK_PIN_PUPD_SPEC_SR(18, 0xe50, 2, 1, 0),
22 MTK_PIN_PUPD_SPEC_SR(19, 0xe60, 12, 11, 10),
23 MTK_PIN_PUPD_SPEC_SR(20, 0xe50, 5, 4, 3),
24 MTK_PIN_PUPD_SPEC_SR(21, 0xe60, 15, 14, 13),
25 MTK_PIN_PUPD_SPEC_SR(22, 0xe50, 8, 7, 6),
26 MTK_PIN_PUPD_SPEC_SR(23, 0xe70, 2, 1, 0),
28 MTK_PIN_PUPD_SPEC_SR(30, 0xf30, 2, 1, 0),
29 MTK_PIN_PUPD_SPEC_SR(31, 0xf30, 6, 5, 4),
30 MTK_PIN_PUPD_SPEC_SR(32, 0xf30, 10, 9, 8),
31 MTK_PIN_PUPD_SPEC_SR(33, 0xf30, 14, 13, 12),
[all …]
Dpinctrl-mt8127.c20 /* 0E4E8SR 4/8/12/16 */
22 /* 0E2E4SR 2/4/6/8 */
25 MTK_DRV_GRP(2, 16, 0, 2, 2)
29 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
30 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
31 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
32 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
33 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
34 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
35 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
[all …]
Dpinctrl-mt8173.c19 #define DRV_BASE 0xb00
22 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
23 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
24 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
25 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
26 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
27 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
29 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
30 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
31 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
[all …]
/kernel/linux/linux-6.6/arch/sh/boards/
Dboard-sh7757lcr.c27 .start = 0xffec005c, /* PUDR */
28 .end = 0xffec005c,
32 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
51 #define GBECONT 0xffc10100
56 if (((unsigned long)addr & 0x00000fff) < 0x0800) in sh7757_eth_set_mdio_gate()
64 .start = 0xfef00000,
65 .end = 0xfef001ff,
68 .start = evt2irq(0xc80),
69 .end = evt2irq(0xc80),
82 .id = 0,
[all …]
/kernel/linux/linux-5.10/arch/sh/boards/
Dboard-sh7757lcr.c27 .start = 0xffec005c, /* PUDR */
28 .end = 0xffec005c,
32 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
51 #define GBECONT 0xffc10100
56 if (((unsigned long)addr & 0x00000fff) < 0x0800) in sh7757_eth_set_mdio_gate()
64 .start = 0xfef00000,
65 .end = 0xfef001ff,
68 .start = evt2irq(0xc80),
69 .end = evt2irq(0xc80),
82 .id = 0,
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
Djpeg_v4_0_3.c36 UVD_PGFSM_STATUS__UVDJ_PWR_ON = 0,
75 return 0; in jpeg_v4_0_3_early_init()
91 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
107 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { in jpeg_v4_0_3_sw_init()
110 for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { in jpeg_v4_0_3_sw_init()
129 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0, in jpeg_v4_0_3_sw_init()
140 (j ? (0x40 * j - 0xc80) : 0)); in jpeg_v4_0_3_sw_init()
152 return 0; in jpeg_v4_0_3_sw_init()
191 direct_wt = { {0} }; in jpeg_v4_0_3_start_sriov()
192 struct mmsch_v4_0_cmd_end end = { {0} }; in jpeg_v4_0_3_start_sriov()
[all …]
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7763.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
32 .id = 0,
47 DEFINE_RES_MEM(0xffe08000, 0x100),
48 DEFINE_RES_IRQ(evt2irq(0xb80)),
68 DEFINE_RES_MEM(0xffe10000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0xf00)),
83 [0] = {
84 .start = 0xffe80000,
85 .end = 0xffe80000 + 0x58 - 1,
[all …]
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4a/
Dsetup-sh7763.c26 DEFINE_RES_MEM(0xffe00000, 0x100),
27 DEFINE_RES_IRQ(evt2irq(0x700)),
32 .id = 0,
47 DEFINE_RES_MEM(0xffe08000, 0x100),
48 DEFINE_RES_IRQ(evt2irq(0xb80)),
68 DEFINE_RES_MEM(0xffe10000, 0x100),
69 DEFINE_RES_IRQ(evt2irq(0xf00)),
83 [0] = {
84 .start = 0xffe80000,
85 .end = 0xffe80000 + 0x58 - 1,
[all …]
/kernel/linux/linux-5.10/include/linux/
Deisa.h16 #define EISA_INT1_CTRL 0x20
17 #define EISA_INT1_MASK 0x21
18 #define EISA_INT2_CTRL 0xA0
19 #define EISA_INT2_MASK 0xA1
20 #define EISA_DMA2_STATUS 0xD0
21 #define EISA_DMA2_WRITE_SINGLE 0xD4
22 #define EISA_EXT_NMI_RESET_CTRL 0x461
23 #define EISA_INT1_EDGE_LEVEL 0x4D0
24 #define EISA_INT2_EDGE_LEVEL 0x4D1
25 #define EISA_VENDOR_ID_OFFSET 0xC80
[all …]
/kernel/linux/linux-6.6/include/linux/
Deisa.h16 #define EISA_INT1_CTRL 0x20
17 #define EISA_INT1_MASK 0x21
18 #define EISA_INT2_CTRL 0xA0
19 #define EISA_INT2_MASK 0xA1
20 #define EISA_DMA2_STATUS 0xD0
21 #define EISA_DMA2_WRITE_SINGLE 0xD4
22 #define EISA_EXT_NMI_RESET_CTRL 0x461
23 #define EISA_INT1_EDGE_LEVEL 0x4D0
24 #define EISA_INT2_EDGE_LEVEL 0x4D1
25 #define EISA_VENDOR_ID_OFFSET 0xC80
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
Dtu102.c27 .debug = 0x408,
28 .fbif = 0x600,
32 .emem_addr = 0x01000000,
40 .cmdq = { 0xc00, 0xc04, 8 },
41 .msgq = { 0xc80, 0xc84, 8 },
47 .unit_acr = 0x07,
70 { 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
80 return nvkm_sec2_new_(tu102_sec2_fwif, device, index, 0x840000, psec2); in tu102_sec2_new()
/kernel/linux/linux-6.6/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_csr.h11 #define HINIC_CSR_FUNC_ATTR0_ADDR 0x0
12 #define HINIC_CSR_FUNC_ATTR1_ADDR 0x4
13 #define HINIC_CSR_FUNC_ATTR2_ADDR 0x8
14 #define HINIC_CSR_FUNC_ATTR4_ADDR 0x10
15 #define HINIC_CSR_FUNC_ATTR5_ADDR 0x14
17 #define HINIC_DMA_ATTR_BASE 0xC80
18 #define HINIC_ELECTION_BASE 0x4200
20 #define HINIC_DMA_ATTR_STRIDE 0x4
24 #define HINIC_PPF_ELECTION_STRIDE 0x4
30 #define HINIC_CSR_API_CMD_BASE 0xF000
[all …]
/kernel/linux/linux-5.10/drivers/net/ethernet/huawei/hinic/
Dhinic_hw_csr.h11 #define HINIC_CSR_FUNC_ATTR0_ADDR 0x0
12 #define HINIC_CSR_FUNC_ATTR1_ADDR 0x4
13 #define HINIC_CSR_FUNC_ATTR2_ADDR 0x8
14 #define HINIC_CSR_FUNC_ATTR4_ADDR 0x10
15 #define HINIC_CSR_FUNC_ATTR5_ADDR 0x14
17 #define HINIC_DMA_ATTR_BASE 0xC80
18 #define HINIC_ELECTION_BASE 0x4200
20 #define HINIC_DMA_ATTR_STRIDE 0x4
24 #define HINIC_PPF_ELECTION_STRIDE 0x4
31 #define HINIC_CSR_API_CMD_BASE 0xF000
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/engine/sec2/
Dtu102.c34 .debug = 0x408,
40 .emem_addr = 0x01000000,
43 .cmdq = { 0xc00, 0xc04, 8 },
44 .msgq = { 0xc80, 0xc84, 8 },
74 { 0, gp102_sec2_load, &tu102_sec2, &gp102_sec2_acr_1 },
85 return nvkm_sec2_new_(tu102_sec2_fwif, device, type, inst, 0x840000, psec2); in tu102_sec2_new()
/kernel/linux/linux-6.6/drivers/staging/rtl8192u/
Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8192u/
Dr819xU_phyreg.h5 #define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
9 #define rFPGA0_TxGainStage 0x80c
10 #define rFPGA0_XA_HSSIParameter1 0x820
11 #define rFPGA0_XA_HSSIParameter2 0x824
12 #define rFPGA0_XB_HSSIParameter1 0x828
13 #define rFPGA0_XB_HSSIParameter2 0x82c
14 #define rFPGA0_XC_HSSIParameter1 0x830
15 #define rFPGA0_XC_HSSIParameter2 0x834
16 #define rFPGA0_XD_HSSIParameter1 0x838
[all …]
/kernel/linux/linux-5.10/drivers/staging/rtl8723bs/hal/
Dodm_RegDefine11N.h13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
[all …]
/kernel/linux/linux-6.6/drivers/staging/rtl8723bs/hal/
Dodm_RegDefine11N.h13 #define ODM_REG_RF_MODE_11N 0x00
14 #define ODM_REG_RF_0B_11N 0x0B
15 #define ODM_REG_CHNBW_11N 0x18
16 #define ODM_REG_T_METER_11N 0x24
17 #define ODM_REG_RF_25_11N 0x25
18 #define ODM_REG_RF_26_11N 0x26
19 #define ODM_REG_RF_27_11N 0x27
20 #define ODM_REG_RF_2B_11N 0x2B
21 #define ODM_REG_RF_2C_11N 0x2C
22 #define ODM_REG_RXRF_A3_11N 0x3C
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
Ddm.h11 #define MF_USC_LSC 0
14 #define MAIN_ANT 0
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
[all …]
/kernel/linux/linux-5.10/drivers/net/wireless/realtek/rtlwifi/rtl8192ee/
Ddm.h11 #define MF_USC_LSC 0
14 #define MAIN_ANT 0
17 #define AUX_ANT_CG_TRX 0
18 #define MAIN_ANT_CGCS_RX 0
22 #define DM_REG_RF_MODE_11N 0x00
23 #define DM_REG_RF_0B_11N 0x0B
24 #define DM_REG_CHNBW_11N 0x18
25 #define DM_REG_T_METER_11N 0x24
26 #define DM_REG_RF_25_11N 0x25
27 #define DM_REG_RF_26_11N 0x26
[all …]
/kernel/linux/linux-6.6/drivers/net/wireless/realtek/rtlwifi/rtl8188ee/
Ddm.h7 #define MAIN_ANT 0
10 #define AUX_ANT_CG_TRX 0
11 #define MAIN_ANT_CGCS_RX 0
15 #define DM_REG_RF_MODE_11N 0x00
16 #define DM_REG_RF_0B_11N 0x0B
17 #define DM_REG_CHNBW_11N 0x18
18 #define DM_REG_T_METER_11N 0x24
19 #define DM_REG_RF_25_11N 0x25
20 #define DM_REG_RF_26_11N 0x26
21 #define DM_REG_RF_27_11N 0x27
[all …]

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