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/kernel/linux/linux-5.10/include/misc/
Docxl-config.h13 #define OCXL_EXT_CAP_ID_DVSEC 0x23
15 #define OCXL_DVSEC_VENDOR_OFFSET 0x4
16 #define OCXL_DVSEC_ID_OFFSET 0x8
17 #define OCXL_DVSEC_TL_ID 0xF000
18 #define OCXL_DVSEC_TL_BACKOFF_TIMERS 0x10
19 #define OCXL_DVSEC_TL_RECV_CAP 0x18
20 #define OCXL_DVSEC_TL_SEND_CAP 0x20
21 #define OCXL_DVSEC_TL_RECV_RATE 0x30
22 #define OCXL_DVSEC_TL_SEND_RATE 0x50
23 #define OCXL_DVSEC_FUNC_ID 0xF001
[all …]
/kernel/linux/linux-6.6/include/misc/
Docxl-config.h13 #define OCXL_EXT_CAP_ID_DVSEC 0x23
15 #define OCXL_DVSEC_VENDOR_OFFSET 0x4
16 #define OCXL_DVSEC_ID_OFFSET 0x8
17 #define OCXL_DVSEC_TL_ID 0xF000
18 #define OCXL_DVSEC_TL_BACKOFF_TIMERS 0x10
19 #define OCXL_DVSEC_TL_RECV_CAP 0x18
20 #define OCXL_DVSEC_TL_SEND_CAP 0x20
21 #define OCXL_DVSEC_TL_RECV_RATE 0x30
22 #define OCXL_DVSEC_TL_SEND_RATE 0x50
23 #define OCXL_DVSEC_FUNC_ID 0xF001
[all …]
/kernel/linux/linux-5.10/sound/soc/codecs/
Dwm2000.h9 #define WM2000_REG_SYS_START 0x8000
10 #define WM2000_REG_ANC_GAIN_CTRL 0x8fa2
11 #define WM2000_REG_MSE_TH2 0x8fdf
12 #define WM2000_REG_MSE_TH1 0x8fe0
13 #define WM2000_REG_SPEECH_CLARITY 0x8fef
14 #define WM2000_REG_SYS_WATCHDOG 0x8ff6
15 #define WM2000_REG_ANA_VMID_PD_TIME 0x8ff7
16 #define WM2000_REG_ANA_VMID_PU_TIME 0x8ff8
17 #define WM2000_REG_CAT_FLTR_INDX 0x8ff9
18 #define WM2000_REG_CAT_GAIN_0 0x8ffa
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/kernel/linux/linux-6.6/sound/soc/codecs/
Dwm2000.h9 #define WM2000_REG_SYS_START 0x8000
10 #define WM2000_REG_ANC_GAIN_CTRL 0x8fa2
11 #define WM2000_REG_MSE_TH2 0x8fdf
12 #define WM2000_REG_MSE_TH1 0x8fe0
13 #define WM2000_REG_SPEECH_CLARITY 0x8fef
14 #define WM2000_REG_SYS_WATCHDOG 0x8ff6
15 #define WM2000_REG_ANA_VMID_PD_TIME 0x8ff7
16 #define WM2000_REG_ANA_VMID_PU_TIME 0x8ff8
17 #define WM2000_REG_CAT_FLTR_INDX 0x8ff9
18 #define WM2000_REG_CAT_GAIN_0 0x8ffa
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/kernel/linux/linux-5.10/drivers/gpu/drm/ast/
Dast_main.c76 *scu_rev = 0xffffffff; in ast_detect_config_mode()
92 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge in ast_detect_config_mode()
96 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_detect_config_mode()
97 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); in ast_detect_config_mode()
98 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { in ast_detect_config_mode()
100 data = ast_read32(ast, 0xf004); in ast_detect_config_mode()
101 if ((data != 0xFFFFFFFF) && (data != 0x00)) { in ast_detect_config_mode()
108 ast_write32(ast, 0xf004, 0x1e6e0000); in ast_detect_config_mode()
109 ast_write32(ast, 0xf000, 0x1); in ast_detect_config_mode()
110 *scu_rev = ast_read32(ast, 0x1207c); in ast_detect_config_mode()
[all …]
Dast_dp501.c34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
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Dast_post.c44 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); in ast_enable_vga()
45 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); in ast_enable_vga()
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_enable_mmio()
63 return !!(ch & 0x01); in ast_is_vga_enabled()
66 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
67 static const u8 extreginfo_ast2300a0[] = { 0x0f, 0x04, 0x1c, 0xff };
68 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
78 for (i = 0x81; i <= 0x9f; i++) in ast_set_def_ext_reg()
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
83 if (dev->pdev->revision >= 0x20) in ast_set_def_ext_reg()
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/kernel/linux/linux-6.6/drivers/gpu/drm/ast/
Dast_main.c45 return !!(ch & 0x01); in ast_is_vga_enabled()
52 ast_io_write8(ast, AST_IO_VGA_ENABLE_PORT, 0x01); in ast_enable_vga()
53 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, 0x01); in ast_enable_vga()
65 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); in ast_enable_mmio_release()
72 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06); in ast_enable_mmio()
79 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8); in ast_open_key()
87 uint32_t scu_rev = 0xffffffff; in ast_device_config_init()
104 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge in ast_device_config_init()
108 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); in ast_device_config_init()
109 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); in ast_device_config_init()
[all …]
Dast_dp501.c34 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_ack()
35 sendack |= 0x80; in send_ack()
36 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_ack()
42 sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff); in send_nack()
43 sendack &= ~0x80; in send_nack()
44 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack); in send_nack()
50 u32 retry = 0; in wait_ack()
52 waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff); in wait_ack()
53 waitack &= 0x80; in wait_ack()
66 u32 retry = 0; in wait_nack()
[all …]
Dast_post.c40 static const u8 extreginfo[] = { 0x0f, 0x04, 0x1c, 0xff };
41 static const u8 extreginfo_ast2300[] = { 0x0f, 0x04, 0x1f, 0xff };
51 for (i = 0x81; i <= 0x9f; i++) in ast_set_def_ext_reg()
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00); in ast_set_def_ext_reg()
59 index = 0xa0; in ast_set_def_ext_reg()
60 while (*ext_reg_info != 0xff) { in ast_set_def_ext_reg()
61 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info); in ast_set_def_ext_reg()
67 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */ in ast_set_def_ext_reg()
70 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01); in ast_set_def_ext_reg()
71 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00); in ast_set_def_ext_reg()
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
Di915_reg_defs.h14 * @__n: 0-based bit number
23 ((__n) < 0 || (__n) > 31))))
27 * @__n: 0-based bit number
36 ((__n) < 0 || (__n) > 7))))
40 * @__high: 0-based high bit
41 * @__low: 0-based low bit
51 ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
55 * @__high: 0-based high bit
56 * @__low: 0-based low bit
66 ((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
[all …]
/kernel/linux/linux-6.6/drivers/dma/ti/
Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
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Dk3-psil-j721s2.c63 PSIL_PDMA_MCASP(0x4400),
64 PSIL_PDMA_MCASP(0x4401),
65 PSIL_PDMA_MCASP(0x4402),
66 PSIL_PDMA_MCASP(0x4403),
67 PSIL_PDMA_MCASP(0x4404),
69 PSIL_PDMA_XY_PKT(0x4600),
70 PSIL_PDMA_XY_PKT(0x4601),
71 PSIL_PDMA_XY_PKT(0x4602),
72 PSIL_PDMA_XY_PKT(0x4603),
73 PSIL_PDMA_XY_PKT(0x4604),
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Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
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/kernel/linux/linux-5.10/drivers/dma/ti/
Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
Dk3-psil-j7200.c64 PSIL_PDMA_MCASP(0x4400),
65 PSIL_PDMA_MCASP(0x4401),
66 PSIL_PDMA_MCASP(0x4402),
68 PSIL_PDMA_XY_PKT(0x4600),
69 PSIL_PDMA_XY_PKT(0x4601),
70 PSIL_PDMA_XY_PKT(0x4602),
71 PSIL_PDMA_XY_PKT(0x4603),
72 PSIL_PDMA_XY_PKT(0x4604),
73 PSIL_PDMA_XY_PKT(0x4605),
74 PSIL_PDMA_XY_PKT(0x4606),
[all …]
Dk3-psil-j721e.c64 PSIL_SA2UL(0x4000, 0),
65 PSIL_SA2UL(0x4001, 0),
66 PSIL_SA2UL(0x4002, 0),
67 PSIL_SA2UL(0x4003, 0),
69 PSIL_ETHERNET(0x4100),
70 PSIL_ETHERNET(0x4101),
71 PSIL_ETHERNET(0x4102),
72 PSIL_ETHERNET(0x4103),
74 PSIL_ETHERNET(0x4200),
75 PSIL_ETHERNET(0x4201),
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/kernel/linux/linux-5.10/include/linux/
Dsdla.h25 #define SDLA_CONTROL_WND 0xE000
27 #define SDLA_502_CMD_BUF 0xEF60
28 #define SDLA_502_RCV_BUF 0xA900
29 #define SDLA_502_TXN_AVAIL 0xFFF1
30 #define SDLA_502_RCV_AVAIL 0xFFF2
31 #define SDLA_502_EVENT_FLAGS 0xFFF3
32 #define SDLA_502_MDM_STATUS 0xFFF4
33 #define SDLA_502_IRQ_INTERFACE 0xFFFD
34 #define SDLA_502_IRQ_PERMISSION 0xFFFE
35 #define SDLA_502_DATA_OFS 0x0010
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/kernel/linux/linux-5.10/arch/arm/mach-s5pv210/
Dregs-clock.h12 #define S3C_ADDR_BASE 0xF6000000
14 #define S3C_VA_SYS S3C_ADDR(0x00100000)
18 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
19 #define S5P_MPLL_LOCK S5P_CLKREG(0x08)
20 #define S5P_EPLL_LOCK S5P_CLKREG(0x10)
21 #define S5P_VPLL_LOCK S5P_CLKREG(0x20)
23 #define S5P_APLL_CON S5P_CLKREG(0x100)
24 #define S5P_MPLL_CON S5P_CLKREG(0x108)
25 #define S5P_EPLL_CON S5P_CLKREG(0x110)
26 #define S5P_EPLL_CON1 S5P_CLKREG(0x114)
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/kernel/linux/linux-6.6/arch/arm/mach-s5pv210/
Dregs-clock.h12 #define S3C_ADDR_BASE 0xF6000000
14 #define S3C_VA_SYS S3C_ADDR(0x00100000)
18 #define S5P_APLL_LOCK S5P_CLKREG(0x00)
19 #define S5P_MPLL_LOCK S5P_CLKREG(0x08)
20 #define S5P_EPLL_LOCK S5P_CLKREG(0x10)
21 #define S5P_VPLL_LOCK S5P_CLKREG(0x20)
23 #define S5P_APLL_CON S5P_CLKREG(0x100)
24 #define S5P_MPLL_CON S5P_CLKREG(0x108)
25 #define S5P_EPLL_CON S5P_CLKREG(0x110)
26 #define S5P_EPLL_CON1 S5P_CLKREG(0x114)
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/kernel/linux/linux-6.6/sound/soc/intel/catpt/
Dregisters.h22 #define CATPT_SHIM_CS1 0x00
23 #define CATPT_SHIM_ISC 0x18
24 #define CATPT_SHIM_ISD 0x20
25 #define CATPT_SHIM_IMC 0x28
26 #define CATPT_SHIM_IMD 0x30
27 #define CATPT_SHIM_IPCC 0x38
28 #define CATPT_SHIM_IPCD 0x40
29 #define CATPT_SHIM_CLKCTL 0x78
30 #define CATPT_SHIM_CS2 0x80
31 #define CATPT_SHIM_LTRC 0xE0
[all …]
/kernel/linux/linux-5.10/sound/soc/intel/catpt/
Dregisters.h22 #define CATPT_SHIM_CS1 0x00
23 #define CATPT_SHIM_ISC 0x18
24 #define CATPT_SHIM_ISD 0x20
25 #define CATPT_SHIM_IMC 0x28
26 #define CATPT_SHIM_IMD 0x30
27 #define CATPT_SHIM_IPCC 0x38
28 #define CATPT_SHIM_IPCD 0x40
29 #define CATPT_SHIM_CLKCTL 0x78
30 #define CATPT_SHIM_CS2 0x80
31 #define CATPT_SHIM_LTRC 0xE0
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/kernel/linux/linux-6.6/include/linux/mtd/
Donenand_regs.h20 #define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
21 #define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
22 #define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
27 #define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
28 #define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
29 #define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
30 #define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
31 #define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
32 #define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
33 #define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
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/kernel/linux/linux-5.10/include/linux/mtd/
Donenand_regs.h20 #define ONENAND_BOOTRAM ONENAND_MEMORY_MAP(0x0000)
21 #define ONENAND_DATARAM ONENAND_MEMORY_MAP(0x0200)
22 #define ONENAND_SPARERAM ONENAND_MEMORY_MAP(0x8010)
27 #define ONENAND_REG_MANUFACTURER_ID ONENAND_MEMORY_MAP(0xF000)
28 #define ONENAND_REG_DEVICE_ID ONENAND_MEMORY_MAP(0xF001)
29 #define ONENAND_REG_VERSION_ID ONENAND_MEMORY_MAP(0xF002)
30 #define ONENAND_REG_DATA_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF003)
31 #define ONENAND_REG_BOOT_BUFFER_SIZE ONENAND_MEMORY_MAP(0xF004)
32 #define ONENAND_REG_NUM_BUFFERS ONENAND_MEMORY_MAP(0xF005)
33 #define ONENAND_REG_TECHNOLOGY ONENAND_MEMORY_MAP(0xF006)
[all …]
/kernel/linux/linux-6.6/Documentation/ABI/testing/
Dsysfs-devices-platform-stratix10-rsu3 What: /sys/devices/platform/stratix10-rsu.0/current_image
10 What: /sys/devices/platform/stratix10-rsu.0/fail_image
17 What: /sys/devices/platform/stratix10-rsu.0/state
26 b[15:0]
27 Currently used only when major error is 0xF006
34 0xF001 bitstream error
35 0xF002 hardware access failure
36 0xF003 bitstream corruption
37 0xF004 internal error
38 0xF005 device error
[all …]

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