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/kernel/linux/linux-6.6/Documentation/devicetree/bindings/display/msm/
Ddsi-phy-20nm.yaml53 reg = <0xfd922a00 0xd4>,
54 <0xfd922b00 0x2b0>,
55 <0xfd922d80 0x7b>;
61 #phy-cells = <0>;
Ddsi-phy-28nm.yaml58 reg = <0xfd922a00 0xd4>,
59 <0xfd922b00 0x2b0>,
60 <0xfd922d80 0x7b>;
66 #phy-cells = <0>;
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_28nm.c39 DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0)); in dsi_28nm_dphy_set_timing()
46 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); in dsi_28nm_phy_regulator_enable_dcdc()
48 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); in dsi_28nm_phy_regulator_enable_dcdc()
49 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); in dsi_28nm_phy_regulator_enable_dcdc()
50 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3); in dsi_28nm_phy_regulator_enable_dcdc()
51 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); in dsi_28nm_phy_regulator_enable_dcdc()
52 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); in dsi_28nm_phy_regulator_enable_dcdc()
53 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20); in dsi_28nm_phy_regulator_enable_dcdc()
54 dsi_phy_write(phy->base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00); in dsi_28nm_phy_regulator_enable_dcdc()
61 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); in dsi_28nm_phy_regulator_enable_ldo()
[all …]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
Ddsi_cfg.c13 .io_offset = 0,
24 .io_start = { 0x4700000, 0x5800000 },
45 .io_start = { 0xfd922800, 0xfd922b00 },
65 .io_start = { 0x1a98000 },
85 .io_start = { 0x1a94000, 0x1a96000 },
105 .io_start = { 0xfd998000, 0xfd9a0000 },
129 .io_start = { 0x994000, 0x996000 },
148 .io_start = { 0xc994000, 0xc996000 },
166 .io_start = { 0xc994000, 0xc996000 },
188 .io_start = { 0xae94000, 0xae96000 },
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
Ddsi_cfg.c19 .io_offset = 0,
25 { 0x4700000, 0x5800000 },
46 { 0xfd922800, 0xfd922b00 },
66 { 0x1a98000 },
77 { 0x1a94000, 0x1a96000 },
97 { 0xfd998000, 0xfd9a0000 },
114 { 0x994000, 0x996000 },
134 { 0xc994000, 0xc996000 },
153 { 0xc994000, 0xc996000 },
173 { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */
[all …]
/kernel/linux/linux-5.10/Documentation/devicetree/bindings/display/msm/
Ddsi.txt23 For DSI6G v2.0 onwards, we need also need the clock:
38 - panel@0: Node of panel connected to this DSI controller.
47 - pinctrl-0: the default pinctrl state (active)
53 - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
60 (DATAn, where n lies between 0 and 3). The clock lane position is fixed
66 data-lanes = <3 0 1 2>;
73 <0 1 2 3>
74 <1 2 3 0>
75 <2 3 0 1>
76 <3 0 1 2>
[all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_28nm.c39 #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0)
109 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); in pll_28nm_software_reset()
134 for (i = 0; i < LPFR_LUT_SIZE; i++) in dsi_pll_28nm_clk_set_rate()
145 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70); in dsi_pll_28nm_clk_set_rate()
146 dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15); in dsi_pll_28nm_clk_set_rate()
155 refclk_cfg = 0x0; in dsi_pll_28nm_clk_set_rate()
156 frac_n_mode = 0; in dsi_pll_28nm_clk_set_rate()
170 rem = 0; in dsi_pll_28nm_clk_set_rate()
174 sdm_cfg0 = 0x0; in dsi_pll_28nm_clk_set_rate()
175 sdm_cfg0 |= DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV(0); in dsi_pll_28nm_clk_set_rate()
[all …]
/kernel/linux/linux-6.6/arch/arm/boot/dts/qcom/
Dqcom-msm8226.dtsi23 memory@0 {
25 reg = <0x0 0x0>;
31 #clock-cells = <0>;
37 #clock-cells = <0>;
61 qcom,ipc = <&apcs 8 0>;
113 reg = <0x3000000 0x100000>;
118 reg = <0x0dc00000 0x1900000>;
141 qcom,local-pid = <0>;
165 reg = <0xf9000000 0x1000>,
166 <0xf9002000 0x1000>;
[all …]
Dqcom-msm8974.dtsi20 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #size-cells = <0>;
34 interrupts = <GIC_PPI 9 0xf04>;
36 CPU0: cpu@0 {
40 reg = <0>;
108 reg = <0x0 0x0>;
113 interrupts = <GIC_PPI 7 0xf04>;
121 qcom,ipc = <&apcs 8 0>;
144 reg = <0x08000000 0x5100000>;
[all …]
/kernel/linux/linux-5.10/arch/arm/boot/dts/
Dqcom-msm8974.dtsi25 reg = <0x08000000 0x5100000>;
30 reg = <0x0d100000 0x100000>;
35 reg = <0x0d200000 0xa00000>;
40 reg = <0x0dc00000 0x1900000>;
45 reg = <0x0f500000 0x500000>;
50 reg = <0xfa00000 0x200000>;
55 reg = <0x0fc00000 0x160000>;
60 reg = <0x0fd60000 0x20000>;
66 reg = <0x0fd80000 0x180000>;
75 #size-cells = <0>;
[all …]