Searched +full:0 +full:xfeb00000 (Results 1 – 25 of 54) sorted by relevance
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15 #define SP5100_WDT_MEM_MAP_SIZE 0x0816 #define SP5100_WDT_CONTROL(base) ((base) + 0x00) /* Watchdog Control */17 #define SP5100_WDT_COUNT(base) ((base) + 0x04) /* Watchdog Count */19 #define SP5100_WDT_START_STOP_BIT BIT(0)25 #define SP5100_PM_IOPORTS_SIZE 0x0233 #define SP5100_IO_PM_INDEX_REG 0xCD634 #define SP5100_IO_PM_DATA_REG 0xCD737 #define SP5100_SB_RESOURCE_MMIO_BASE 0x9C39 #define SP5100_PM_WATCHDOG_CONTROL 0x6940 #define SP5100_PM_WATCHDOG_BASE 0x6C[all …]
74 R8A7742 (RZ/G1H) DPAD 0 LVDS 0 LVDS 1 -75 R8A7743 (RZ/G1M) DPAD 0 LVDS 0 - -76 R8A7744 (RZ/G1N) DPAD 0 LVDS 0 - -77 R8A7745 (RZ/G1E) DPAD 0 DPAD 1 - -78 R8A77470 (RZ/G1C) DPAD 0 DPAD 1 LVDS 0 -79 R8A774A1 (RZ/G2M) DPAD 0 HDMI 0 LVDS 0 -80 R8A774B1 (RZ/G2N) DPAD 0 HDMI 0 LVDS 0 -81 R8A774C0 (RZ/G2E) DPAD 0 LVDS 0 LVDS 1 -82 R8A774E1 (RZ/G2H) DPAD 0 HDMI 0 LVDS 0 -83 R8A7779 (R-Car H1) DPAD 0 DPAD 1 - -[all …]
68 "^port@[0-3]$":73 - port@0121 - const: du.0133 port@0:134 description: DPAD 0142 - port@0170 - const: du.0183 - const: du.0187 port@0:188 description: DPAD 0[all …]
40 #clock-cells = <0>;42 clock-frequency = <0>;47 #size-cells = <0>;50 cpu0: cpu@0 {53 reg = <0>;70 L2_CA15: cache-controller-0 {81 #clock-cells = <0>;83 clock-frequency = <0>;96 #clock-cells = <0>;98 clock-frequency = <0>;[all …]
27 #size-cells = <0>;30 cpu0: cpu@0 {33 reg = <0>;50 L2_CA7: cache-controller-0 {61 #clock-cells = <0>;63 clock-frequency = <0>;76 #clock-cells = <0>;78 clock-frequency = <0>;92 reg = <0 0xe6020000 0 0x0c>;102 reg = <0 0xe6050000 0 0x50>;[all …]
34 * The external audio clocks are configured as 0 Hz fixed frequency40 #clock-cells = <0>;41 clock-frequency = <0>;45 #clock-cells = <0>;46 clock-frequency = <0>;50 #clock-cells = <0>;51 clock-frequency = <0>;57 #clock-cells = <0>;59 clock-frequency = <0>;64 #size-cells = <0>;[all …]
32 * The external audio clocks are configured as 0 Hz fixed frequency38 #clock-cells = <0>;39 clock-frequency = <0>;43 #clock-cells = <0>;44 clock-frequency = <0>;48 #clock-cells = <0>;49 clock-frequency = <0>;55 #clock-cells = <0>;57 clock-frequency = <0>;62 #size-cells = <0>;[all …]
36 * The external audio clocks are configured as 0 Hz fixed42 #clock-cells = <0>;43 clock-frequency = <0>;47 #clock-cells = <0>;48 clock-frequency = <0>;52 #clock-cells = <0>;53 clock-frequency = <0>;59 #clock-cells = <0>;61 clock-frequency = <0>;66 #size-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;30 #clock-cells = <0>;31 clock-frequency = <0>;35 #clock-cells = <0>;36 clock-frequency = <0>;42 #clock-cells = <0>;44 clock-frequency = <0>;49 #size-cells = <0>;[all …]
40 * The external audio clocks are configured as 0 Hz fixed frequency46 #clock-cells = <0>;47 clock-frequency = <0>;51 #clock-cells = <0>;52 clock-frequency = <0>;56 #clock-cells = <0>;57 clock-frequency = <0>;63 #clock-cells = <0>;65 clock-frequency = <0>;70 #size-cells = <0>;[all …]
40 #clock-cells = <0>;42 clock-frequency = <0>;47 #size-cells = <0>;49 cpu0: cpu@0 {52 reg = <0>;71 L2_CA15: cache-controller-0 {82 #clock-cells = <0>;84 clock-frequency = <0>;97 #clock-cells = <0>;99 clock-frequency = <0>;[all …]
27 #size-cells = <0>;29 cpu0: cpu@0 {32 reg = <0>;51 L2_CA7: cache-controller-0 {62 #clock-cells = <0>;64 clock-frequency = <0>;77 #clock-cells = <0>;79 clock-frequency = <0>;93 reg = <0 0xe6020000 0 0x0c>;104 reg = <0 0xe6050000 0 0x50>;[all …]
21 #clock-cells = <0>;22 clock-frequency = <0>;27 #size-cells = <0>;29 a53_0: cpu@0 {31 reg = <0x0>;48 #clock-cells = <0>;50 clock-frequency = <0>;65 #clock-cells = <0>;66 clock-frequency = <0>;79 reg = <0 0xe6020000 0 0x0c>;[all …]
30 #clock-cells = <0>;31 clock-frequency = <0>;36 #size-cells = <0>;38 a53_0: cpu@0 {41 reg = <0>;68 #clock-cells = <0>;70 clock-frequency = <0>;75 #clock-cells = <0>;77 clock-frequency = <0>;95 #clock-cells = <0>;[all …]
31 #clock-cells = <0>;32 clock-frequency = <0>;37 #size-cells = <0>;39 a53_0: cpu@0 {42 reg = <0>;89 #clock-cells = <0>;91 clock-frequency = <0>;96 #clock-cells = <0>;98 clock-frequency = <0>;104 #clock-cells = <0>;[all …]
22 #clock-cells = <0>;23 clock-frequency = <0>;28 #size-cells = <0>;30 a53_0: cpu@0 {33 reg = <0>;60 #clock-cells = <0>;62 clock-frequency = <0>;67 #clock-cells = <0>;69 clock-frequency = <0>;87 #clock-cells = <0>;[all …]
22 #clock-cells = <0>;23 clock-frequency = <0>;28 #size-cells = <0>;30 a53_0: cpu@0 {33 reg = <0>;80 #clock-cells = <0>;82 clock-frequency = <0>;87 #clock-cells = <0>;89 clock-frequency = <0>;95 #clock-cells = <0>;[all …]
19 * The external audio clocks are configured as 0 Hz fixed frequency25 #clock-cells = <0>;26 clock-frequency = <0>;31 #clock-cells = <0>;32 clock-frequency = <0>;38 #clock-cells = <0>;39 clock-frequency = <0>;44 #size-cells = <0>;46 a53_0: cpu@0 {48 reg = <0x0>;[all …]
138 0x80000000 | 0xf0000000 | UART0139 0x80004000 | 0xf0004000 | UART1140 0x80008000 | 0xf0008000 | UART2141 0x8000c000 | 0xf000c000 | UART3142 0x80010000 | 0xf0010000 | UART4143 0x80014000 | 0xf0014000 | UART5144 0x80018000 | 0xf0018000 | UART6145 0x8001c000 | 0xf001c000 | UART7146 0x80020000 | 0xf0020000 | UART8147 0x80024000 | 0xf0024000 | UART9[all …]
149 0x80000000 | 0xf0000000 | UART0150 0x80004000 | 0xf0004000 | UART1151 0x80008000 | 0xf0008000 | UART2152 0x8000c000 | 0xf000c000 | UART3153 0x80010000 | 0xf0010000 | UART4154 0x80014000 | 0xf0014000 | UART5155 0x80018000 | 0xf0018000 | UART6156 0x8001c000 | 0xf001c000 | UART7157 0x80020000 | 0xf0020000 | UART8158 0x80024000 | 0xf0024000 | UART9[all …]