0xff0000 (full) in projects: kernel - OpenGrok search results

Project(s)

Full Search
Definition
Symbol
File Path
History
Type

Searched +full:0 +full:xff0000 (Results 1 – 25 of 416) sorted by relevance

12 3 4 5 6 7 8 9 10 >>...17

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/gmc/
D	gmc_7_1_sh_mask.h	`27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]`
D	gmc_8_1_sh_mask.h	`27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]`
D	gmc_7_0_sh_mask.h	`27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30 36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4 [all …]`
D	gmc_8_2_sh_mask.h	`27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]`
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/gmc/
D	gmc_7_1_sh_mask.h	`27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]`
D	gmc_8_1_sh_mask.h	`27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]`
D	gmc_7_0_sh_mask.h	`27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MC_RD_ENABLE_MASK 0x30 36 #define MC_CONFIG__MC_RD_ENABLE__SHIFT 0x4 [all …]`
D	gmc_8_2_sh_mask.h	`27 #define MC_CONFIG__MCDW_WR_ENABLE_MASK 0x1 28 #define MC_CONFIG__MCDW_WR_ENABLE__SHIFT 0x0 29 #define MC_CONFIG__MCDX_WR_ENABLE_MASK 0x2 30 #define MC_CONFIG__MCDX_WR_ENABLE__SHIFT 0x1 31 #define MC_CONFIG__MCDY_WR_ENABLE_MASK 0x4 32 #define MC_CONFIG__MCDY_WR_ENABLE__SHIFT 0x2 33 #define MC_CONFIG__MCDZ_WR_ENABLE_MASK 0x8 34 #define MC_CONFIG__MCDZ_WR_ENABLE__SHIFT 0x3 35 #define MC_CONFIG__MCDS_WR_ENABLE_MASK 0x10 36 #define MC_CONFIG__MCDS_WR_ENABLE__SHIFT 0x4 [all …]`
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/include/asic_reg/smu/
D	smu_7_1_2_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
D	smu_7_1_3_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f 32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0 33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780 34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7 35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800 36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb [all …]
D	smu_7_0_0_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
D	smu_7_0_1_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
D	smu_7_1_0_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
D	smu_7_1_1_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/include/asic_reg/smu/
D	smu_7_1_2_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
D	smu_7_1_3_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define GCK_MCLK_FUSES__StartupMClkDid_MASK 0x7f 32 #define GCK_MCLK_FUSES__StartupMClkDid__SHIFT 0x0 33 #define GCK_MCLK_FUSES__MClkADCA_MASK 0x780 34 #define GCK_MCLK_FUSES__MClkADCA__SHIFT 0x7 35 #define GCK_MCLK_FUSES__MClkDDCA_MASK 0x1800 36 #define GCK_MCLK_FUSES__MClkDDCA__SHIFT 0xb [all …]
D	smu_7_0_0_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
D	smu_7_0_1_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
D	smu_7_1_0_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
D	smu_7_1_1_sh_mask.h	27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff 28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0 29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff 30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0 31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f 32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0 33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100 34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8 35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200 36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9 [all …]
/kernel/linux/linux-5.10/drivers/infiniband/hw/efa/
D	efa_regs_defs.h	`10 EFA_REGS_RESET_NORMAL = 0, 24 /* 0 base */ 25 #define EFA_REGS_VERSION_OFF 0x0 26 #define EFA_REGS_CONTROLLER_VERSION_OFF 0x4 27 #define EFA_REGS_CAPS_OFF 0x8 28 #define EFA_REGS_AQ_BASE_LO_OFF 0x10 29 #define EFA_REGS_AQ_BASE_HI_OFF 0x14 30 #define EFA_REGS_AQ_CAPS_OFF 0x18 31 #define EFA_REGS_ACQ_BASE_LO_OFF 0x20 32 #define EFA_REGS_ACQ_BASE_HI_OFF 0x24 [all …]`
/kernel/linux/linux-6.6/drivers/infiniband/hw/efa/
D	efa_regs_defs.h	`10 EFA_REGS_RESET_NORMAL = 0, 24 /* 0 base */ 25 #define EFA_REGS_VERSION_OFF 0x0 26 #define EFA_REGS_CONTROLLER_VERSION_OFF 0x4 27 #define EFA_REGS_CAPS_OFF 0x8 28 #define EFA_REGS_AQ_BASE_LO_OFF 0x10 29 #define EFA_REGS_AQ_BASE_HI_OFF 0x14 30 #define EFA_REGS_AQ_CAPS_OFF 0x18 31 #define EFA_REGS_ACQ_BASE_LO_OFF 0x20 32 #define EFA_REGS_ACQ_BASE_HI_OFF 0x24 [all …]`
/kernel/linux/linux-5.10/drivers/staging/comedi/drivers/
D	pcm3724.c	`23 * [0] - I/O port base address 40 #define PCM3724_8255_0_BASE 0x00 41 #define PCM3724_8255_1_BASE 0x04 42 #define PCM3724_DIO_DIR_REG 0x08 43 #define PCM3724_DIO_DIR_C0_OUT BIT(0) 49 #define PCM3724_GATE_CTRL_REG 0x09 50 #define PCM3724_GATE_CTRL_C0_ENA BIT(0) 66 if (s->io_bits & 0x0000ff) { in compute_buffer() 67 if (devno == 0) in compute_buffer() 72 if (s->io_bits & 0x00ff00) { in compute_buffer() [all …]`
/kernel/linux/linux-6.6/drivers/comedi/drivers/
D	pcm3724.c	`23 * [0] - I/O port base address 39 #define PCM3724_8255_0_BASE 0x00 40 #define PCM3724_8255_1_BASE 0x04 41 #define PCM3724_DIO_DIR_REG 0x08 42 #define PCM3724_DIO_DIR_C0_OUT BIT(0) 48 #define PCM3724_GATE_CTRL_REG 0x09 49 #define PCM3724_GATE_CTRL_C0_ENA BIT(0) 65 if (s->io_bits & 0x0000ff) { in compute_buffer() 66 if (devno == 0) in compute_buffer() 71 if (s->io_bits & 0x00ff00) { in compute_buffer() [all …]`
/kernel/linux/linux-6.6/drivers/accel/habanalabs/include/gaudi2/asic_reg/
D	dcore0_edma0_qm_masks.h	24 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 25 #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF 27 #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 29 #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 31 #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000 34 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 35 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF 37 #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 39 #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 41 #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 [all …]

12 3 4 5 6 7 8 9 10 >>...17